CN105629154A - Chip top metal cover circuit test realization method and device - Google Patents
Chip top metal cover circuit test realization method and device Download PDFInfo
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- CN105629154A CN105629154A CN201510994235.1A CN201510994235A CN105629154A CN 105629154 A CN105629154 A CN 105629154A CN 201510994235 A CN201510994235 A CN 201510994235A CN 105629154 A CN105629154 A CN 105629154A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/2851—Testing of integrated circuits [IC]
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Abstract
The invention discloses a chip top metal cover test realization method and device. The method comprises the steps that a part of metal wires are selected from all the metal wires of a top metal cover circuit in successive batches to perform input data signal overturning; when input data signal overturning of each batch of metal wires is completed, comparative analysis is performed on the input data and the output data of all the metal wires; and summarization is performed according to the comparative analysis result of the input data and the output data of all batches, and normality of the function of the top metal cover circuit is determined according to the summarization result. According to the method, a part of metal wires are selected in successive batches to perform input data signal overturning, comparative analysis is performed on the input data and the output data of all batches of signal overturning, and judgment of normality of the function of the top metal cover circuit is realized through a logical integrity circuit so that test cost of the top metal cover circuit is reduced and work efficiency of testing of the top metal cover circuit is enhanced.
Description
Technical Field
The present invention relates to circuit testing technology, and is especially method and device for realizing top metal covering circuit test of chip.
Background
The metal covering of the top layer of the chip is one of the design methods of the high-security smart card chip. By covering a layer of metal medium on the top layer of the chip, the bottom layer circuit and the signal of the chip can be effectively protected from being attacked by external malicious attacks. Due to the fact that the function of the top metal cover of part of the chip possibly fails in the production and processing process, the safety of key data in the chip cannot be guaranteed. Therefore, chip removal for top metal cap failure is required.
The top layer metal overlay is typically tested by logic integrity circuits: the design principle of the logic integrity circuit is as follows: the method comprises the steps that logic gate circuits are respectively added at two ends of a metal wire covered by a top layer, whether data are correctly transmitted from an input end to an output end of the metal wire is tested through the added logic gate circuits, if the data of all the metal wires are normally transmitted, the metal wires covered by the top layer are determined to be effectively connected, and further the metal covering function of the top layer is determined to be normal; if the data of the metal wire is not normally transmitted, for example, the metal wire is broken, the logic values of the circuits at the two ends of the metal wire are not equal, and it is determined that the top-layer metal covering function is abnormal. Fig. 1 is a schematic diagram of a logic integrity circuit of a single metal line, as shown in fig. 1, an inverter is added to each end of the metal line, and if the data output of the metal line is equal to the data input (Dout ═ Din), it is determined that the metal line is effectively connected; if the data output of the metal wire is different from the data input, the metal wire is determined to be invalid in connection, the chip is maliciously damaged, and the protection circuit informs the chip control circuit through an alarm signal, so that the chip is protected. FIG. 2 is a schematic diagram of a conventional chip logic integrity circuit, and as shown in FIG. 2, the logic integrity circuit divides metal lines covered by a top layer into n groups (n ≧ 2), each group including m metal lines (m ≧ 2). When the logic integrity circuit works, certain data is applied to the input of the metal wire, whether Din [ i ] is equal to Dout [ i ] (i is 1-m) or not is judged, and whether the chip is attacked or not is judged by comparing whether the data at two ends of n × m metal wires are equal or not. The method for testing the metal coverage of the top layer of the chip based on the logic integrity circuit comprises the following two steps: the first method is that whether the chip is in normal function is determined by whether the logic integrity circuit generates an alarm signal; the second is that under the premise that the logic integrity circuit does not generate an alarm signal, a plurality of selected metal wires are cut off, and if the logic integrity circuit generates an alarm, the chip is determined to be in a normal function.
The existing chip top layer metal coverage test method has the following problems: when the first method is adopted for testing, whether the top layer metal covering is complete or not is determined only by whether an alarm signal is generated or not under the condition that the logic integrity circuit is not attacked; whether an alarm signal can be generated when the logic integrity circuit is attacked or not is not tested, and the protection of data in the chip cannot be realized. The second test method is a destructive test, and the test of cutting off a plurality of metal wires cannot represent that the top metal cover of the chip has no problem; in addition, the result of a single test cannot represent the test of all chips, and the test method cannot be used for the mass production test of the chips; in addition, the testing method has the problems of low efficiency and high cost. In summary, the existing method cannot determine that the metal coverage test of the top layer of the chip is effective, and cannot effectively remove the chip with the failed metal wire connection.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a method and an apparatus for implementing a chip top metal cover circuit test, which can test a chip top metal cover circuit when it is determined that a logic integrity circuit is functioning normally.
In order to achieve the object of the present invention, the present invention provides a method for implementing a top metal coverage test of a chip, wherein all metal lines of a top metal coverage circuit comprise:
sequentially selecting partial metal wires in batches to perform signal inversion of input data;
when the signal inversion of the input data of each batch of metal wires is finished, comparing and analyzing the input data and the output data of all the metal wires;
and summarizing according to the comparative analysis results of the input data and the output data of all batches, and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result.
Optionally, the successively-batched selection of the metal lines for inverting the input data signal includes:
sorting each group of metal wires of the top layer metal covering circuit respectively;
according to the sequence, sequentially selecting a first preset number of metal wires from each group of metal wires which are not subjected to signal inversion to perform signal inversion of input data;
the first preset number is one or more than one.
Optionally, the comparing and analyzing the input data and the output data includes:
when the signal inversion of the input data is completed for each batch of metal lines,
comparing and analyzing input data and output data of each metal wire of the top metal covering circuit through a logic integrity circuit, and determining whether the input data and the output data of each metal wire are equal;
and taking the inverse data of the input data of each metal wire of the top metal covering circuit, and comparing and analyzing whether the inverse data of the input data of each metal wire is different from the output data of each metal wire through the logic integrity circuit.
Optionally, determining whether the function of the chip top metal covering circuit is normal includes:
summarizing the comparative analysis results of the input data and the output data of all batches,
if the input data and the output data of each metal wire are equal, and the inverse data of the input data and the output data of each metal wire are unequal, determining that the top metal covering circuit of the chip is normal in function;
if the input data of the metal wire and the output data of the metal wire are not equal; and/or determining that the top layer metal covering circuit of the chip is abnormal if the inverse data of the input data of the metal wire is equal to the output data of the metal wire.
On the other hand, this application still provides a device of realizing chip top layer metal covering test, includes: the device comprises a signal overturning unit, a batch analysis unit and a determination unit; wherein,
the signal overturning unit is used for overturning signals of input data for all metal wires of the top layer metal covering circuit by selecting part of the metal wires in batches successively;
the batch analysis unit is used for comparing and analyzing the input data and the output data of all the metal wires when the metal wires in each batch complete the signal inversion of the input data;
the determining unit is used for summarizing according to the comparative analysis results of the input data and the output data of all batches and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result.
Optionally, the signal turning unit is specifically configured to sort all the metal lines of the top metal covering circuit respectively;
according to the sequence, sequentially selecting a first preset number of metal wires from each group of metal wires which are not subjected to signal inversion to perform signal inversion of input data;
the first preset number is one or more than one.
Optionally, the batch analysis unit is specifically adapted to,
when the metal lines in each batch complete the inversion of the input data signal,
comparing and analyzing input data and output data of each metal wire of the top metal covering circuit through a logic integrity circuit, and determining whether the input data and the output data of each metal wire are equal;
and taking the inverse data of the input data of each metal wire of the top metal covering circuit, and comparing and analyzing whether the inverse data of the input data of each metal wire is different from the output data of each metal wire through the logic integrity circuit.
Optionally, the determining unit is specifically configured to,
summarizing the comparative analysis results of the input data and the output data of all batches,
if the input data and the output data of each metal wire are equal, and the inverse data of the input data and the output data of each metal wire are unequal, determining that the top metal covering circuit of the chip is normal in function;
if the input data of the metal wire and the output data of the metal wire are not equal; and/or determining that the top layer metal covering circuit of the chip is abnormal if the inverse data of the input data of the metal wire is equal to the output data of the metal wire.
Compared with the prior art, the technical scheme of the application comprises the following steps: sequentially selecting a part of metal wires in batches from all metal wires of the top metal covering circuit to perform signal inversion of input data; when the signal inversion of the input data of each batch of metal wires is finished, comparing and analyzing the input data and the output data of all the metal wires; and summarizing according to the comparative analysis results of the input data and the output data of all batches, and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result. The method selects partial metal wires in batches to perform signal inversion of input data, performs comparative analysis on the input data and the output data of all batches of signal inversion, and realizes judgment on whether the function of the top layer metal covering circuit is normal or not through the logic integrity circuit, thereby reducing the testing cost of the top layer metal covering circuit and improving the working efficiency of the top layer metal covering circuit testing.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without limiting the invention. In the drawings:
FIG. 1 is a schematic diagram of a logic integrity circuit for a single metal line;
FIG. 2 is a schematic diagram of a prior art chip logic integrity circuit;
FIG. 3 is a flow chart of a method for implementing a chip top metal coverage test according to the present invention;
FIG. 4 is a block diagram of an apparatus for implementing a top metal coverage test of a chip according to the present invention;
FIG. 5 is a block diagram of an exemplary logic integrity circuit embodying the present invention;
fig. 6 is a schematic diagram illustrating an exemplary metal line connection disconnection.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.
Fig. 3 is a flowchart of a method for implementing a chip top metal coverage test according to the present invention, and as shown in fig. 3, all metal lines of a top metal coverage circuit include:
300, selecting a part of metal wires in batches successively to perform signal inversion of input data;
the method specifically comprises the following steps: the method for inverting the input data signals by the metal wires of the selected part in batches comprises the following steps:
sorting each group of metal wires of the top layer metal covering circuit respectively;
according to the sequence, sequentially selecting a first preset number of metal wires from each group of metal wires which are not subjected to signal inversion to perform signal inversion of input data;
the first preset number is one or more than one.
It should be noted that the first preset number generally takes the value of one strip to perform test analysis on the top metal covering circuit more clearly and conveniently; when the preset number is one, in each group of metal wires, each metal wire is inevitably subjected to signal turnover compared with the metal wires in the group, so that the condition that the metal wires in the group are adhered can be tested; the method for sequentially selecting part of the metal wires in batches to perform signal inversion of input data is only an optional embodiment of the invention; whether to sequence or not, whether to select the same number of metal lines in each group, whether to select the metal lines for signal inversion of input data in each group, and the like can be adjusted by a person skilled in the art according to practical application. Alternatively, the signal inversion performed in the present invention may be performed only once for each metal line, that is, all metal lines must undergo one signal inversion.
301, comparing and analyzing the input data and the output data of all the metal wires when the metal wires in each batch complete the signal inversion of the input data;
in this step, the comparing and analyzing of the input data and the output data includes:
when the metal lines in each batch complete the inversion of the input data signal,
comparing and analyzing input data and output data of each metal wire of the top metal covering circuit through a logic integrity circuit, and determining whether the input data and the output data of each metal wire are equal;
and taking the inverse data of the input data of each metal wire of the top-layer metal covering circuit, and comparing and analyzing whether the inverse data of the input data of each metal wire is different from the output data of each metal wire through a logic integrity circuit.
And step 302, summarizing according to the comparative analysis results of the input data and the output data of all batches, and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result.
In this step, determining whether the function of the chip top metal covering circuit is normal includes:
summarizing the comparative analysis results of the input data and the output data of all batches,
if the input data and the output data of each metal wire are equal and the inverse data and the output data of the input data of each metal wire are unequal, determining that the top metal covering circuit of the chip is normal in function;
if the input data of the metal wire and the output data of the metal wire are not equal; and/or if the inverse data of the input data of the metal wire is equal to the output data of the metal wire, determining that the top layer metal covering circuit of the chip is abnormal in function.
According to the method, part of metal wires are selected in batches successively to perform signal inversion of input data, and the input data and the output data of all batches of signal inversion are compared and analyzed, so that the judgment on whether the function of the top metal covering circuit is normal or not due to the influence of abnormal working of a logic integrity circuit is avoided; the test cost of the top metal covering circuit is reduced, and the work efficiency of the top metal covering circuit test is improved.
Fig. 4 is a block diagram of a device for implementing a chip top layer metal coverage test according to the present invention, as shown in fig. 4, including: the device comprises a signal overturning unit, a batch analysis unit and a determination unit; wherein,
the signal overturning unit is used for overturning signals of input data for all metal wires of the top layer metal covering circuit by selecting part of the metal wires in batches successively;
the signal turning unit is specifically used for sequencing all the metal wires of the top layer metal covering circuit respectively;
according to the sequence, sequentially selecting a first preset number of metal wires from each group of metal wires which are not subjected to signal inversion to perform signal inversion of input data;
the first preset number is one or more than one.
The batch analysis unit is used for comparing and analyzing the input data and the output data of all the metal wires when the metal wires in each batch complete the signal inversion of the input data;
the batch analysis unit is particularly useful for,
when the metal lines in each batch complete the inversion of the input data signal,
comparing and analyzing input data and output data of each metal wire of the top metal covering circuit through a logic integrity circuit, and determining whether the input data and the output data of each metal wire are equal;
and taking the inverse data of the input data of each metal wire of the top-layer metal covering circuit, and comparing and analyzing whether the inverse data of the input data of each metal wire is different from the output data of each metal wire through a logic integrity circuit.
The determining unit is used for summarizing according to the comparative analysis results of the input data and the output data of all batches and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result.
The determination unit is specifically adapted to,
summarizing comparative analysis results of input data and output data of all batches;
if the input data and the output data of each metal wire are equal and the inverse data and the output data of the input data of each metal wire are unequal, determining that the top metal covering circuit of the chip is normal in function;
if the input data of the metal wire and the output data of the metal wire are not equal; and/or if the inverse data of the input data of the metal wire is equal to the output data of the metal wire, determining that the top layer metal covering circuit of the chip is abnormal in function.
The process of the present invention is illustrated in clear detail below by means of specific examples, which are provided only for illustrating the present invention and are not intended to limit the scope of the process of the present invention.
Examples
Fig. 5 is a block diagram of an exemplary logic integrity circuit applied in the present invention, and as shown in fig. 5, clk is a clock signal, rst is a reset signal, en is a working enable signal, rn is a random number input signal, te is a test enable signal, and error is an alarm signal for abnormal working of a top metal covering circuit.
The application example divides the metal wires of the top metal covering circuit of the chip into n groups, and each group comprises 8 metal wires, namely m is 8. After the system is reset, the initial value of each set of metal lines ([8:1]) is all "0". And the work enable is turned on (en is equal to 1), the logic integrity circuit enters a work mode, and whether the top layer metal circuit of the chip works normally is detected. The logic integrity circuit supports loop detection.
The metal wire covers the whole chip, and when the metal wire top layer metal covering circuit is tested, if the metal wire is connected normally, the input data and the output data of the metal wire should be equal. And if the input data and the output data are not equal, determining that the top layer metal covering circuit of the chip works abnormally.
The application example successively batches the metal wires of the selected part to perform signal inversion of input data;
when the signal inversion of the input data of each batch of metal wires is finished, comparing and analyzing the input data and the output data of all the metal wires;
and summarizing according to the comparative analysis results of the input data and the output data of all batches, and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result.
Fig. 6 is a schematic diagram of a connection and disconnection of metal lines in the application example, as shown in fig. 6, after each group of metal lines is sorted, according to the sorting order, one group of metal lines is selected each time to perform data inversion of an input signal, that is, the metal lines of the top metal covering circuit are traversed in a signal inversion mode one by one according to a single bit, because the metal lines are disconnected, the input data and the output data are different inevitably, and it can be determined that the top metal covering circuit of the chip is abnormal, that is, the chip is abnormal, and the chip with the abnormality is determined by the test method object of the application example, so as to perform screening and removing processing on the chip. The application example is simple in design and efficient in test, and can be used for testing a top layer metal covering circuit during chip volume production.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A method for realizing chip top layer metal covering test is characterized in that all metal wires of a top layer metal covering circuit comprise:
sequentially selecting partial metal wires in batches to perform signal inversion of input data;
when the signal inversion of the input data of each batch of metal wires is finished, comparing and analyzing the input data and the output data of all the metal wires;
and summarizing according to the comparative analysis results of the input data and the output data of all batches, and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result.
2. The method of claim 1, wherein said successively batched selection of portions of metal lines to perform input data signal inversion comprises:
sorting each group of metal wires of the top layer metal covering circuit respectively;
according to the sequence, sequentially selecting a first preset number of metal wires from each group of metal wires which are not subjected to signal inversion to perform signal inversion of input data;
the first preset number is one or more than one.
3. The method of claim 1 or 2, wherein the comparative analysis of the input data and the output data comprises:
when the signal inversion of the input data is completed for each batch of metal lines,
comparing and analyzing input data and output data of each metal wire of the top metal covering circuit through a logic integrity circuit, and determining whether the input data and the output data of each metal wire are equal;
and taking the inverse data of the input data of each metal wire of the top metal covering circuit, and comparing and analyzing whether the inverse data of the input data of each metal wire is different from the output data of each metal wire through the logic integrity circuit.
4. The method of claim 1 or 2, wherein the determining whether the chip top metal covering circuit is functioning normally comprises:
summarizing the comparative analysis results of the input data and the output data of all batches,
if the input data and the output data of each metal wire are equal, and the inverse data of the input data and the output data of each metal wire are unequal, determining that the top metal covering circuit of the chip is normal in function;
if the input data of the metal wire and the output data of the metal wire are not equal; and/or determining that the top layer metal covering circuit of the chip is abnormal if the inverse data of the input data of the metal wire is equal to the output data of the metal wire.
5. An apparatus for implementing a chip top layer metal coverage test, comprising: the device comprises a signal overturning unit, a batch analysis unit and a determination unit; wherein,
the signal overturning unit is used for overturning signals of input data for all metal wires of the top layer metal covering circuit by selecting part of the metal wires in batches successively;
the batch analysis unit is used for comparing and analyzing the input data and the output data of all the metal wires when the metal wires in each batch complete the signal inversion of the input data;
the determining unit is used for summarizing according to the comparative analysis results of the input data and the output data of all batches and determining whether the function of the top metal covering circuit of the chip is normal or not according to the summarizing result.
6. The apparatus of claim 5, wherein the signal flipping unit is specifically configured to sort each group of metal lines of the top metal overlay circuit for all metal lines;
according to the sequence, sequentially selecting a first preset number of metal wires from each group of metal wires which are not subjected to signal inversion to perform signal inversion of input data;
the first preset number is one or more than one.
7. The apparatus according to claim 5 or 6, characterized in that the batch analysis unit is specifically adapted to,
when the metal lines in each batch complete the inversion of the input data signal,
comparing and analyzing input data and output data of each metal wire of the top metal covering circuit through a logic integrity circuit, and determining whether the input data and the output data of each metal wire are equal;
and taking the inverse data of the input data of each metal wire of the top metal covering circuit, and comparing and analyzing whether the inverse data of the input data of each metal wire is different from the output data of each metal wire through the logic integrity circuit.
8. The apparatus according to claim 5 or 6, characterized in that the determination unit is specifically configured to,
summarizing the comparative analysis results of the input data and the output data of all batches,
if the input data and the output data of each metal wire are equal, and the inverse data of the input data and the output data of each metal wire are unequal, determining that the top metal covering circuit of the chip is normal in function;
if the input data of the metal wire and the output data of the metal wire are not equal; and/or determining that the top layer metal covering circuit of the chip is abnormal if the inverse data of the input data of the metal wire is equal to the output data of the metal wire.
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| CN108090384A (en) * | 2017-11-06 | 2018-05-29 | 大唐微电子技术有限公司 | A kind of metal line detector and chip |
| CN109726507A (en) * | 2019-01-17 | 2019-05-07 | 湖南进芯电子科技有限公司 | A kind of efficiently multi-functional verification platform and method |
| CN109782154A (en) * | 2019-02-27 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of tamper detection protection circuit, implementation method and tamper chip |
| CN117521162A (en) * | 2023-10-24 | 2024-02-06 | 北京城建智控科技股份有限公司 | Top layer covering circuit of security chip, security chip and attack identification method |
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| CN109726507A (en) * | 2019-01-17 | 2019-05-07 | 湖南进芯电子科技有限公司 | A kind of efficiently multi-functional verification platform and method |
| CN109726507B (en) * | 2019-01-17 | 2023-04-18 | 湖南进芯电子科技有限公司 | Efficient multifunctional verification method |
| CN109782154A (en) * | 2019-02-27 | 2019-05-21 | 大唐微电子技术有限公司 | A kind of tamper detection protection circuit, implementation method and tamper chip |
| CN117521162A (en) * | 2023-10-24 | 2024-02-06 | 北京城建智控科技股份有限公司 | Top layer covering circuit of security chip, security chip and attack identification method |
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