CN105609549A - Bi-directional discharge tube chip and manufacturing method thereof - Google Patents

Abstract

The invention provides a bidirectional discharge tube chip and a manufacturing method thereof. The structure of the bidirectional discharge tube chip is N ⁺ -P ⁺ -N ^- -NP ⁺⁺ -P ⁺ type; the planar structure of the bidirectional discharge tube chip is sequentially diffused N ⁺ region, diffused P ⁺ region, implanted N ^- region, diffused P ⁺⁺ region, metal region, oxidation isolation region, passivation glass layer and chip scribing region; the cross-sectional structure of the bidirectional discharge tube chip is sequentially diffused N ⁺ region , Diffusion P ⁺ area, implanted N ^- area, substrate N area, diffusion P ⁺⁺ area, metal area, oxidation isolation area, passivation glass layer and chip scribing area. The present invention has the following advantages: the P ⁺⁺ junction is formed by the deep junction diffusion of the solid-state diffusion source (boron nitride sheet), so that the junction depth is flat and uniform, and the anti-surge is stronger; at the same time, the width of the base area can be reduced , so that the turn-on voltage is reduced, the response speed is fast, and the power consumption is small; the P ⁺⁺ junction can also reduce the body resistance and increase the carrying power of the discharge tube.

Description

Bidirectional discharge tube chip and manufacturing method thereof

technical field

The invention relates to the technical field of production of semiconductor discharge tube chips, in particular to a low-power bidirectional discharge tube chip with more concentrated voltage and a manufacturing method.

Background technique

Semiconductor discharge tubes are widely used in all areas requiring lightning protection, such as program-controlled switches, telephones, fax machines, distribution frames, communication interfaces, and communication transmission equipment in communication switching equipment, to protect internal ICs from instantaneous overvoltage impact and damage. At present, semiconductor discharge tubes are mostly made of planar technology in the industry, and there are some technical defects: 1) high cost and complicated process; 2) large switching loss and slow response speed; 3) PN junction is formed on the surface, using silicon dielectric Membrane protection, easy to be damaged, voltage breakdown on the surface; 4) The symmetry of the bidirectional discharge tube is poor, and one end will be defective during circuit use.

Contents of the invention

In view of the defects in the prior art, the purpose of the present invention is to provide a bidirectional discharge tube chip with low turn-on voltage, fast response speed and more concentrated breakdown voltage and its manufacturing method.

In order to solve the above technical problems, the present invention provides a bidirectional discharge tube chip, the structure of the bidirectional discharge tube chip is N ⁺ -P ⁺ -N ^- -NP ⁺⁺ -P ⁺ type; the plane of the bidirectional discharge tube chip The structure is sequentially diffused N ⁺ area, diffused P ⁺ area, implanted N ^- area, diffused P ⁺⁺ area, metal area, oxidation isolation area, passivation glass layer and chip scribing area; the cross section of the bidirectional discharge tube chip The layer structure is sequentially the diffused N ⁺ region, the diffused P ⁺ region, the implanted N ^- region, the substrate N region, the diffused P ⁺⁺ region, the metal region, and the oxidation isolation region , the passivation glass layer and the chip scribe area.

A method for manufacturing a bidirectional discharge tube chip, comprising the steps of:

Step 1, cleaning the surface of the silicon wafer;

Step 2, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 1.5 microns to 2.5 microns;

Step 3, make the N ^- region pattern on both sides of the oxidized silicon wafer by photolithography and development;

Step 4, using ammonium fluoride etching solution to etch out the N ^- region;

Step 5, growing a sacrificial oxide layer on the surface of the silicon wafer;

Step 6, implanting phosphorous ions into the photoetched N ^- region and advancing to form a deep N ^- region;

Step 7, immerse in hydrofluoric acid and ultrasonically clean with deionized water to remove the surface oxide layer;

Step 8, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 1.2 microns to 2.0 microns;

Step 9, making a P ⁺⁺ region by photolithography and development in the adjacent double-sided region of the N ^- region;

Step 10, put the silicon wafer with the P ⁺⁺ area photoetched on the quartz boat provided with the boron nitride wafer, and then perform pre-deposition;

Step 11, the pre-deposited silicon wafer is subjected to deep junction diffusion in a diffusion furnace to form a deep P ⁺⁺ region;

Step 12, soaking with hydrofluoric acid and ultrasonic cleaning with deionized water to remove the oxide layer on the surface of the silicon wafer;

Step 13, placing the cleaned silicon wafer on a quartz boat provided with a boron nitride wafer, and performing pre-deposition in a diffusion furnace;

In step 14, the pre-deposited silicon wafer is diffused in a diffusion furnace to form a P ⁺ region;

Step 15, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 1.5 microns to 2.5 microns;

Step 16, making an N ⁺ area ⁱⁿ the N- area;

Step 17, put the silicon wafer with the N ⁺ region photoetched into the diffusion furnace and pass it into phosphorus oxychloride for pre-deposition;

Step 18, the phosphorus-deposited silicon wafer is diffused in a diffusion furnace to form an N ⁺ region;

Step 19, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 0.7 μm to 1 μm;

Step 20, forming a mesa groove pattern through the processes of gluing, exposing, developing, and removing the oxide layer;

Step 21, corroding the groove of the table top and rinsing it with deionized water;

Step 22, placing the silicon wafer in the electrophoretic solution for glass electrophoresis;

Step 23, sintering the electrophoresed silicon wafer in a sintering furnace at 800°C to 820°C;

Step 24, apply glue, photolithography, development, deoxidation and glass to the sintered silicon wafer to form metal areas and scribe lines;

Step 25, nickel-plating, gold-plating, and drying the silicon wafer;

Step 26, using a laser cutting machine to cut the gold-plated silicon wafer into individual chips from the scribing lane.

Preferably, in the step 6, phosphorus ions of 5×10 ¹⁵ keV to 8×10 ¹⁵ keV are implanted into the photolithographic N ^- region by ion implantation, and the temperature is 1250°C to 1280°C for 50 hours to After 60 hours, a deep N ^- zone is formed.

Preferably, in the step 10, the silicon wafer with the P ⁺⁺ area photoetched out is placed on a quartz boat provided with a boron nitride sheet, and the silicon wafer and the boron nitride sheet are placed crosswise, at 1150°C to 1200°C pre-deposition in a diffusion furnace.

Preferably, in the step 11, the pre-deposited silicon wafer is subjected to deep junction diffusion in a diffusion furnace at 1250° C. to 1260° C. for 20 hours to 30 hours to form a deep P ⁺⁺ region.

Preferably, in the step 13, the cleaned silicon wafer is placed on a quartz boat provided with a boron nitride sheet, and the silicon wafer and the boron nitride sheet are placed crosswise, and the silicon wafer is placed in a diffusion furnace at 1150°C to 1200°C. pre-deposition.

Preferably, in the step 14, the pre-deposited silicon wafer is subjected to propulsion diffusion in a diffusion furnace at 1250° C. to 1260° C. for 8 hours to 12 hours to form a P ⁺ region;

Preferably, in the step 17, the silicon wafer with a plurality of N ⁺ regions photoetched out is put into a diffusion furnace at 1100° C. to 1200° C. and pre-deposited by passing phosphorus oxychloride.

Preferably, in the step 18, the phosphorus-deposited silicon wafer is diffused in a diffusion furnace at 1150° C. to 1250° C. for 4 hours to 8 hours to form an N ⁺ region.

Preferably, in the step 21, nitric acid, hydrofluoric acid, and glacial acetic acid are used to prepare a mixed acid according to a ratio of 5:3.3:1, and the groove of the mesa is corroded, and the depth of the groove exceeds 1.2 to 1.5 times the depth of the P ⁺ layer, The temperature of the mixed acid is 0℃～5℃, and it should be rinsed with deionized water.

Compared with the prior art, the bidirectional discharge tube chip and its manufacturing method of the present invention have the following advantages:

1. The P ⁺⁺ junction is formed by the deep junction diffusion of the solid-state diffusion source (boron nitride sheet), so that the junction depth is flat and uniform, and the anti-surge is stronger; at the same time, it can reduce the width of the base region and make the turn-on voltage Reduced, fast response, low power consumption; P ⁺⁺ junction can also reduce body resistance and increase the carrying power of the discharge tube;

2. The method of forming a layer of sacrificial oxide layer before phosphorus ion implantation can play the role of adsorbing impurities, so that phosphorus ions are evenly distributed and reduce leakage current;

3. Phosphorus ion implantation is used to form a deep N ^- junction, with controllable dose and uniform concentration, which can make the breakdown voltage more concentrated, and at the same time, the voltage breaks down in the body, not on the surface of the table, so that the flow resistance of the table is good. Improved anti-surge capability;

4. The countertop adopts double-sided glass powder electrophoresis to form a passivation protective layer, which has good symmetry, enhances the mechanical damage resistance of the bidirectional discharge tube, and improves the reliability of the discharge tube;

5. Adopt the design of dicing lane and use laser to cut the chip, which reduces the damage of the chip and improves the production efficiency at the same time.

Description of drawings

Other features, objects and advantages of the present invention will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings.

Fig. 1 is the structure plan view of bidirectional discharge tube chip of the present invention;

Fig. 2 is a cross-sectional view of the bidirectional discharge tube chip structure of the present invention;

Fig. 3 is a flow chart of the manufacturing method of the bidirectional discharge tube chip of the present invention.

In the picture:

1- Diffused N ⁺ region ^2- Diffused P ⁺ region 3- Implanted N- region

4- Substrate N region 5- Diffused P ⁺⁺ region 6- Metal region

7-Oxidation isolation area 8-Passivation glass layer 9-Chip scribe area

detailed description

The present invention will be described in detail below in conjunction with specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

As shown in Figures 1 to 3, the specific steps of the method for manufacturing a bidirectional discharge tube chip provided by the present invention are as follows:

1) Cleaning before oxidation: chemically treat the surface of the silicon wafer through electronic cleaning agents SC1 (ammonia + hydrogen peroxide) and SC2 (hydrochloric acid + hydrogen peroxide), ultrasonic cleaning with deionized water, etc., to obtain a clean original silicon wafer;

2) Oxidation: grow the oxide layer mask on both sides of the cleaned silicon wafer in an oxidation furnace at 1100°C to 1200°C, and the thickness of the oxide layer mask is 1.5 microns to 2.5 microns;

3) Photolithography N ^- : Make an asymmetric N ^- area pattern on the front and back sides of the oxidized silicon wafer by photolithography and development;

4) Remove the N ^- region oxide layer: use ammonium fluoride etching solution to etch the N ^- region;

5) Long sacrificial oxide layer: a thin layer of sacrificial oxide layer is grown on the surface of the silicon wafer;

6) Phosphorus implantation: Phosphorus ions of 5×10 ¹⁵ keV to 8×10 ¹⁵ keV are implanted into the N ^- region formed by photolithography by ion implantation, and the temperature is 1250°C to 1280°C for 50 hours to 60 hours. Formation of deep N ^- regions;

7) Advance post-treatment: soak in hydrofluoric acid and ultrasonically clean with deionized water to remove the surface oxide layer;

8) Oxidation: grow an oxide layer mask on both sides of the cleaned silicon wafer in an oxidation furnace at 1100°C to 1200°C, the thickness of the oxide layer mask is 1.2 microns to 2.0 microns;

9) Photolithography P ⁺⁺ area: the P ⁺⁺ area is produced by photolithography and development in the adjacent double ^- sided area of the N- area;

10) Pre-deposition of boron source: Put the silicon wafer with P ⁺⁺ area etched out on the quartz boat with boron nitride sheet, place the silicon wafer and boron nitride sheet crosswise, and diffuse at 1150°C to 1200°C pre-deposition in the furnace;

11) Boron source advancement: the pre-deposited silicon wafer is subjected to deep junction diffusion in a diffusion furnace at 1250°C to 1260°C for 20 to 30 hours to form a deep P ⁺⁺ region;

12) Advance post-treatment: soak in hydrofluoric acid and ultrasonically clean with deionized water to remove the surface oxide layer;

13) Boron source pre-deposition: put the cleaned silicon wafer on a quartz boat equipped with boron nitride slices, place the silicon wafer and boron nitride slice crosswise, and perform pre-deposition in a diffusion furnace at 1150°C to 1200°C ;

14) Boron source propulsion: pre-deposited silicon wafers are propulsed and diffused in a diffusion furnace at 1250°C to 1260°C for 8 hours to 12 hours to form a P ⁺ region;

15) Oxidation: Silicon wafers are grown in an oxidation furnace at 1100°C to 1200°C on both sides of an oxide layer mask, and the thickness of the oxide layer mask is 1.5 microns to 2.5 microns;

16) Photolithographic N ⁺ area: In the N ^- area, a high concentration and multiple disconnected N ⁺ areas are produced by photolithography and development;

17) Phosphorus source pre-deposition: Put the silicon wafer with multiple N ⁺ regions photoetched into a diffusion furnace at 1100°C to 1200°C and pass it into phosphorus oxychloride for pre-deposition;

18) Phosphorus diffusion: Phosphorus-deposited silicon wafers are diffused in a diffusion furnace at 1150°C to 1250°C for 4 hours to 8 hours to form N ⁺ regions;

19) Oxidation: Silicon wafers are grown in an oxidation furnace at 1100°C to 1200°C on both sides of an oxide layer mask, and the thickness of the oxide layer mask is 0.7 micron to 1 micron;

20) Photolithographic mesa groove: form the mesa groove pattern through the processes of glue coating, exposure, development, and deoxidation;

21) Mesa groove corrosion: Use nitric acid, hydrofluoric acid, and glacial acetic acid to prepare a mixed acid in a ratio of 5:3.3:1 to corrode the groove on the table. The depth of the groove exceeds 1.2 to 1.5 times the depth of the P ⁺ layer. The temperature of the mixed acid 0 ℃ ~ 5 ℃, and rinse with deionized water;

22) Electrophoretic glass: configure electrophoretic fluid, place the silicon wafer in the prepared electrophoretic fluid, set the time (preferably 50 seconds to 200 seconds) according to the weight of glass to be deposited according to the depth of the table groove, and perform glass electrophoresis;

23) Sintering: Sinter the silicon wafer after electrophoresis in a sintering furnace at 800°C to 820°C;

24) Photoetching metal area and scribing road: apply glue, photolithography, development, deoxidation layer and glass to the sintered silicon wafer to form metal area and scribing road;

25) Nickel plating and gold plating: Nickel plating, gold plating, and drying of silicon wafers after deoxidation and scribing of glass in a metal electroplating tank;

26) Chip cutting: Use a laser cutting machine to cut the gold-plated silicon wafer into a single chip from the scribe line at the groove of the table.

As shown in Figure 1 and Figure 2, the bidirectional discharge tube chip structure is N ⁺ -P ⁺ -N ^- -NP ⁺⁺ -P ⁺ type; the planar cross-sectional structure is sequentially diffused N ⁺ area 1, diffused P ⁺ area 2, Implanted N ^- region 3, diffused P ⁺⁺ region 5, metal region 6, oxidation isolation region 7, passivation glass layer 8, chip scribe region 9; the cross-sectional structure is sequentially diffused N ⁺ region, 1 diffused P ⁺ region 2. Implant N ^- region 3, substrate N region 4, diffuse P ⁺⁺ region 5, metal region 6, oxide isolation region 7, passivation glass layer 8, chip scribe region 9.

The parameters of the low-power bidirectional discharge tube with more concentrated voltage produced by this method are shown in Table 1:

parameter VDRM Idm vs. IH VT Capacitance Test Conditions IDRM=1.2uA VDRM=320V Is=800mA IT=2.2A 1MHz, 2Vbias unit V uA V mA V (Pf) standard value ≥320 ≤5 ≤400 ≥150 ≤4 ≤40 measured value 360 0.8 380 200 2.8 25

Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. In the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims (10)

1. A bidirectional discharge tube chip, characterized in that, the structure of the bidirectional discharge tube chip is N ⁺ -P ⁺ -N ^- -NP ⁺⁺ -P ⁺ type; The planar structure of the bidirectional discharge tube chip is sequentially a diffused N ⁺ region, a diffused P ⁺ region, an implanted N ^- region, a diffused P ⁺⁺ region, a metal region, an oxidation isolation region, a passivation glass layer, and a chip scribing region; The cross-sectional layer structure of the bidirectional discharge tube chip is sequentially the diffused N ⁺ region, the diffused P ⁺ region, the implanted N ⁻ region, the substrate N region, the diffused P ⁺⁺ region, the The metal region, the oxidation isolation region, the passivation glass layer and the chip scribe region. 2. A manufacturing method of bidirectional discharge tube chip, is characterized in that, comprises the steps: Step 1, cleaning the surface of the silicon wafer; Step 2, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 1.5 microns to 2.5 microns; Step 3, make the N ^- region pattern on both sides of the oxidized silicon wafer by photolithography and development; Step 4, using ammonium fluoride etching solution to etch out the N ^- region; Step 5, growing a sacrificial oxide layer on the surface of the silicon wafer; Step 6, implanting phosphorous ions into the photoetched N ^- region and advancing to form a deep N ^- region; Step 7, immerse in hydrofluoric acid and ultrasonically clean with deionized water to remove the surface oxide layer; Step 8, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 1.2 microns to 2.0 microns; Step 9, making a P ⁺⁺ region by photolithography and development in the adjacent double-sided region of the N ^- region; Step 10, put the silicon wafer with the P ⁺⁺ area photoetched on the quartz boat provided with the boron nitride wafer, and then perform pre-deposition; Step 11, the pre-deposited silicon wafer is subjected to deep junction diffusion in a diffusion furnace to form a deep P ⁺⁺ region; Step 12, soaking with hydrofluoric acid and ultrasonic cleaning with deionized water to remove the oxide layer on the surface of the silicon wafer; Step 13, placing the cleaned silicon wafer on a quartz boat provided with a boron nitride wafer, and performing pre-deposition in a diffusion furnace; In step 14, the pre-deposited silicon wafer is diffused in a diffusion furnace to form a P ⁺ region; Step 15, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 1.5 microns to 2.5 microns; Step 16, making an N ⁺ area ⁱⁿ the N- area; Step 17, put the silicon wafer with the N ⁺ region photoetched into the diffusion furnace and pass it into phosphorus oxychloride for pre-deposition; Step 18, the phosphorus-deposited silicon wafer is diffused in a diffusion furnace to form an N ⁺ region; Step 19, growing an oxide layer mask on both sides of the silicon wafer in an oxidation furnace at 1100° C. to 1200° C., the thickness of the oxide layer mask being 0.7 μm to 1 μm; Step 20, forming a mesa groove pattern through the processes of gluing, exposing, developing, and removing the oxide layer; Step 21, corroding the groove of the table top and rinsing it with deionized water; Step 22, placing the silicon wafer in the electrophoretic solution for glass electrophoresis; Step 23, sintering the electrophoresed silicon wafer in a sintering furnace at 800°C to 820°C; Step 24, apply glue, photolithography, development, deoxidation and glass to the sintered silicon wafer to form metal areas and scribe lines; Step 25, nickel-plating, gold-plating, and drying the silicon wafer; Step 26, using a laser cutting machine to cut the gold-plated silicon wafer into individual chips from the scribing lane. 3. The manufacturing method of bidirectional discharge tube chip according to claim 2, characterized in that, in the step 6, 5×10 ¹⁵ keV～8×10 ¹⁵ is implanted into the N ^- region formed by photolithography by ion implantation method kev phosphorous ions, and use a temperature of 1250 ° C ~ 1280 ° C for 50 hours to 60 hours to form a deep N ^- region. 4. the manufacture method of bidirectional discharge tube chip according to claim 2 is characterized in that, in described step 10, the silicon wafer of P ⁺⁺ district is put into on the quartz boat that is provided with boron nitride sheet by photolithography , Silicon wafers and boron nitride wafers are placed crosswise, and pre-deposited in a diffusion furnace at 1150 ° C to 1200 ° C. 5. The manufacturing method of bidirectional discharge tube chip according to claim 2, characterized in that, in the step 11, the pre-deposited silicon wafer is subjected to deep junction diffusion in a diffusion furnace at 1250° C. to 1260° C. for 20 hours to 20 hours. 30 hours, a deep P ⁺⁺ zone is formed. 6. the manufacture method of bidirectional discharge tube chip according to claim 2 is characterized in that, in described step 13, the silicon wafer after cleaning is placed on the quartz boat that is provided with boron nitride sheet, silicon wafer and nitrogen The boron oxide sheets are arranged crosswise, and pre-deposited in a diffusion furnace at 1150°C to 1200°C. 7. The manufacturing method of the bidirectional discharge tube chip according to claim 2, characterized in that, in the step 14, the pre-deposited silicon wafer is pushed and diffused in a diffusion furnace at 1250° C. to 1260° C. for 8 hours to 12 hours , forming a P ⁺ region. 8. The manufacturing method of bidirectional discharge tube chip according to claim 2, characterized in that, in the step 17, the silicon wafer with a plurality of N ⁺ regions etched by photolithography is put into a diffusion furnace at 1100°C-1200°C Feed phosphorus oxychloride for pre-deposition. 9. The manufacturing method of bidirectional discharge tube chip according to claim 2, characterized in that, in the step 18, the silicon wafer deposited with phosphorus is diffused in a diffusion furnace at 1150° C. to 1250° C. for 4 hours to 8 hours, N ⁺ region is formed. 10. The manufacturing method of bidirectional discharge tube chip according to claim 2, characterized in that, in said step 21, use nitric acid, hydrofluoric acid, glacial acetic acid to be mixed into mixed acid according to the ratio of 5:3.3:1, and corrode the table top Groove, the depth of the groove exceeds 1.2 to 1.5 times the depth of the P ⁺ layer, the temperature of the mixed acid is 0°C to 5°C, and it is rinsed with deionized water.