CN105609416A - Silicon etching method - Google Patents

Abstract

The invention provides a silicon etching method, which comprises the following steps: (1) making an etching mask pattern on a silicon substrate; (2) placing the silicon substrate with the etching mask pattern on Etching is carried out in an etching machine; the power of the lower electrode of the etching machine is generated by a pulse power supply of 100-1000 Hz, and the temperature of the loading table of the etching machine is -120°C--100°C. The above silicon etching method combines the low-temperature silicon etching process with the low-frequency process, which can well control the sidetracking phenomenon generated during the silicon etching process, and is suitable for nanoscale silicon etching with high aspect ratio, which solves the problem of the existing technology. Sidetracking occurs during silicon etch.

Description

A silicon etching method

technical field

The invention relates to the technical field of semiconductor micro-nano processing, in particular to a silicon etching method.

Background technique

In the fields of integrated circuits, micro-electromechanical systems, and optical device manufacturing, it is hoped that the dry etching of single crystal silicon and polycrystalline silicon high aspect ratio structures can be realized. Therefore, the plasma etching technology not only needs to have a certain etching rate and etching selectivity, but also needs to have almost completely controllable anisotropic sidewall etching. At present, the generally used anisotropic dry etching cannot meet the anisotropic requirements required for etching high aspect ratio structures due to the inevitable existence of lateral etching caused by ion bombardment on the sidewall. Therefore, to obtain a structure with a high aspect ratio, a layer of corrosion-resistant film can be covered on the surface of the sidewall during etching to protect the sidewall from being etched laterally, thereby obtaining a vertical etching result.

The general resist layer is an organic polymer film formed by chemical deposition during the etching process, for which C (carbon) element needs to be introduced into the reaction gas. Introduce CF gas and etching gas to generate plasma at the same time for etching. However, due to the generation of organic polymers, there are many physical and chemical factors in the chamber. It is necessary to achieve sufficient thickness and stable and reliable during the etching process. Polymer resists are very difficult and often fall short of high aspect ratio structures with better sidewall quality. In response to this, the researchers developed the Bosch etching process, which separates the deposition of the polymer resist layer and the etching of the single crystal silicon into two independent processes and alternates them in cycles, thus avoiding the deposition The interaction between etching and etching ensures the stable and reliable quality of etching resistance, so that the required anisotropic etching can be obtained, and it has a higher etching rate and selectivity ratio.

The Bosch etching process also has its application limitations, such as rough sidewalls and sidetracking grooves of hundreds of nanometers, so the Bosch etching process is more suitable for etching of dimensions above the micron scale. If it is desired to obtain an etching structure with a smooth side wall and a high aspect ratio, a low-temperature plasma etching method of an inorganic etching resist layer can be used. The temperature of the stage for low-temperature silicon etching is generally -150°C to -100°C. The etching gas is F (fluorine)-based gas, and SiF _x O _y is formed with the participation of oxygen, which is volatile in a chamber environment at room temperature. , but is solid at low temperature. By reducing the volatility of the substances generated by the surface reaction, the thickness and reliability of the etching resist layer are increased to prevent the lateral etching of the sidewall during the etching process, and a higher aspect ratio etching pattern can be achieved, and at the same time, it has a higher selection ratio.

Although the low-temperature plasma silicon etching process has the above-mentioned advantages, in the conventional low-temperature etching in the experiment (the frequency of the lower electrode power source is 13.56MHz, which belongs to radio frequency RF: RadioFrequency), etching nanoscale high depth and width Compared with the structure, due to the narrow opening of the groove, it is relatively difficult for the active chemical reaction substance to diffuse to the bottom of the groove with a high aspect ratio, and at the same time, the volatiles generated after the chemical reaction at the bottom of the groove are also difficult to be extracted. That is to say, the concentration of reactant species near the opening of the narrower slot is higher than that at the bottom of the slot, so the concave sidetracking phenomenon is easily formed near the slot opening, which widens the size of the opening, and finally makes the side wall of the entire slot not as desired. required anisotropy. As shown in FIG. 1 , the slot opening width of the electron beam glue on the silicon substrate in FIG. 1 is 100 nm, and the slot opening width after etching is 145.8 nm, which is 45.8 nm wider. The angle between the base line of the etched bottom of the groove and the edge of the etched groove is 92.6°. Therefore, the etched bottom of the groove is 50nm narrower, and the side wall is not steep.

In addition, if an insulating material such as _SiO2 is used as a mask, the discharge effect at the tip of the insulating layer will form a local electric field, and this micro-electric field will deflect the ions bombarded downward, resulting in sidetracking on the side wall below the mask. Therefore, in nanoscale etching, the similar sidetracking phenomenon will greatly reduce the performance of various devices.

Contents of the invention

Based on the defects in the prior art, the present invention provides a method for etching silicon to solve the sidetracking phenomenon in the etching process of silicon in the prior art.

For this purpose, the invention provides a kind of silicon etching method, comprises the following steps:

(1) making an etching mask pattern on a silicon substrate;

(2) Place the silicon substrate with the etching mask pattern in an etching machine for etching; the lower electrode power of the etching machine is generated by a pulse power supply of 100-1000 Hz, and the etching machine The temperature of the slide table is -120℃～-100℃.

Preferably, the above method also includes the following steps:

(3) Overetching the etched silicon substrate.

Preferably, the temperature of the loading stage of the etching machine in the step (3) is the same as the temperature of the loading table of the etching machine in the step (2).

Preferably, in the etching process, the power of the pulse power supply is 3-30W, the duty ratio of the generated pulse signal is 10%-50%, and the power of the upper electrode of the etching machine is 200-1000W , the vacuum chamber pressure of the etching machine is 5-15 mTorr, the flow rate of the SF ₆ gas used by the etching machine is 20-40 sccm, and the flow rate of the O ₂ gas used by the etching machine is 5-30 sccm.

Preferably, in the etching process, the power of the pulse power supply is 5W, the frequency of the pulse power supply is 500Hz, and the duty cycle of the pulse signal generated by the pulse power supply is 35%; the etching machine The upper electrode power is 400W, the vacuum chamber pressure of the etching machine is 5mTorr, the flow rate of the SF gas used by the etching machine is ₂₀ sccm, the O gas flow rate used by the etching machine is ₅ sccm, and the The temperature of the loading stage of the etching machine is -120°C.

Preferably, in the etching process, the power of the pulse power supply is 5W, the frequency of the pulse power supply is 300Hz, and the duty cycle of the pulse signal generated by the pulse power supply is set to 35%; the etching machine The power of the upper electrode is 400W, the vacuum chamber pressure of the etching machine is _9mTorr , the flow rate of the SF gas used by the etching machine is 30 sccm, and the flow rate of the O gas used in the etching machine is ₉ sccm, so The temperature of the loading stage of the etching machine is -110°C.

Preferably, in the etching process, the power of the pulse power supply is 30W, the frequency of the pulse power supply is 1000Hz, and the duty cycle of the pulse signal generated by the pulse power supply is 50%; The power of the upper electrode is 1000W, the vacuum chamber pressure of the etching machine is 15mTorr, the flow rate of the SF gas used by the etching machine is ₄₀ sccm, the O gas flow rate used by the etching machine is ₂₀ sccm, and the The temperature of the loading stage of the etching machine is -100°C.

Preferably, in the over-etching process, the power of the pulse power supply is 3W, the frequency of the pulse power supply is 500Hz, and the duty cycle of the pulse signal generated by the pulse power supply is set to 10%; the etching The power of the upper electrode of the etching machine is 400W, the vacuum chamber pressure of the etching machine is 7mTorr, the flow rate of the SF gas used by the etching machine is ₂₀ sccm, and the flow rate of the O gas used in the etching machine is ₁₅ sccm, The temperature of the loading table of the etching machine is -110°C.

Preferably, the electron beam colloid is positive colloid or negative colloid.

Preferably, in described step (1), make etching mask pattern on silicon substrate, comprise:

Coating electron beam glue, electron beam exposure and electron beam development on the silicon substrate.

It can be seen from the above technical solution that the silicon etching method of the present invention combines the low-temperature silicon etching process with the low-frequency process, uses a low-frequency pulse power supply as the lower electrode power supply of the etching machine, and sets the temperature of the slide table at a certain low temperature range It can well control the sidetracking phenomenon generated in the silicon etching process, and is suitable for nanoscale silicon etching with high aspect ratio.

Description of drawings

Fig. 1 is the image obtained by the cross-sectional scanning electron microscope of prior art etching nano-silicon;

2 is a schematic flow diagram of a silicon etching method provided by an embodiment of the present invention;

3 is an image obtained by a scanning electron microscope of a cross-section of nano-silicon etched by a silicon etching method provided by an embodiment of the present invention;

4 is an image obtained by a scanning electron microscope of a cross-section of nano-silicon etched by a silicon etching method provided by another embodiment of the present invention;

Fig. 5 is the image of different graphic arrays obtained by a scanning electron microscope of a cross-section of nanometer silicon etched by a silicon etching method provided by another embodiment of the present invention;

FIG. 6 is an image obtained by a scanning electron microscope of a cross-section of polysilicon etched by a silicon etching method according to another embodiment of the present invention.

detailed description

The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

FIG. 2 shows a schematic flowchart of a method for etching silicon according to an embodiment of the present invention. As shown in FIG. 2 , the silicon etching method of this embodiment includes step (1) and step (2).

(1) making an etching mask pattern on a silicon substrate;

(2) Place the silicon substrate with the pattern of the etching mask in an etching machine for etching.

Wherein, the power of the lower electrode of the etching machine is generated by a 100-1000 Hz pulse power supply, and the temperature of the loading stage of the etching machine is -120°C--100°C.

The silicon etching method of this embodiment combines low-frequency pulse technology with low-temperature etching technology, and the obtained etching groove has good verticality and no sidetracking phenomenon.

FIG. 3 shows an image obtained by a cross-sectional scanning electron microscope of etching nano-silicon by the silicon etching method provided by an embodiment of the present invention. The silicon etching method of the present embodiment is as follows:

(1) Coating electron beam positive resist ZEP520 on the silicon substrate, after pre-baking, electron beam exposure and development, a positive photoresist pattern is prepared.

(2) Place the silicon substrate in an inductively coupled plasma etching machine for etching.

Wherein, the power of the pulse power supply is set to 5W, the frequency is set to 500Hz, and the duty cycle of the pulse signal generated by the pulse power supply is set to 35%. The power of the upper electrode of the inductively coupled plasma etching machine is set to 400W, the pressure of the vacuum chamber is set to 5mTorr, the flow rate of _SF6 gas is 20sccm, the flow rate of _O2 gas is 5sccm, and the temperature of the slide table is set to -120°C.

The etched silicon wafer was cut along the direction of the etching groove, and the section of the etching groove was observed with a scanning electron microscope (SEM). The obtained SEM image is shown in FIG. 3 . It can be seen from FIG. 3 that the slot opening width of the electron beam glue on the silicon substrate of this embodiment is 100 nm, and the slot opening width after etching is 104.4 nm, which is 4.4 nm wider. After etching, the angle between the baseline of the bottom of the groove and the edge of the etched groove is 89.7°, and the depth of the etched groove is 1.46 μm. Therefore, the aspect ratio of the etched groove reaches 14:1, and the width of the groove opening is consistent with the width of the glue opening. , There is no sidetracking phenomenon at the opening, the edge line of the etched groove after etching is almost vertical to the baseline, the etched groove has high steepness, and the side wall is smooth.

In the silicon etching method of this embodiment, the electron beam positive resist is used as an etching mask, and a low-frequency pulse power supply and a low-temperature loading stage are used to complete the etching of the silicon substrate, and the obtained etching groove has a high aspect ratio. Moreover, the etching groove has high steepness and smooth side walls, which overcomes the sidetracking phenomenon in the silicon etching process in the prior art.

FIG. 4 shows an image obtained by a cross-sectional scanning electron microscope of etching nano-silicon by the silicon etching method provided by another embodiment of the present invention. The silicon etching method of the present embodiment is as follows:

(1) Electron beam positive resist ZEP520 is coated on silicon substrate SOI (Silicon On Insulator) on an insulating substrate, and a positive photoresist pattern is prepared after pre-baking, electron beam exposure, and development.

(2) Place the silicon substrate in an inductively coupled plasma etching machine for etching.

Wherein, the power of the pulse power supply is set to 5W, the frequency is set to 300Hz, and the duty ratio of the pulse signal generated by the pulse power supply is set to 35%. The power of the upper electrode of the inductively coupled plasma etching machine was set to 400W, the pressure of the vacuum chamber was set to _9mTorr , the flow rate of SF gas was 30 sccm, the flow rate of O gas was ₉ sccm, and the temperature of the slide stage was set to -110°C.

(3) Over-etching the etched SOI by using an inductively coupled plasma etching machine.

Wherein, the power of the pulse power supply is set to 3W, the frequency is set to 500Hz, and the duty cycle of the pulse signal generated by the pulse power supply is set to 10%. The power of the upper electrode of the inductively coupled plasma etching machine is set to 400W, the pressure of the vacuum chamber is set to 7mTorr, the flow rate of _SF6 gas is 20sccm, the flow rate of _O2 gas is 15sccm, and the temperature of the slide table is set to -110°C.

The etched silicon wafer was cut along the direction of the etching groove, and the section of the etching groove was observed with a scanning electron microscope (SEM). The obtained SEM image is shown in FIG. 4 . It can be seen from FIG. 4 that the slot opening width of the electron beam glue on the SOI sheet of this embodiment is 110 nm, and the slot opening width after etching is 110.0 nm without broadening. The angle between the baseline of the groove bottom and the edge of the etched groove after etching is 90.4°, and the depth of the etched groove is 1.06 μm. Therefore, the etching aspect ratio reaches 10:1, the opening width of the groove is consistent with the width of the glue opening, and there is no sidetracking phenomenon at the opening; the etching groove has high steepness and smooth side walls; there is no footing at the bottom of the etching groove ( Footing) phenomenon, that is, there is no sidetracking at the bottom of the etching.

In the silicon etching method of this embodiment, by over-etching the etched SOI sheet, the opening of the obtained etching groove is not widened, the etching groove has a high steepness, the side wall is smooth, and the bottom of the etching groove is free of Sidetracking.

FIG. 5 shows images of different pattern arrays obtained by scanning electron microscopy of a cross-section of nano-silicon etched by a silicon etching method provided by another embodiment of the present invention. The silicon etching method of the present embodiment is as follows:

(1) Coating electron beam glue HSQ on the silicon substrate, and preparing a negative photoresist pattern through electron beam exposure technology, the key dimension of the line is sub-10nm, and the thickness is about 30nm.

(2) The silicon substrate is etched in an inductively coupled plasma etching machine.

Wherein, the power of the pulse power supply is set to 12W, the frequency is set to 350Hz, and the duty ratio of the pulse signal generated by the pulse power supply is 25%. The power of the upper electrode of the inductively coupled plasma etching machine is 350W, the pressure of the vacuum chamber is 7mTorr, the flow rate of SF ₆ gas is 30 sccm, the flow rate of O ₂ gas is 20 sccm, and the temperature of the slide table is set to -110°C.

The etched silicon wafer was cut along the direction of the etching groove, and the section of the etching groove was observed with a scanning electron microscope (SEM). The obtained SEM image is shown in FIG. 5 . It can be seen from FIG. 5 that the sub-10nm line etching depth of the annular etching structure, dot matrix etching structure, linear etching structure, and hexagonal line etching structure on the silicon substrate of this embodiment is 300nm, and the depth of each etching structure is 300nm. The width ratio is 10:1, the side wall of the line has no sidetracking phenomenon, the straightness is high, and the side wall is smooth.

The silicon etching method of this embodiment can etch different structures, and the sidewalls of the lines of each etched structure have no sidetracking phenomenon, and the straightness is high.

FIG. 6 shows an image obtained by a cross-sectional scanning electron microscope of polysilicon etched by a silicon etching method provided by another embodiment of the present invention. The silicon etching method of the present embodiment is as follows:

(1) Electron beam glue ZEP520 was coated on a polysilicon SOI sheet (700nm top polysilicon grown by plasma enhanced chemical vapor deposition method PECVD), and a positive photoresist pattern was prepared after pre-baking, electron beam exposure, and development.

(2) Place the silicon substrate in an inductively coupled plasma etching machine for etching.

Wherein, the power of the pulse power supply is set to 30W, the frequency is set to 1000Hz, and the duty ratio of the pulse signal generated by the pulse power supply is set to 50%. The power of the upper electrode of the inductively coupled plasma etching machine is set to 1000W, the pressure of the vacuum chamber is set to 15mTorr, the flow rate of _SF6 gas is 40sccm, the flow rate of _O2 gas is 20sccm, and the temperature of the slide table is set to -100°C.

(3) Over-etching the etched SOI by using an inductively coupled plasma etching machine.

Wherein, the power of the pulse power supply is set to 5W, the frequency is set to 100Hz, and the duty cycle of the pulse signal generated by the pulse power supply is set to 10%. The power of the upper electrode of the inductively coupled plasma etching machine is set to 200W, the pressure of the vacuum chamber is set to _15mTorr , the flow rate of SF gas is ₃₀ sccm, the flow rate of O gas is 30 sccm, and the temperature of the slide table is set to -100°C.

The etched silicon wafer was cut along the direction of the etching groove, and the section of the etching groove was observed with a scanning electron microscope (SEM). The obtained SEM image is shown in FIG. 6 . It can be seen from FIG. 6 that the opening width of the electron beam glue on the SOI sheet of this embodiment is 169.0 nm, and the depth of the etched groove is 705.3 nm. Therefore, the etching aspect ratio reaches 4:1, the opening width of the groove is consistent with the width of the glue opening, and there is no sidetracking at the opening; the etching groove has high steepness and smooth side walls; there is no footing at the bottom of the etching groove ( Footing) phenomenon, that is, there is no sidetracking at the bottom of the etching.

In the silicon etching method of this embodiment, polysilicon SOI wafers are etched, and the obtained etching grooves have high steepness, smooth side walls, and no footing and sidetracking.

Those of ordinary skill in the art can understand that: although the present invention has been described in detail with general descriptions, specific embodiments and tests above, on the basis of the present invention, some modifications or improvements can be made to it. It is obvious to the skilled person. Therefore, the modifications or improvements made on the basis of not departing from the spirit of the present invention all belong to the protection scope of the present invention.

Claims (10)

1. A silicon etching method, is characterized in that, comprises the following steps: (1) making an etching mask pattern on a silicon substrate; (2) Place the silicon substrate with the etching mask pattern in an etching machine for etching; the lower electrode power of the etching machine is generated by a pulse power supply of 100-1000 Hz, and the etching machine The temperature of the slide table is -120℃～-100℃. 2. method according to claim 1, is characterized in that, said method also comprises the following steps: (3) Overetching the etched silicon substrate. 3. The method according to claim 2, characterized in that, the temperature of the loading table of the etching machine described in the step (3) is the same as the temperature of the loading table of the etching machine described in the step (2). same. 4. The method according to claim 1, characterized in that, in the etching process, the power of the pulse power supply is 3-30W, and the duty cycle of the generated pulse signal is 10%-50%, so The power of the upper electrode of the etching machine is 200-1000W, the vacuum chamber pressure of the etching machine is 5-15mTorr, the flow rate of the _SF6 gas used by the etching machine is 20-40sccm, and the etching machine adopts The flow rate of _O2 gas is 5~30sccm. 5. The method according to claim 1, characterized in that, in the etching process, the power of the pulse power supply is 5W, the frequency of the pulse power supply is 500Hz, and the pulse signal generated by the pulse power supply occupies The empty ratio is 35%; the upper electrode power of the etching machine is 400W, the vacuum chamber pressure of the etching machine is 5mTorr, the _SF6 gas flow rate used by the etching machine is 20sccm, and the etching machine The flow rate of the O ₂ gas used is 5 sccm, and the temperature of the loading stage of the etching machine is -120°C. 6. The method according to claim 1, characterized in that, in the etching process, the power of the pulse power supply is 5W, the frequency of the pulse power supply is 300Hz, and the pulse signal generated by the pulse power supply occupies The empty ratio is set to 35%; the upper electrode power of the etching machine is 400W, the vacuum chamber pressure of the etching machine is 9mTorr, and the flow rate of the SF gas used by the etching machine is _30sccm , the etching machine The flow rate of _O2 gas used in the etching machine is 9 sccm, and the temperature of the loading stage of the etching machine is -110°C. 7. The method according to claim 1, characterized in that, in the etching process, the power of the pulse power supply is 30W, the frequency of the pulse power supply is 1000Hz, and the pulse signal generated by the pulse power supply occupies The empty ratio is 50%; the power of the upper electrode of the etching machine is 1000W, the vacuum chamber pressure of the etching machine is _15mTorr , the flow rate of the SF gas used by the etching machine is 40sccm, and the etching machine The flow rate of the O ₂ gas used is 20 sccm, and the temperature of the loading stage of the etching machine is -100°C. 8. The method according to claim 2, characterized in that, in the overetching process, the power of the pulse power supply is 3W, the frequency of the pulse power supply is 500Hz, and the pulse signal generated by the pulse power supply The duty cycle is set to 10%; the power of the upper electrode of the etching machine is 400W, the vacuum chamber pressure of the etching machine is 7mTorr, the flow rate of the _SF6 gas used by the etching machine is 20sccm, the etching machine The flow rate of _O2 gas used in the etching machine is 15 sccm, and the temperature of the loading stage of the etching machine is -110°C. 9. The method according to claim 1, wherein the electron beam colloid is a positive colloid or a negative colloid. 10. method according to claim 1, is characterized in that, in described step (1), make etching mask pattern on silicon substrate, comprising: Coating electron beam gel, exposing and developing on the silicon substrate.