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CN105592624A - High-density PCB high-efficiently suppressing edge radiation and method for suppressing edge radiation - Google Patents

High-density PCB high-efficiently suppressing edge radiation and method for suppressing edge radiation Download PDF

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CN105592624A
CN105592624A CN201510964145.8A CN201510964145A CN105592624A CN 105592624 A CN105592624 A CN 105592624A CN 201510964145 A CN201510964145 A CN 201510964145A CN 105592624 A CN105592624 A CN 105592624A
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layer
short
pcb board
laminated structure
power
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CN105592624B (en
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张木水
邓春业
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Sun Yat Sen University
SYSU CMU Shunde International Joint Research Institute
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Sun Yat Sen University
SYSU CMU Shunde International Joint Research Institute
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • H05K1/0216Reduction of cross-talk, noise or electromagnetic interference
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/0929Conductive planes
    • H05K2201/093Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

本发明一种高效抑制边沿辐射的高密度PCB板及边沿辐射抑制方法。PCB板中EMI的主要来源是电源分配网络,电源分配网络中的电源/地平面对形成一个谐振腔,在谐振频率处会造成严重的电磁辐射,本发明提出的高密度PCB板及边沿辐射抑制方法,能够高效屏蔽电源/地中的电磁辐射,将EMI减小到最理想的状态。其中叠层设计采用嵌入式平面电容叠层,这种由薄电介质和电源地平面对构成的嵌入式平面电容在高频段可以看作交流短路,能够达到特别好的电磁辐射抑制效果。

The invention discloses a high-density PCB board for efficiently suppressing edge radiation and a method for suppressing edge radiation. The main source of EMI in the PCB board is the power distribution network. The power/ground plane in the power distribution network forms a resonant cavity, which can cause serious electromagnetic radiation at the resonant frequency. The high-density PCB board and edge radiation suppression proposed by the present invention The method can effectively shield the electromagnetic radiation in the power supply/ground, and reduce the EMI to an optimal state. Among them, the stack design adopts embedded planar capacitor stacking. This embedded planar capacitor composed of thin dielectric and power ground plane can be regarded as an AC short circuit in the high frequency band, which can achieve a particularly good electromagnetic radiation suppression effect.

Description

高效抑制边沿辐射的高密度PCB板及边沿辐射抑制方法High-density PCB board and edge radiation suppression method for efficiently suppressing edge radiation

技术领域technical field

本发明涉及PCB板领域,更具体地涉及一种高效抑制边沿辐射的高密度PCB板及边沿辐射抑制方法。The invention relates to the field of PCB boards, and more particularly to a high-density PCB board and an edge radiation suppression method for efficiently suppressing edge radiation.

背景技术Background technique

随着半导体工艺的高速发展,电子系统的集成规模越来越大,体积越来越小,速度越来越快,功能也越来越强大。但也正是由于众多的晶体管集成到单个的芯片中,处理器和芯片的功耗不断增加,供电电压不断减小,电压噪声容限也随之减小,电磁辐射不断增加,信号完整性问题越来越严峻。电磁干扰(EMI)问题已成为高速数字系统设计所面临的一个巨大挑战。With the rapid development of semiconductor technology, the integration scale of electronic systems is getting bigger and bigger, the volume is getting smaller, the speed is getting faster, and the functions are getting more powerful. But it is precisely because many transistors are integrated into a single chip, the power consumption of processors and chips continues to increase, the supply voltage continues to decrease, the voltage noise margin also decreases, electromagnetic radiation continues to increase, and signal integrity problems It's getting tougher. The problem of electromagnetic interference (EMI) has become a huge challenge for the design of high-speed digital systems.

PCB的边缘辐射抑制是高速PCBEMI/EMC(板级EMI)设计的一个部分,同时也是最重要的一个部分。现阶段,一些经常用来抑制电磁辐射的方法有:20-H准则、边缘过孔防护栏、电磁带隙结构、分离式电容器去耦墙等。20-H准则只是一个经验法则,在很多时候达到的抑制效果并不理想。边缘过孔防护栏是在PCB的边缘订上一些类似栅栏的过孔防护带来屏蔽电磁辐射,可以起到不错的抑制效果。电磁带隙结构也可以起到较好的抑制效果,但是一般蘑菇型EBG结构具有较差低频隔离而且阻带较窄。分离式电容器去耦墙设计简单,但是只是频率低时性能突出,在高频时性能不好。PCB edge radiation suppression is a part of high-speed PCBEMI/EMC (board-level EMI) design, and it is also the most important part. At this stage, some methods that are often used to suppress electromagnetic radiation include: 20-H rule, edge via guardrail, electromagnetic bandgap structure, decoupling wall of separated capacitors, etc. The 20-H guideline is only a rule of thumb, and the suppression achieved in many cases is not ideal. The edge via guardrail is to place some fence-like via guards on the edge of the PCB to shield electromagnetic radiation, which can have a good suppression effect. The electromagnetic bandgap structure can also have a better suppression effect, but the general mushroom-type EBG structure has poor low-frequency isolation and a narrow stop band. The split capacitor decoupling wall is simple in design, but it only performs well at low frequencies and does not perform well at high frequencies.

本发明提供的方案主要是基于嵌入式平面去耦电容的PCB的叠层设计和短路孔设计。现在的单板及系统速率越来越高,单板PCB的叠层越来越重要。单板PCB的叠层就是将信号层、电源平面层和地平面层在既符合机械工艺要求又符合单板性能要求下合理的堆叠在一起。合理的叠层不仅能起到信号传输线阻抗控制的作用,同时又起到抑制板上系统噪声的作用,能够起到抑制电磁辐射的效果。提出的该设计方法主要是针对嵌入式平面去耦电容的叠层设计。嵌入式平面电容需要使用短路孔将噪声接入PCB的整个电流回路当中,所以短路孔的连接方式也影响到EMI的效果。The solution provided by the present invention is mainly based on the stacking design of the PCB with the embedded planar decoupling capacitor and the design of the short circuit hole. Nowadays, the speed of single boards and systems is getting higher and higher, and the stacking of single board PCBs is becoming more and more important. The stacking of a single-board PCB is to reasonably stack the signal layer, power plane layer, and ground plane layer together under the requirements of both the mechanical process and the performance of the single board. Reasonable lamination can not only control the impedance of the signal transmission line, but also suppress the system noise on the board and suppress electromagnetic radiation. The proposed design method is mainly aimed at the stack design of embedded planar decoupling capacitors. Embedded planar capacitors need to use short-circuit holes to connect noise to the entire current loop of the PCB, so the connection method of the short-circuit holes also affects the effect of EMI.

发明内容Contents of the invention

本发明为解决以上现有技术的缺陷,提供了一种高效抑制边沿辐射的高密度PCB板,能够高效屏蔽电源层/地层中的电磁辐射,将EMI减小到最理想的状态。In order to solve the above defects of the prior art, the present invention provides a high-density PCB board that efficiently suppresses edge radiation, can efficiently shield electromagnetic radiation in the power layer/earth layer, and reduce EMI to an optimal state.

为实现以上发明目的,采用的技术方案是:For realizing above-mentioned purpose of the invention, the technical scheme that adopts is:

一种高效抑制边沿辐射的高密度PCB板,其特征在于:采用非对称式的叠层结构或对称式的叠层结构,其中所述非对称式的叠层结构由若干个从上到下依次分布的地层-电源层对构成,其中所述地层-电源层对中地层位于电源层的顶部;所述对称式的叠层结构由若干个从上到下依次分布的电源层-地层-电源层对构成,其中所述地层设置在两层电源层之间;A high-density PCB board that efficiently suppresses edge radiation is characterized in that it adopts an asymmetrical laminated structure or a symmetrical laminated structure, wherein the asymmetrical laminated structure consists of several Distributed ground layer-power layer pair, wherein the ground layer-power layer pair is located on the top of the power layer; the symmetrical stack structure consists of several power layer-ground layer-power layer distributed sequentially from top to bottom A pair of configurations, wherein the ground layer is arranged between two power supply layers;

非对称式的叠层结构和对称式的叠层结构中,相邻的地层与电源层之间设置有一层高介电常数的介质层,地层、电源层与介质层贴合;所述高介电常数的介质层的介电常数大于3.7;In the asymmetric laminated structure and the symmetrical laminated structure, a dielectric layer with a high dielectric constant is provided between the adjacent ground layer and the power supply layer, and the ground layer, the power supply layer and the dielectric layer are bonded together; the high dielectric constant The dielectric constant of the dielectric layer is greater than 3.7;

非对称式的叠层结构和对称式的叠层结构中,所有的电源层/地层通过短路过孔进行连接。In the asymmetric stacked structure and the symmetrical stacked structure, all power planes/ground planes are connected through short-circuit vias.

上述方案中,由介质层和电源层、地层构成的嵌入式平面电容,由于较大的分布电容在高频段可以看作交流短路,由此,电源层、地层可以视为无限小阻抗的短路。这样一个嵌入式平面电容可视为一个平面,在这种情况下,嵌入式平面电容就可视为接地短路孔。In the above scheme, the embedded planar capacitance composed of the dielectric layer, the power layer, and the ground layer can be regarded as an AC short circuit in the high frequency band due to the large distributed capacitance. Therefore, the power layer and the ground layer can be regarded as a short circuit with infinitely small impedance. Such an embedded planar capacitor can be regarded as a plane, and in this case, the embedded planar capacitor can be regarded as a shorting hole to ground.

优选地,所述介质层的厚度为0.4mm。Preferably, the thickness of the dielectric layer is 0.4 mm.

优选地,所述介质层的厚度为0.01mm,介电常数为20。Preferably, the dielectric layer has a thickness of 0.01 mm and a dielectric constant of 20.

优选地,所述非对称式的叠层结构或对称式的叠层结构中,电源层、地层的厚度一致。Preferably, in the asymmetric stacked structure or the symmetrical stacked structure, the power layer and the ground layer have the same thickness.

优选地,所述短路过孔的半径为0.15mm。Preferably, the radius of the short-circuit via hole is 0.15 mm.

同时,本发明还提供了一种边沿辐射抑制方法,其具体方案如下:Simultaneously, the present invention also provides a kind of edge radiation suppression method, and its specific scheme is as follows:

一种边沿辐射抑制方法,通过对高密度PCB板的叠层结构进行选择以及对短路过孔的设计来抑制边沿辐射,包括以下步骤:A method for suppressing edge radiation, which suppresses edge radiation by selecting a stacked structure of a high-density PCB board and designing short-circuit vias, comprising the following steps:

S1.判断EMI干扰为低频干扰还是高频干扰,若为低频干扰,则使高密度PCB板采用对称式的叠层结构,若为高频干扰,则使高密度PCB板采用非对称式的叠层结构;S1. Determine whether the EMI interference is low-frequency interference or high-frequency interference. If it is low-frequency interference, use a symmetrical laminated structure for the high-density PCB board. If it is high-frequency interference, use an asymmetrical laminated structure for the high-density PCB board. layer structure;

S2.计算短路过孔的周期,若短路过孔的周期大于20H,则使高密度PCB板采用非对称式的叠层结构,且使短路过孔只将所有的地层连接起来;若短路过孔的周期小于20H,则使则使高密度PCB板采用对称式的叠层结构,并使短路过孔将所有的地层、所有的电源层连接起来;S2. Calculate the period of the short-circuit via. If the period of the short-circuit via is greater than 20H, the high-density PCB board adopts an asymmetrical laminated structure, and the short-circuit via only connects all the ground layers; if the short-circuit via If the period is less than 20H, the high-density PCB board adopts a symmetrical laminated structure, and the short-circuit via holes connect all ground layers and all power layers;

S3.若S1、S2确定的叠层结构相冲突,则采用步骤S1确定的叠层结构。S3. If the stacked structure determined in S1 and S2 conflicts, adopt the stacked structure determined in step S1.

与现有技术相比,本发明的有益效果是:Compared with prior art, the beneficial effect of the present invention is:

(1)嵌入式平面去耦电容可以提供快速的转换速度,从而提高高速电路的功率传输性能。(1) Embedded planar decoupling capacitors can provide fast switching speeds, thereby improving the power transfer performance of high-speed circuits.

(2)有效地减少高频噪声的功率,提高信号完整性性能,减少EMI。(2) Effectively reduce the power of high-frequency noise, improve signal integrity performance, and reduce EMI.

(3)性能优异,可以达到很好的抑制效果。(3) It has excellent performance and can achieve a good suppression effect.

(4)抑制带可以达到很宽,获得很高的转折频率。(4) The suppression band can be very wide and a high corner frequency can be obtained.

附图说明Description of drawings

图1为实验原型板示意图。Figure 1 is a schematic diagram of the experimental prototype board.

图2为嵌入式平面去耦电容结构示意图。FIG. 2 is a schematic diagram of the structure of an embedded planar decoupling capacitor.

图3为非对称式叠层结构示意图。FIG. 3 is a schematic diagram of an asymmetric laminated structure.

图4为对称式叠层结构示意图。Fig. 4 is a schematic diagram of a symmetrical laminated structure.

图5为G短路过孔示意图。FIG. 5 is a schematic diagram of a G short circuit via.

图6为P短路过孔示意图。FIG. 6 is a schematic diagram of a P short circuit via.

图7为P/G短路过孔示意图。FIG. 7 is a schematic diagram of a P/G short circuit via.

图8为接地短路孔示意图。FIG. 8 is a schematic diagram of a grounding short circuit hole.

具体实施方式detailed description

附图仅用于示例性说明,不能理解为对本专利的限制;The accompanying drawings are for illustrative purposes only and cannot be construed as limiting the patent;

以下结合附图和实施例对本发明做进一步的阐述。The present invention will be further elaborated below in conjunction with the accompanying drawings and embodiments.

实施例1Example 1

1、本发明的实验板原型选择。1. Experimental board prototype selection of the present invention.

本发明以现有的尺寸最常见的三层PCB板为实验板原型,大小为80mm×120mm,介质材料为最常用的的介电常数是4.4的FR4,介质层的厚度为0.4mm,电源/地平面层厚度为0.03mm。激励源为集总端口激励,位于PCB板的右下侧,如图1所示。The present invention takes the three-layer PCB board with the most common size as the experimental board prototype, the size is 80mm×120mm, the dielectric material is the most commonly used FR4 with a dielectric constant of 4.4, the thickness of the dielectric layer is 0.4mm, and the power supply/ The thickness of the ground plane layer is 0.03mm. The excitation source is the lumped port excitation, which is located on the lower right side of the PCB, as shown in Figure 1.

2、抑制边沿辐射的嵌入式平面电容叠层设计。2. Embedded planar capacitor stack design that suppresses edge radiation.

对于这种原型板,会由于各种各样的原因产生电磁辐射。平面边缘处电流路径中断,阻抗突变,信号发生发射产生振铃,频谱在振铃频率处出现峰值,加剧辐射。电源/地平面对构成平面板谐振腔,被平面间的电流或者噪声激励而发生谐振现象,从而在PCB边缘产生严重的电磁辐射。本发明提出的这种嵌入式平面电容叠层设计,可以达到很好的电磁辐射抑制效果,具体步骤如下:For such prototyping boards, electromagnetic radiation is generated for various reasons. The current path is interrupted at the edge of the plane, the impedance changes suddenly, the signal is emitted and rings, and the spectrum peaks at the ringing frequency, which intensifies the radiation. The power/ground plane pair constitutes a flat panel resonant cavity, which is excited by the current or noise between the planes to cause resonance, resulting in serious electromagnetic radiation at the edge of the PCB. The embedded planar capacitor stack design proposed by the present invention can achieve a good electromagnetic radiation suppression effect, and the specific steps are as follows:

(1)原型板的每个电源层和地层都设计成嵌入式平面电容结构,即被非常薄的、高介电常数的介质隔开的电源/地平面对,新介质层的厚度通常取0.01mm,介电常数为20。(1) Each power layer and ground layer of the prototype board is designed as an embedded planar capacitor structure, that is, a power/ground pair separated by a very thin, high dielectric constant medium. The thickness of the new dielectric layer is usually 0.01 mm with a dielectric constant of 20.

(2)嵌入式平面去耦电容的叠层有两种,一种是非对称式G-P-G-P-G-P的叠层设计,如图3所示,另一种是对称式P-G-P-P-G-P的叠层设计,如图4所示。(2) There are two stacks of embedded planar decoupling capacitors, one is the asymmetric G-P-G-P-G-P stack design, as shown in Figure 3, and the other is the symmetrical P-G-P-P-G-P stack design, as shown in Figure 4 .

对于图3,低频时顶部平面电容去耦效果比较差,电流更多选择的是P短路孔路径以及随后的底部平面电容流通并形成回路,高频时,顶部平面电容去耦效果大幅提升,电流选择顶部平面电容和G短路过孔流通并形成回路。对于图4的分析类似,只是低频时电流经过的短路孔是G短路孔,高频时电流经过的短路孔是P短路孔。观察图3和图4可以看出,非对称式和对称式叠层,短路孔路径是不一样的,低频时,图4的G短路孔长度比图3的P短路孔长度短,对应的寄生电感及其带来的阻抗也小,所以噪声去耦性能更好,产生的电磁辐射也会更小。而在高频时,图4中的P短路过孔长度则比图3的G短路过孔长度更长,所以去噪性能比较差,带来的电磁辐射也就比图3更大了。For Figure 3, the decoupling effect of the top plane capacitor is relatively poor at low frequencies, and the current is more likely to flow through the P short circuit path and the subsequent bottom plane capacitor to flow and form a loop. At high frequencies, the decoupling effect of the top plane capacitor is greatly improved, and the current Select the top plane capacitor and G short circuit to flow through the hole and form a loop. The analysis of Figure 4 is similar, except that the short-circuit hole through which the current passes at low frequencies is the G short-circuit hole, and the short-circuit hole through which the current passes at high frequencies is the P short-circuit hole. Observing Figure 3 and Figure 4, it can be seen that the path of the short-circuit hole is different for the asymmetric and symmetrical stacks. At low frequencies, the length of the G-short-circuit hole in Figure 4 is shorter than that of the P-short-circuit hole in Figure 3, and the corresponding parasitic The inductance and the impedance it brings are also small, so the noise decoupling performance is better, and the electromagnetic radiation generated will be smaller. At high frequencies, the length of the P short-circuit via in Figure 4 is longer than that of the G short-circuit via in Figure 3, so the denoising performance is relatively poor, and the electromagnetic radiation it brings is greater than that in Figure 3.

所以低频时的EMI抑制采用对称的叠层设计,高频时的EMI抑制采用非对称式的叠层结构。Therefore, the EMI suppression at low frequencies adopts a symmetrical stack design, and the EMI suppression at high frequencies adopts an asymmetric stack structure.

3、短路过孔墙的设计。3. Design of short-circuit via wall.

在PCB板的边沿四周只要用短路孔将上下的嵌入式平面去耦电容连接起来,便可实现对电源噪声的有效管理,从而杜绝平面间噪声,短路过孔墙的主要设计步骤如下:Around the edge of the PCB board, as long as the upper and lower embedded plane decoupling capacitors are connected with short-circuit holes, the effective management of power supply noise can be realized, thereby eliminating noise between planes. The main design steps of the short-circuit via wall are as follows:

(1)过孔、焊盘、反焊盘尺寸的确定。(1) Determination of the dimensions of vias, pads, and anti-pads.

过孔的连接属于非理想互联,会带来阻抗突变,反射等问题。焊盘是过孔与走线在交接处的相融部分,目的是尽量使交接处阻抗匹配。过孔通过不必要连接的平面使会形成反焊盘,半径稍大于过,俗称出砂孔。从成本和信号质量两方面考虑,选择合理尺寸的过孔大小,本发明选择的过孔半径大小为0.15mm。出砂孔相当于平面有一个微小的开槽,会破坏平面的连续性,使得平面的回路电感变大,电磁完整性变差,所以再设计中应当尽量使用小的出砂孔并使出砂孔间的距离尽量大。The connection of via holes is a non-ideal interconnection, which will cause problems such as impedance mutation and reflection. The pad is the fusion part of the via and the trace at the junction, and the purpose is to match the impedance of the junction as much as possible. The via hole will form an anti-pad through the plane that is not necessary to connect, and the radius is slightly larger than the via, commonly known as the sand hole. In consideration of cost and signal quality, a reasonable via hole size is selected, and the radius of the via hole selected in the present invention is 0.15 mm. The sand outlet hole is equivalent to a tiny slot on the plane, which will destroy the continuity of the plane, increase the loop inductance of the plane, and deteriorate the electromagnetic integrity. Therefore, in the redesign, try to use small sand outlet holes and make the sand outlet The distance between the holes should be as large as possible.

(2)过孔周期的确定。(2) Determination of the via cycle.

短路过孔的周期可以根据如下公式计算:The period of the short-circuit via can be calculated according to the following formula:

其中fc表示短路过孔的转折频率,C0为真空中的光速,k是一个修正系数,值为0.13,p为短路孔分布周期,r为短路孔半径,εr为介质的介电常数。Where f c represents the corner frequency of the short-circuit via, C 0 is the speed of light in vacuum, k is a correction coefficient with a value of 0.13, p is the distribution period of the short-circuit hole, r is the radius of the short-circuit hole, and εr is the dielectric constant of the medium.

每一种周期和半径的短路孔去耦墙设计都对应着一个辐射抑制带,周期越小,半径越大,抑制带越宽,我们称这个抑制带的上限频率为短路孔的转折频率。在实际设计中,如果知道了所需要的转折频率和短路孔的半径,根据上面的公式就能求出短路过孔的周期。Each short-circuit hole decoupling wall design with period and radius corresponds to a radiation suppression zone. The smaller the period, the larger the radius and the wider the suppression zone. We call the upper limit frequency of this suppression zone the corner frequency of the short-circuit hole. In actual design, if the required corner frequency and the radius of the short-circuit hole are known, the period of the short-circuit via can be calculated according to the above formula.

(3)短路孔连接方式的选择(3) Selection of short-circuit hole connection method

短路孔有三种连接方式,G短路过孔、P短路过孔和P/G短路过孔,分别对应着图5、6、7。一般情况下,只对电源层的P短路过孔连接和只对地层的G短路过孔连接效果都差不多,但是都没有同时将电源层P和地层G都用短路过孔连接的效果好,所以一般情况下都选择P/G短路过孔连接。There are three connection methods for short-circuit holes, G-short-circuit vias, P-short-circuit vias, and P/G short-circuit vias, corresponding to Figures 5, 6, and 7, respectively. Under normal circumstances, the effect of connecting only the P short-circuit vias on the power layer and the G short-circuit vias only on the ground layer is similar, but the effect of connecting both the power layer P and the ground layer G with short-circuit vias at the same time is not good, so In general, P/G short-circuit via connection is selected.

短路过孔周期过大,应该使用非对称式的叠层和单一的G短路过孔,如果短路过孔的周期足够小,应该使用非对称式的叠层加混合P/G短路孔设计。If the period of the short-circuit via is too large, an asymmetric stack and a single G short-circuit via should be used. If the period of the short-circuit via is small enough, an asymmetric stack plus a mixed P/G short-circuit design should be used.

4、高频等效设计4. High frequency equivalent design

由薄电介质和电源地平面对构成的嵌入式平面电容,如图2所示,由于较大的分布电容在高频段可以看作交流短路,由此,电源地平面对可以视为无限小阻抗的短路。这样一个嵌入式平面电容可视为一个平面,在这种情况下,嵌入式平面电容就可视为接地短路孔,如图8所示。The embedded planar capacitance composed of a thin dielectric and the power ground plane pair, as shown in Figure 2, can be regarded as an AC short circuit in the high frequency band due to the large distributed capacitance, so the power ground plane pair can be regarded as an infinitely small impedance short circuit. Such an embedded planar capacitor can be regarded as a plane. In this case, the embedded planar capacitor can be regarded as a ground short-circuit hole, as shown in FIG. 8 .

显然,本发明的上述实施例仅仅是为清楚地说明本发明所作的举例,而并非是对本发明的实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明权利要求的保护范围之内。Apparently, the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, rather than limiting the implementation of the present invention. For those of ordinary skill in the art, other changes or changes in different forms can be made on the basis of the above description. It is not necessary and impossible to exhaustively list all the implementation manners here. All modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the claims of the present invention.

Claims (6)

1.一种高效抑制边沿辐射的高密度PCB板,其特征在于:采用非对称式的叠层结构或对称式的叠层结构,其中所述非对称式的叠层结构由若干个从上到下依次分布的地层-电源层对构成,其中所述地层-电源层对中地层位于电源层的顶部;所述对称式的叠层结构由若干个从上到下依次分布的电源层-地层-电源层对构成,其中所述地层设置在两层电源层之间;1. A high-density PCB board that efficiently suppresses edge radiation is characterized in that: an asymmetrical laminated structure or a symmetrical laminated structure is used, wherein the asymmetrical laminated structure consists of several from top to bottom The ground layer-power layer pair distributed in sequence below, wherein the ground layer-power layer pair is located on the top of the power layer; the symmetrical laminated structure consists of several power layer-ground layers- A pair of power supply layers, wherein the ground layer is arranged between two power supply layers; 非对称式的叠层结构和对称式的叠层结构中,相邻的地层与电源层之间设置有一层高介电常数的介质层,地层、电源层与介质层贴合;所述高介电常数的介质层的介电常数大于3.7;In the asymmetric laminated structure and the symmetrical laminated structure, a dielectric layer with a high dielectric constant is provided between the adjacent ground layer and the power supply layer, and the ground layer, the power supply layer and the dielectric layer are bonded together; the high dielectric constant The dielectric constant of the dielectric layer is greater than 3.7; 非对称式的叠层结构和对称式的叠层结构中,所有的电源层/地层通过短路过孔进行连接。In the asymmetric stacked structure and the symmetrical stacked structure, all power planes/ground planes are connected through short-circuit vias. 2.根据权利要求1所述的高效抑制边沿辐射的高密度PCB板,其特征在于:所述介质层的厚度为0.4mm。2. The high-density PCB board for efficiently suppressing edge radiation according to claim 1, characterized in that: the thickness of the dielectric layer is 0.4mm. 3.根据权利要求2所述的高效抑制边沿辐射的高密度PCB板,其特征在于:所述介质层的厚度为0.01mm,介电常数为20。3. The high-density PCB board capable of efficiently suppressing edge radiation according to claim 2, wherein the dielectric layer has a thickness of 0.01 mm and a dielectric constant of 20. 4.根据权利要求1所述的高效抑制边沿辐射的高密度PCB板,其特征在于:所述非对称式的叠层结构或对称式的叠层结构中,电源层、地层的厚度一致。4. The high-density PCB board capable of efficiently suppressing edge radiation according to claim 1, characterized in that: in the asymmetric laminated structure or the symmetrical laminated structure, the thickness of the power supply layer and the ground layer are the same. 5.根据权利要求1所述的高效抑制边沿辐射的高密度PCB板,其特征在于:所述短路过孔的半径为0.15mm。5. The high-density PCB board capable of efficiently suppressing edge radiation according to claim 1, characterized in that: the radius of the short-circuit via hole is 0.15 mm. 6.一种边沿辐射抑制方法,其特征在于:通过对权利要求1~5任一项所述高密度PCB板的叠层结构进行选择以及对短路过孔的设计来抑制边沿辐射,包括以下步骤:6. A method for suppressing edge radiation, characterized in that: suppressing edge radiation by selecting the laminated structure of the high-density PCB board described in any one of claims 1 to 5 and designing short-circuit vias, comprising the following steps : S1.判断EMI干扰为低频干扰还是高频干扰,若为低频干扰,则使高密度PCB板采用对称式的叠层结构,若为高频干扰,则使高密度PCB板采用非对称式的叠层结构;S1. Determine whether the EMI interference is low-frequency interference or high-frequency interference. If it is low-frequency interference, use a symmetrical laminated structure for the high-density PCB board. If it is high-frequency interference, use an asymmetrical laminated structure for the high-density PCB board. layer structure; S2.计算短路过孔的周期,若短路过孔的周期大于20H,则使高密度PCB板采用非对称式的叠层结构,且使短路过孔只将所有的地层连接起来;若短路过孔的周期小于20H,则使则使高密度PCB板采用对称式的叠层结构,并使短路过孔将所有的地层、所有的电源层连接起来;S2. Calculate the period of the short-circuit via. If the period of the short-circuit via is greater than 20H, the high-density PCB board adopts an asymmetric laminated structure, and the short-circuit via only connects all the ground layers; if the short-circuit via If the period is less than 20H, the high-density PCB board adopts a symmetrical laminated structure, and the short-circuit via holes connect all ground layers and all power layers; S3.若S1、S2确定的叠层结构相冲突,则采用步骤S1确定的叠层结构。S3. If the stacked structure determined in S1 and S2 conflicts, adopt the stacked structure determined in step S1.
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