CN105590865A - Methods Of Forming Replacement Gate Structures On FINFET Devices And The Resulting Devices - Google Patents

Abstract

The present invention relates to a method of forming a replacement gate structure on a FINFET device and the resulting device. Among other things, the present disclosure discloses a method comprising, among other methods, forming a fin having an upper surface and a plurality of side surfaces, forming a low density oxide material having a density less than 1.8 grams per cubic centimeter and associated with the fin. The top surface is in contact with the side surface, and a sacrificial gate structure of sacrificial gate material on and in contact with the top surface of the low density oxide material, and forms sidewall spacers adjacent to the sacrificial gate structure. The method further includes removing the sacrificial gate material to thereby expose the low density oxide material to define a replacement gate hole, and forming a replacement gate structure in the replacement gate hole.

Description

Method of forming a replacement gate structure on a FINFET device and the resulting device

technical field

The present invention relates generally to the fabrication of semiconductor devices, and more particularly to various novel methods of forming replacement gate structures on FinFET devices and the resulting devices.

Background technique

In modern integrated circuits, such as microprocessors, memory devices, etc., a large number of circuit devices, especially transistors, are arranged on a limited chip area. Transistors come in various shapes and forms, eg, planar transistors, FinFETs, nanowire devices, and the like. These transistors are usually NMOS (N-Type Field Effect Transistor) or PMOS (P-Type Field Effect Transistor) type devices, where the "N" and "P" designations are based on the source/drain design used to create the device doping type. The so-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refer to integrated circuit products manufactured with NMOS and PMOS transistor devices. Regardless of the physical configuration of the transistor devices, each device includes drain and source regions, and a gate electrode structure above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conducting channel region is formed between the drain region and the source region.

FIG. 1A shows a perspective view of a prior art, FinFET semiconductor device 10 formed over a semiconductor substrate 12, which will be referred to for convenience of illustration. At a very high level, a conventional FinFET Some basic characteristics of the device. In this example, FinFET device 10 includes three exemplary fins 14 , a gate structure 16 , sidewall spacers 18 , and a gate cap 20 . Gate structure 16 typically includes a layer of insulating material (not shown separately), such as a high-k insulating material layer or silicon dioxide, and one or more layers of conductive material (eg, metal and/or polysilicon) that serve as the grid electrode. Fin 14 has a three-dimensional configuration: height 14H, width 14W, and axial length 14L. Axial length 14L corresponds to the direction of current travel, eg, the gate length (GL) of device 10 when it is operational. The portion of the fin 14 covered by the gate structure 16 is the channel region of the FinFET device 10 . In a conventional process flow, the portion of the fin portion 14 located at the periphery of the spacer 18, that is, the source/drain region of the device 10, is grown additional semiconductor material on the device 10 by performing one or more epitaxial growth processes. on the fins in the source/drain regions of the region to increase or even merge together (this situation is not shown in FIG. 1A ).

FIG. 1B shows a simplified plan view of a conventional FinFET device including three exemplary fins 14 . A cross-sectional view of device 10 is obtained from gate structure 16 shown in FIG. 1C. Referring to FIG. 1C , device 10 includes a layer 22 of insulating material between fins 14 , another layer of insulating material 24 over gate capping layer 20 , and a gate contact structure 28 electrically coupled to gate structure 16 . The device 10 shown in FIG. 1C is a tri-gate (or tri-gate) FinFET device. That is, during operation, a very shallow conductive region 26 (shown only in the middle fin in FIG. 1C ) is created to provide a current path or channel to flow from the source to the drain. . The conductive region 26 forms the inward side surface 14S and is located below the top surface 14T of the fin 14 . As shown, the overall gate length (GL) of the FinFET device 10 and the overall width (GW) of the FinFET device 10 are all oriented substantially parallel to the horizontal plane 12A of the substrate 10 .

For many early device technology generations, the gate electrode structure of most transistor components consisted of multiple silicon-based materials, such as silicon dioxide and/or silicon oxynitride gate insulating layers, combined with polysilicon gate electrodes. However, as transistor components have been aggressively shrunk, channel lengths have progressively become smaller, and many newer generation devices employ gate electrode stacks that include alternative materials in an effort to avoid short-channel effects that differ from conventional silicon-based materials. Transistors for smaller channel lengths are closely related. For example, in some aggressively scaled transistor devices, which may have channel lengths on the order of 14 to 32 nanometers, the gate structure includes a high-k gate insulating layer (k value of 10 or greater) and one or more A metal layer, the so-called high-k dielectric/metal gate (HK/MG) configuration, has been shown to provide significantly enhanced performance over the hitherto more commonly used silicon dioxide/polysilicon (SiO/poly) configuration.

One known processing method that has been used to form transistors with high-k/metal gate structures is the so-called "gate last" or "replacement gate" technique. In replacement gate technology, so-called "dummy" or sacrificial gate structures are initially formed and maintained in place while performing many process operations to form the device, for example, formation of doped source/drain regions, performing anneals process to repair damage to the substrate caused by the ion implantation process, and to activate the implanted dopant material. At some point in the process, the sacrificial gate structure is removed to define a gate hole where the final HK/MG gate structure of the device is formed.

The gate electrode structures formed on FinFET devices present several unique challenges. Typically the fins 14 are formed by performing an etching process by patterning the hard mask layer to define a plurality of trenches in the substrate. The portion of the substrate 12 covered by the patterned hard mask layer is the fin 14 . Typical hard mask layers include a thermally grown silicon dioxide layer (pad oxide) formed on the substrate 12 and a silicon nitride layer (pad nitride) formed on the pad oxide layer. The nitride and oxide pads are then patterned using photolithography and etching techniques to define the patterned hard mask layer. In today's advanced generation technology, the fin 14 of the FinFET device is relatively thin, and thus easily damaged if the patterned hard mask is not thick enough. In addition, if the oxide pad portion of the hard mask layer is too thick, it is difficult to ensure that the portion of the oxide pad can be completely removed, so it is difficult to form a tri-gate (tri-gate) FinFET device. Generally, the process step, ie performing the etching process module or step to etch the substrate 12 to define the fins 14 , is not easily transferable when the structure of the fins 14 is changed. That is, if one parameter, such as fin height, fin width, or hardmask thickness, is changed, the entire etch process module needs to be reworked, ie, the old etch process module cannot be easily used with different Physical parameters of the fin 14. This would result in consuming a lot of research and development time and resources to create a new etch process module that can be used in a manufacturing facility to form a newly designed fin. These questions, when it comes to the formation of alternative gate structures for FinFET devices, may be even more uncertain.

Another problem encountered in manufacturing FinFET devices using conventional manufacturing techniques is related to surface topography control. Typically, when the trenches are formed to define the fins 14, recesses 22 of insulating material are formed between the fins 14 in the trenches. Thereafter, a sacrificial gate insulating layer is thermally grown on the exposed portion of the fin 14 above the recessed layer 22 of insulating material. Next, a sacrificial gate material, such as amorphous silicon, is blanket deposited on the substrate 12 to overfill the trench. Given the topography of the fins 14 and the trenches, the upper surface of the accumulation of sacrificial gate material is uneven and must be planarized (by CMP) before the gate capping material, eg silicon nitride, is formed. The planarization process is a timed process, ie the polishing process does not stop at another material layer. Therefore, the thickness of the sacrificial gate material above the upper surface of the fin 14 is controlled by the duration of the polishing process. Any variation in the polishing rate and/or the duration of the polishing process results in an undesired variation in the thickness of the sacrificial gate material. Such thickness variations can occur from wafer-to-wafer and/or lot-to-lot of the wafer and create further manufacturing problems.

The present invention relates to methods of forming replacement gate structures on FinFET devices and resulting devices that solve or reduce one or more of the above-mentioned problems.

Contents of the invention

The following presents a simplified summary of the invention in order to provide a basic understanding of the invention in some aspects. This summary is not an extensive overview of the invention. It is not intended to identify key or critical components of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

In general, the present invention relates to various novel methods of forming replacement gate structures on FinFET devices and the resulting devices. An illustrative method disclosed herein includes, among other methods, forming a plurality of trenches in a semiconductor substrate to define a fin having an upper surface and a plurality of side surfaces, forming a sacrificial gate structure including having a density of a low density oxide material of less than 1.8 g/cm3 in the plurality of trenches and in contact with the upper surface and the side surface of the fin, the low density oxide material having a substantially planar upper surface, and at a height higher than the upper surface of the fin, and a sacrificial gate material on and in contact with the upper surface of the low density oxide material and forming sidewall spacers adjacent to the sacrificial gate material and the sacrificial gate structure of the low density oxide material. In this embodiment, the method further includes performing a first etch process to remove the sacrificial gate material to thereby expose the low density oxide material maintained on the fin throughout the first etch process. location on the upper surface and the side surface of the fin portion, removing the exposed low density oxide material to define a replacement gate hole, and thereby exposing the upper surface and the fin portion within the replacement gate hole A side surface, and a replacement gate structure is formed around the exposed upper surface and the side surface of the fin in the replacement gate hole.

Description of drawings

The present invention may be understood by reference to the following and in conjunction with the accompanying drawings, in which like reference numerals identify like components, in which:

1A to 1C show prior art FinFET devices.

FIGS. 2A to 2T show various exemplary novel methods of forming replacement gate structures on FinFET devices disclosed in the present invention and the resulting novel devices.

While the presently disclosed subject matter is amenable to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and described in detail herein. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all within the spirit and scope of the invention as defined by the appended claims. All modifications, equivalents and substitutes.

detailed description

Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It should of course be understood that in the development of any such actual embodiment, many implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Another embodiment. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this invention.

The subject matter will now be described with reference to the accompanying drawings. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only so as not to obscure the present invention with details that are well known to those skilled in the art. Nevertheless, the accompanying drawings are included to describe and explain illustrative examples of the present invention. The words and phrases used herein should be understood and interpreted to have the same meaning as those understood by those skilled in the relevant art. Consistent use of a term or phrase herein is not intended to imply a specific definition, that is, a definition that is different from the commonly used meaning understood by those skilled in the art. To the extent that the term or phrase has a special meaning, i.e., a meaning other than that understood by those skilled in the art, such a specific definition will be clearly specified, and the definition of the term or phrase is directly and explicitly provided in the description. special definition. It will be apparent to those skilled in the art after a complete reading of this specification that the methods disclosed in the present invention can be used to manufacture various devices, including, but not limited to, logic devices, memory devices, etc., and that the devices can be NMOS or PMOS devices.

As will be understood by those skilled in the art after reading this specification, various doped regions, eg, source/drain regions, halogen implant regions, well regions, etc., are not shown in the drawings. Of course, the invention disclosed herein should not be considered limited to the illustrative examples shown and described herein. The various components and structures of the integrated circuit device 100 disclosed herein can be formed using a variety of different materials and by performing various known techniques, such as chemical vapor deposition (CVD) processes, atomic layer deposition (ALD ) process, thermal growth process, spin coating process and so on. The thickness of these various material layers may also vary, depending on the particular application. Various illustrative embodiments of the methods and devices disclosed herein will now be described in greater detail with reference to the accompanying figures.

2A-2T show various views of an illustrative embodiment of a FinFET device 100 formed using the disclosed methods. These figures also include simplified plan views (in the upper right corner) of device 100 showing where the various cross-sectional views described in the following figures would be taken. More specifically, viewing angle "X-X" is taken through the source/drain region of device 100, across the long axis of the fin (that is, substantially parallel to the gate width of device 100 direction); the viewing angle "Y-Y" is taken from a cross-sectional view through the gap between the fins, substantially parallel to the gate length direction of the device 100 (that is, the direction of current conduction); and the viewing angle "Z-Z" is taken through the The long axis of the fin, a cross-sectional view transverse to the long axis of the gate structure (ie, in the direction of current conduction of the device).

In the examples described herein, the FinFET device 100 will be formed in and over a semiconductor substrate 102 . The substrate 102 may have various structural configurations, such as silicon-on-insulator (SOI) or silicon-on-insulator germanium (SOGI) including a bulk semiconductor layer, a buried insulating layer, and an active layer. Alternatively, the substrate may have a simple mass configuration. The substrate 102 may be made of silicon or a material other than silicon. Accordingly, the terms "substrate" or "semiconductor substrate" should be understood to cover all semiconductor materials and all forms of all materials.

FIG. 2A shows device 100 at a fabrication node after several process runs have been performed. First, a patterned etch mask 104, such as a combination of a silicon dioxide layer (eg, an oxide pad - not shown separately) and a silicon nitride layer (eg, a nitride pad - not shown separately), is formed on a substrate 102. . In some examples, the pad oxide can be omitted if desired. Thereafter, one or more etch processes are performed through the patterned etch mask 104 to define a plurality of trenches 105 in the substrate 102 . This results in the formation of a plurality of fins 106 . The illustrative FinFET device 100 disclosed herein is depicted as having two exemplary fins 106 . However, as will be understood by those skilled in the art after reading this specification, the methods and devices disclosed in the present invention may be employed in fabricating FinFET devices having any number of fins. Fins 106 extend laterally into and out of the drawing page in the direction of current conduction of device 100 , and into what will become source/drain regions of device 100 .

Continuing to refer to FIG. 2A , the overall size, shape, and configuration of the trenches 105 and fins 106 may vary depending on the particular embodiment. The depth and width of trenches 105 may vary depending on the particular embodiment. In an illustrative embodiment, the overall depth of trench 105 (relative to the upper surface of substrate 102 ) may range from about 20 to 50 nanometers, according to current technology. In the illustrative embodiment shown in this figure, trenches 105 and fins 106 will simply be shown as having generally rectangular portions and cross-sections. In an actual real world device, the sidewalls of the trench 105 may taper slightly inwardly, although this configuration is not shown in the figures. Accordingly, the size and configuration of trenches 105 and fins 106, as well as the manner in which they are formed, should not be considered limiting of the invention. For ease of disclosure, only substantially rectangular trenches 105 and fins 106 having substantially rectangular cross-sectional structures will be shown in the drawings.

FIG. 2B shows the FinFET device 100 after forming a recessed layer of insulating material 108 , such as silicon dioxide, in the trench 105 between the fin structures 106 . The insulating material recessed layer 108 can be formed by overfilling the trench 105 with an insulating material, performing a CMP process on the insulating material layer to stop on the upper surface of the patterned hard mask layer 104, and performing a recessed layer on the insulating material layer 108. An etching process to recess the upper surface 108S of the insulating material layer 108 to a desired height within the trench 105 .

FIG. 2C shows the FinFET device 100 after performing a gas cluster ion beam (GCIB) process to form an etch stop layer 110 at the bottom of the trench 105 and over the patterned hard mask layer 104 . For ease of illustration, etch stop layer 110 has different cross-hatching relative to patterned hard mask 104 . In fact, the etch stop layer 110 and the patterned hard mask layer 104 can be composed of the same material, such as silicon nitride, or they can be made of materials that exhibit similar etch characteristics, so that they can both be used in a common etch process. be removed. In general, the GCIB process may be performed so as to result in material 110 being formed on substantially horizontally oriented planes, such as over hardmask layer 104 , without forming a significant amount of material 110 on vertically oriented planes. The thickness of the etch stop layer 110 can vary depending on the particular embodiment, for example, about 2 to 10 nanometers.

FIG. 2D shows FinFET device 100 with material layer 112 formed between fins 106 above etch stop layer 110 . In one illustrative example, material layer 112 may be a low density flowable oxide material or OPL material. Material layer 112 may have sacrificial properties, or it may be part of the finished device, depending on the fabrication process chosen to form device 100 and the material chosen for material layer 112 . In a particular example, material layer 112 may be a low density oxide material, such as a flowable oxide material, having a density less than 1.8 g/cm3. The low density oxide material layer 112 can be deposited to a desired thickness by using the relatively new Novellus flowable oxidation process, at least some aspects of which are believed to be disclosed in U.S. Patent No. 7,915,139 , which is hereby incorporated by reference in its entirety. Generally, the Novartis process is a relatively low temperature process whereby the precursor materials used in the process flow into the lowest layer in the structure, in this case the trenches between the fins 106 above the etch stop layer 110 area in groove 105. Parameters of the low density oxide deposition process, such as the length of the deposition process, determine the final thickness of the low density oxide material layer 112, which may vary depending on the particular application. In other embodiments, the low density oxide material layer 112 may initially be formed thicker than its final desired thickness, and a recess etch process may be performed to reduce its thickness to its final desired thickness. Regardless of the process technology used, the final thickness of the low density oxide material layer 112 can vary depending on the particular application, eg, 5 to 10 nanometers. As noted above, in a particular embodiment, the low density oxide material discussed in this specification may have a density of less than 1.8 grams per cubic centimeter. Such low-density oxide materials can be considered relatively low-quality oxide materials compared to other higher-quality oxide materials, such as thermally grown oxide materials (density equal to about 2.27 g/cm3), PECVD deposited oxide materials (density is about 2.1 g/cm3), HARP oxide material (density is about 2.0 g/cm3), HDP oxide material (density is about 2.16 g/cm3) and so on. In the case where the material layer 112 is an OPL material, the OPL layer 112 may be formed by overfilling the trench with OPL and then recessing the OPL material to the desired height level within the trench 105, that is, until it is located at the fin Portions of etch stop layer 110 and hard mask layer 104 above 106 are exposed.

FIG. 2E shows an embodiment in which the material layer 112 is a low density flowable oxide material layer 112 . The FinFET device 100 is shown after performing one or more etch processes to remove portions of the etch stop layer 110 and hard mask layer 104 not covered by the low density oxide material layer 112 . This process operates to clear the upper surface 106S of the fin 106 and the side surface 106X of the fin of such material. The process operation would be the same if the material layer 112 was a recessed layer of OPL material. As discussed more fully below, where material layer 112 is a low density oxide material, it may or may not remain in place after performing the etching process. In case the material layer 112 is made of an OPL material, the OPL material is typically stripped after performing the etching process to thereby expose the etch stop layer 110 .

FIG. 2F shows FinFET device 100 after performing a second LDOX deposition process to form LDOX material layer 114 over etch stop layer 110 and between fins 106 . As shown, in one embodiment, the low density oxide material layer 114 is formed to a thickness such that its upper surface is higher than the upper surface 106S of the fin 106 . As mentioned above, in an exemplary example, the low density oxide material layer 112 may be removed prior to the formation of the low density oxide material layer 114 . In other embodiments, the low density oxide material layer 114 may simply be formed on top of the low density oxide material layer 112 (FIG. 2F includes dashed lines reflecting the latter technique). As before, the low density oxide material layer 114 can be deposited to its desired thickness by using the relatively new Novell flowable oxidation process described above, or it can be formed by performing a deposition and etch back process, as described above. Regardless of the process technology employed, in an exemplary embodiment, the final thickness of the low density oxide material layer 114 is a thickness 114T, which may be approximately 2 to 10 nanometers above the upper surface 106S of the fin 106 .

In another embodiment, as shown in FIG. 2G , a CMP process may be performed on the low-density oxide material layer 114 , stopping at and exposing the upper surface 106S of the fin 106 . Thereafter, a thin layer of silicon dioxide 107 , eg, 3 to 5 nm, may be deposited on the exposed upper surface 106S and the planarized upper surface of the low density oxide material layer 114 . For ease of disclosure, the remaining figures will show the fabrication flow, where the additional oxide layer 107 will not be formed as described in this paragraph.

The present invention will be disclosed in the context of forming the gate structure of the FinFET device 100 by performing a replacement gate process. Thus, FIG. 2H shows device 100 after deposition and patterning of sacrificial gate material 116 and gate capping layer 118 over low density oxide material layer 114 using conventional masking and etching techniques. Generally, the sacrificial gate material 116 includes polysilicon or amorphous silicon, and the gate capping layer 118 includes a material such as silicon nitride. The thickness of these materials can vary depending on the particular application. It should be noted that, unlike prior fabrication techniques, the patterned sacrificial gate material 116 is formed on the low density oxide material 114, that is, it is not formed on the thermal oxide layer previously formed on the fin 106, including The upper surface 106S of the fin 106 is as done in at least some prior art manufacturing techniques. In addition, using the method disclosed in the present invention, the sacrificial gate material 116 is a substantially planar structure formed on or over the substantially planar upper surface of the low-density oxide layer 114, thereby eliminating or reducing the background section of this specification. The non-uniform topography problem is described where the sacrificial gate electrode material is formed in the trench between the fins. Where the additional oxide layer 107 described above is formed, the patterned sacrificial gate material 116 will be formed on the substantially planar upper surface of the additional thin oxide material layer 107 . Using these process techniques, the sacrificial gate material layer 116 can be formed such that it has a substantially uniform thickness across the substrate.

2I shows after removing the low density oxide material relative to the etch stop layer 110 and the fins 106 by performing an anisotropic etch process to remove exposed portions of the low density oxide material layer 114 (and 112, if present). The fin field effect transistor device 100. Note that exposed portions of the low density oxide material layer 114 (and 112 , if present) remain under the patterned sacrificial gate material 116 . With the formation of the additional oxide layer 107 described above, only a portion of the additional thin layer of oxide material 107 will be located under the patterned sacrificial gate material 116 above the upper surface 106S of the fin 106 . The additional oxide layer 107 (not shown) will be located between the patterned low density oxide material layer 114 and the patterned sacrificial gate material 116 at the viewing angle Y-Y of FIG. 2I .

FIG. 2J shows, in a simplified depiction, sidewall spacers 120 adjacent to patterned sacrificial gate material 116, patterned gate capping layer 118, and low density oxide material 114 (and 112, if present) underlying these structures. The FinFET device 100 after the patterned portion is formed. Collectively, the patterned portions of sacrificial gate material 116 and low density oxide material 114 ( 112 ) may be considered a sacrificial gate structure. The sidewall spacers 120 are formed by depositing a layer of spacer material (eg, silicon nitride) and thereafter performing an anisotropic etch process. Spacer 120 may have any desired thickness.

FIG. 2K shows the FinFET device 100 after performing several process operations. First, an optional fin merging process is performed, in which epitaxial semiconductor material 122 is illustratively shown grown on the portion of fin 106 located in the source/drain region of device 100 . Dashed line 106Y shows the outline of initial fin structure 106 . Of course, the formation of such epitaxial material 122 in the source/drain regions of device 100 is not required to practice the invention. Thereafter, another layer of insulating material 124 , such as silicon dioxide, is blanket deposited over the device 100 . Then, one or more chemical mechanical polishing (CMP) processes are performed to planarize the upper surface of the insulating material 124 and the upper surface of the gate capping layer 118 .

FIG. 2L shows the FinFET device 100 after performing a timed etch back process to remove the gate capping layer 118 and portions of the spacers 120 selectively with respect to surrounding structures. Special cross-sectional view (A-A) taken from viewing angle Y-Y of Fig. 2L. Viewing angle A-A is taken from the gate length direction of device 100 (only a single fin 106 is shown in viewing angle A-A). As best shown in View A-A, the low density oxide material 114 (112), in its entirety, is considered to be on and in contact with the etch stop layer 110, if any, and the low density oxide material is in the The upper surface 106S and the side surface 106Y of the fin portion 106 are formed on and in contact with them. That is, the low density oxide material 114 ( 112 ) encapsulates the upper and side surfaces of the fin 106 . Additionally, as described above, the low density oxide material defines a substantially planar upper surface 114S over which sacrificial gate material 116 is formed. Note that the patterned sacrificial gate material 116 formed by the method disclosed in the present invention is substantially planar and has a substantially uniform thickness throughout the substrate. obtained from the cross-sectional view. Such a substantially planar layer for this sacrificial gate structure of a FinFET device is in contrast to the "step profile" of the polysilicon or amorphous silicon portion of the sacrificial gate structure formed on a FinFET device using existing fabrication techniques. ” in stark contrast, where thermal oxide is formed on the fins prior to forming the polysilicon or amorphous silicon material for the sacrificial gate structure in the trench between the fins. With the insulating material layer 107 formed (see FIG. 2G ), a substantially planar material layer 116 for the sacrificial gate structure of the FinFET device 100 will be formed on the insulating material layer 107 and contact with it.

FIG. 2M shows the FinFET device 100 with one or more planarization processes (eg, CMP processes) performed on the insulating material layer 124 , and the planarization process stops at the sacrificial material layer 116 .

FIG. 2N shows the FinFET device 100 after performing a timed etch back process to recess the upper surface of the insulating material layer 124 from the surrounding material. The amount of dishing can vary depending on the particular application, for example about 15 nanometers. It should be noted that, in the example shown, the recessed upper surface of the insulating material layer 124 is at a level lower than the upper surfaces of both the spacer 120 and the sacrificial material layer 116 .

FIG. 2O shows the FinFET device 100 after forming a thin insulating capping layer 121 over the device 100 by performing a conformal deposition process. In an illustrative embodiment, the insulating capping layer 121 may include the same material as the sidewall spacer 120 , such as silicon nitride. As discussed more fully below, the purpose of the insulating protective layer 121 is to protect the insulating material layer 124 from consumption when the low density oxide material is removed from between the spacers 120 . In addition, although the embodiments shown herein show that the low-density oxide material 114 is formed in the space defined by the spacers 120, due to the presence of the insulating protective layer 121, the high-quality and denser oxide material is different from the low-density oxide material, such as thermal Growth oxide, HARP oxide or HDP oxide, may be formed in the space between the spacers 120 . Such higher quality and dense oxide material may be more difficult to remove than the low density oxide material shown in the present invention, however, in such cases, the insulating protective layer 121 is used to prevent the undesired removal of the insulating material layer 124. Consumed when such other higher quality oxidizing material is removed from the spaces between the spacers 120 .

FIG. 2P shows device 100 after depositing another layer of insulating material 123 over device 100 and performing a CMP process stopping behind insulating capping layer 121 . The insulating material 123 may include a material such as silicon dioxide.

FIG. 2Q shows the FinFET device 100 after performing a timed etch back process to remove exposed portions of the insulating capping layer 121 selectively with respect to the surrounding structures. This process operation exposes the sacrificial gate material 116 to be removed.

FIG. 2R shows FinFET device 100 after performing one or more etch processes to remove low density oxide material 114 ( 112 ) of sacrificial gate material 116 relative to the surrounding material and particularly underlying sacrificial gate material 118 . . The operation of the process results in the formation of voids 125 and exposes the low density oxide material 114 ( 112 ) located between the spacers 120 .

FIG. 2S shows the FinFET device 100 after performing another etch process through the cavity 125 to remove the exposed low density oxide material 114 ( 112 ) selectively relative to the surrounding structure. The etch process stops the etch stop layer 110 and the fins 106 in the channel region of the device. This process operation results in the formation of replacement gate holes 127 between spacers 120 and where the final replacement gate structure of device 100 will be formed. It should be noted that, as mentioned above, during this etching process, when the low-density oxide material 114 in the gate hole 127 is removed, the insulating material layer 123 will also be removed, but the insulating protective layer 121 will serve as an etch stop layer to prevent Insulating material 124 is removed from over the source/drain regions of device 100 .

Importantly, during the etch process shown in Figure 2S, a very fast cleaning process (eg, HF cleaning) can be employed to quickly remove the low density oxide material. In some cases, depending on the etchant used, the rate of removal of the low density oxide material can be about 100 times faster than the rate of removal of conventional thermally grown silicon dioxide material, which is The material that is sacrificial gate material 116 is formed on the upper surface and the side surface of fin 106 before being formed. Thus, using the methods disclosed herein, this surface of the fin 106 is less likely to be attacked and consumed when it is low density oxide material to be removed rather than thermally grown oxide material. Furthermore, as mentioned above, the presence of etch stop layer 110 above (view Y-Y) the insulating material 108 in the gate region allows it to effectively establish a "hard stop" during the etch process, allowing the exposed vertical The height is more precisely controlled and also becomes part of the channel region of device 100.

FIG. 2T shows the FinFET device 100 with a replacement gate structure 130 and a gate capping layer 132 (eg, silicon nitride) formed in the replacement gate hole 127 . The replacement gate structure 130 shown herein is intended to represent virtually any form of replacement gate structure that may be used in the manufacture of integrated circuit products. Typically, prior to forming the various material layers that will become part of the replacement gate structure 130 , a pre-cleaning process will be performed in an attempt to remove all foreign material from within the replacement gate hole 127 . Thereafter, the final gate structure 130 may be formed by sequentially depositing materials of the gate structure into the replacement gate hole 127 and over the insulating material layer 124, and then performing a CMP process to remove excess material over the insulating material layer 124, including Insulation protection layer 121. Next, a recess etch process is performed to recess the material in the gate hole 127 to create a space to form the gate capping layer 132 . A gate capping layer 132 is then formed over the recessed gate material and in place of the gate hole. The gate capping layer 132 may include various materials, such as silicon nitride, and it may be formed by overfilling the remainder of the replacement gate hole 127 with the gate capping material, after which a CMP process is performed to remove the insulating material layer stopped at Excess material on 124. As previously mentioned, the gate structure 130 may include a high-k insulating material layer (k value equal to or greater than 10) and one or more metal layers.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the processing steps described above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design shown in this specification, other than as described in the appended claims. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Please note that terms such as "first", "second", "third" or "fourth" are used to describe various processes or structures in this specification and in the appended claims These steps/structures are abbreviated as a reference and do not necessarily imply that these steps/structures are performed/formed in any order. Of course, this order of processes may or may not be required, depending on the exact claim language. Accordingly, the protection sought for this invention is as set forth in the appended claims.

Claims (21)

1. form a method for replacement gate structure at fin formula field-effect transistor device, its featureBe, the method comprises:

In Semiconductor substrate, form multiple grooves, so that definition has upper surface and multiple side tableThe fin of face;

Form sacrificial gate electrode structure, this sacrificial gate electrode structure comprises:

There is the low-density oxidation material that density is less than 1.8 grams/cc, be positioned at that these are manyIn individual groove, and contact this low-density oxygen with this side surface with this upper surface of this finIt is smooth upper surface substantially that formed material has, and its place height will be higher than this finThe height of this upper surface; And

Sacrificial gate material, be positioned on this upper surface of this low-density oxidation material and and itsContact;

Form sidewall spacer, adjacent to comprising this sacrificial gate material and this low-density oxidation materialThis sacrificial gate electrode structure of material;

Carry out the first etch process to remove this sacrificial gate material, to expose thus, this is low closeDegree oxidation material, this low-density oxidation material maintains this fin in whole this first etch processPosition on this upper surface of portion and this side surface;

Remove this low-density oxidation material exposing to define replacement gate hole, thus and sudden and violentBe exposed to this upper surface and this side surface of this fin in this replacement gate hole; And

Shape around this upper surface exposing of this fin and this side surface in this replacement gate holeBecome replacement gate structure.

2. the method for claim 1, is characterized in that, is forming this sacrifice drain junctionsBefore structure, the method more comprises:

In the plurality of groove, form insulation material layer, make the upper surface of this insulation material layerHeight will be lower than the height of this upper surface of this fin; And

On this upper surface of this insulation material layer and above this upper surface of this fin, form erosionCarve stop-layer.

3. method as claimed in claim 2, is characterized in that, is forming this sacrifice drain junctionsBefore structure, the method more comprises:

Above this etching stopping layer being positioned on this insulation material layer, form material layer, this materialLayer has upper surface, and its position makes this etching of this upper surface top that is positioned at this finStop-layer comes out; And

Remove position this this etching stopping layer exposing above this upper surface of this fin.

4. method as claimed in claim 2, is characterized in that, this material layer is OPL materialOne of them of oxidation material maybe can flow.

5. the method for claim 1, is characterized in that, this sacrificial gate material comprisesOne of them of polysilicon or non-crystalline silicon.

6. the method for claim 1, is characterized in that, this replacement gate structure comprisesHigh k gate insulation material and at least one metal level.

7. the method for claim 1, is characterized in that, this low-density oxidation material isThe oxidation material that can flow, it forms by carrying out at least two roads oxide deposition technique that can flow.

8. the method for claim 1, is characterized in that, this low-density oxidation material isThe oxidation material that can flow, it forms by fill order's oxide deposition technique that can flow together.

9. the method for claim 1, is characterized in that, this low-density oxidation material isThe oxidation material that can flow, it is by removing the flowed oxidation material layer of previous formation, and thenOne oxide deposition technique that can flow of fill order forms.

10. the method for claim 1, is characterized in that, when wide by the grid of this deviceThe section that obtains of degree direction is observed, this sacrificial gate material be substantially have substantially on average thickThe planar structure of degree.

11. the method for claim 1, is characterized in that, are forming this sidewall spacerAfterwards, the method more comprises:

In the plurality of groove, the peripheral recessed layer of insulating materials that forms of the side direction of this distance piece, makes thisThe concave upper surface of the recessed layer of insulating materials be in lower than the height of the upper surface of this distance piece andLower than the height of the upper surface of this sacrificial gate material;

At this upper surface of this concave upper surface of the recessed layer of this insulating materials, this distance piece and shouldOn this upper surface of sacrificial gate material, form insulating protective layer;

Remove this insulating protective layer position in the portion above this distance piece and above this sacrificial gate materialPoint; And

To the remainder of this insulating protective layer in the recessed layer of this insulating materials top position, carry outThis first etch process, wherein, this remainder of this insulating protective layer is in this first etching workCan the recessed layer of this insulating materials of protection in the implementation of skill.

12. 1 kinds form the method for replacement gate structure, its feature at fin formula field-effect transistor deviceBe, the method comprises:

In Semiconductor substrate, form multiple grooves, so that definition has upper surface and multiple side tableThe fin of face;

In the plurality of groove, form the first insulation material layer, make this first insulation material layerConcave upper surface place height is lower than the height of this upper surface of this fin;

Carry out at least one technological operation with in this concave upper surface of this first insulation material layerForm etching stopping layer, remove this etching stopping layer simultaneously and stay above this etching stopping layerThis upper surface of this fin and this side surface;

In the plurality of groove, form the second insulation material layer, and with this upper surface of this finAnd this side surface, contact with the upper surface of this etching stopping layer in addition, this second insulating materialsIt is smooth substantially that the formation of layer makes the upper surface of this second insulation material layer, and its placeIt is highly the height higher than this upper surface of this fin;

On this upper surface of this second insulation material layer, form sacrificial gate material;

This sacrificial gate material of patterning and this second insulation material layer, to define sacrifice drain junctionsStructure;

Form sidewall spacer adjacent to comprising this sacrificial gate material and this second insulation material layerThis sacrificial gate electrode structure;

Carry out the first etch process to remove this sacrificial gate material between this distance piece, withThereby just expose this second insulation material layer, this second insulation material layer is in whole this first erosionIn carving technology, maintain the position on this upper surface and this side surface of this fin;

Carry out the second etch process, it is parked in this etching stopping layer, and removes that this exposesAt least a portion of the second insulating materials, thus to define replacement gate hole and expose at thisThis upper surface of this fin in replacement gate hole and this side surface; And

Shape around this upper surface exposing of this fin and this side surface in this replacement gate holeBecome replacement gate structure.

13. methods as claimed in claim 12, is characterized in that, shape in the plurality of grooveBecome this second insulation material layer comprise formation can flow oxidation material, CVD deposition oxidation material,HARP oxidation material or HDP oxidation material wherein at least one.

14. methods as claimed in claim 12, is characterized in that, are formed at the plurality of grooveIn this second insulation material layer be the oxidation material that can flow.

15. methods as claimed in claim 12, is characterized in that, when the grid by this deviceSection that width obtains is observed, this sacrificial gate material be substantially have substantially averageThe planar structure of thickness.

16. methods as claimed in claim 12, is characterized in that, shape in the plurality of grooveThis second insulation material layer becoming is to have the silica material that density is less than 1.8 grams/ccMaterial.

17. methods as claimed in claim 12, is characterized in that, are forming this sidewall spacersAfter part, the method more comprises:

In the plurality of groove, the peripheral recessed layer of insulating materials that forms of the side direction of this distance piece, makes thisThe concave upper surface of the recessed layer of insulating materials is the height being in lower than the upper surface of this distance piece, withAnd lower than the height of the upper surface of this sacrificial gate material;

At this upper surface of this concave upper surface of the recessed layer of this insulating materials, this distance piece and shouldOn this upper surface of sacrificial gate material, form insulating protective layer;

Remove this insulating protective layer position in the portion above this distance piece and above this sacrificial gate materialPoint; And

To the remainder of this insulating protective layer in the recessed layer of this insulating materials top position, carry outThis first etch process, wherein, this remainder of this insulating protective layer is in this first etching workCan the recessed layer of this insulating materials of protection in the implementation of skill.

18. 1 kinds form the method for replacement gate structure, its feature at fin formula field-effect transistor deviceBe, the method comprises:

In Semiconductor substrate, form multiple grooves, so that definition has upper surface and multiple side tableThe fin of face;

In the plurality of groove, form the first insulation material layer, make this first insulation material layerUpper surface place height is lower than the height of this upper surface of this fin;

On this upper surface of this first insulation material layer and square on this upper surface of this finBecome etching stopping layer;

In the plurality of groove, form the first oxidation material that density is less than 1.8 grams/ccLayer, and contact with the upper surface of this etching stopping layer and this side surface of this fin, this is first years oldIt is smooth substantially that the formation of oxidation material layer makes the upper surface of this first oxidation material layer,And place height is the height lower than this upper surface of this fin;

Remove at least this etching stopping layer from this upper surface top of this fin, be wherein positioned at thisThis upper surface of this fin and this side table of this fin of this upper surface top of one oxidation material layerFace is this etching stopping layer not;

In the plurality of groove, form the second oxidation material that density is less than 1.8 grams/ccLayer, and with this upper surface of this first oxidation material layer and this upper surface of this fin and this sideSurface Contact, the formation of this second oxidation material layer makes the upper surface of this second oxidation material layerSubstantially be smooth, and place height is the height higher than this upper surface of this fin;

On this upper surface of this second oxidation material layer, form sacrificial gate material;

This sacrificial gate material of patterning and this first and second oxidation materials layer, to define bagDraw together the sacrificial gate electrode structure of this sacrificial gate material and this first and second oxidation material layer;

Form sidewall spacer adjacent to this sacrificial gate electrode structure;

Carry out the first etch process to remove this sacrificial gate material between this distance piece, so thatThereby expose this second oxidation material layer, this first and second oxidation material layer in whole thisIn one etch process, integrally cover this upper surface and this side surface of this fin;

Carry out the second etch process to remove position this first and second oxidation between this distance pieceAt least a portion of material layer, thus substitute to define replacement gate hole and expose at thisThis upper surface of this fin in grid hole and this side surface; And

In this replacement gate hole around this upper surface exposing and this side surface of this finForm replacement gate structure.

19. methods as claimed in claim 18, is characterized in that, when the grid by this deviceSection that width obtains is observed, this sacrificial gate material be substantially have substantially averageThe planar structure of thickness.

20. methods as claimed in claim 18, is characterized in that, this first and second oxidationMaterial layer is to be made up of can flowing oxidation material.

21. methods as claimed in claim 18, is characterized in that, are forming this sidewall spacersAfter part, the method more comprises:

In the plurality of groove, above the side direction of this distance piece periphery and this second oxide layer, form absolutelyThe recessed layer of edge material, making the concave upper surface of the recessed layer of this insulating materials is to be in lower than this distance pieceUpper surface height and lower than the height of the upper surface of this sacrificial gate material;

At this upper surface of this concave upper surface of the recessed layer of this insulating materials, this distance piece and shouldOn this upper surface of sacrificial gate material, form insulating protective layer;

Remove this insulating protective layer position in the portion above this distance piece and above this sacrificial gate materialPoint; And

To the remainder of this insulating protective layer in the recessed layer of this insulating materials top position, carry outThis second etch process, wherein, this remainder of this insulating protective layer is in this second etching workCan the recessed layer of this insulating materials of protection in the implementation of skill.