CN105590842B - Reduce the structures and methods of source electrode and drain electrode resistance - Google Patents
Reduce the structures and methods of source electrode and drain electrode resistance Download PDFInfo
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- CN105590842B CN105590842B CN201410654361.8A CN201410654361A CN105590842B CN 105590842 B CN105590842 B CN 105590842B CN 201410654361 A CN201410654361 A CN 201410654361A CN 105590842 B CN105590842 B CN 105590842B
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Abstract
The invention discloses the methods for reducing source and drain electrode resistance.It can effectively reduce source electrode and drain electrode area resistance by this method.This method comprises: grid formed on a substrate, source electrode and drain electrode area and side wall；The hard exposure mask of the first side wall is formed on the outside of the side wall；Semiconductor layer is formed in the source electrode and drain electrode area；The hard exposure mask of the second side wall is formed on the outside of the hard exposure mask of the first side wall；The semiconductor layer is etched using the hard exposure mask of the second side wall as mask layer；The hard exposure mask of first side wall and the hard exposure mask of the second side wall are removed, to form the bulge-structure separated with the grid in the source electrode and drain electrode area.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to reduce the structures and methods of source and drain electrode resistance.
Background technique
With the rapid development of nanofabrication technique, the characteristic size of transistor has entered nanoscale.It is contracted by equal proportion
The performance that small method improves current main-stream silicon CMOS device is limited by more and more physics, technique.In order to make integrated electricity
Road technique can continue the revealed development speed of Moore's Law, it is necessary to the exploitation new material compatible with silicon technology, new construction and newly
Property.
Fig. 1 shows the cross-sectional view of the metal silicide formed on device in the prior art.As shown in Figure 1, in grid 106
With metal silicide film 112 is covered in source electrode and drain electrode area 110.These metal silicide films 110 utilize self-registered technology shape
At.Firstly, one layer of metal of conformal deposited on a surface of a wafer, by low temperature rta technique, the metal can be with polysilicon or silicon
Silicon in substrate reacts to form metal silicide, without with silicon nitride or oxidation pasc reaction, it is fast followed by high temperature
Fast annealing technique mutually reduces contact resistance by contact resistance by high resistant phase transition low-resistance in turn, then passes through selective etch and remove
The metal, due in the part except grid and source electrode and drain electrode contact zone there are barrier layers such as silicon oxide or silicon nitrides,
Metal, which fails to react with polysilicon or silicon substrate, generates metal silicide, therefore the metal outside contact zone is gone in this step
It removes, and the metal silicide formed on grid and source electrode and drain electrode contact zone is retained to form metal silicide layer 112.
In CMOS technology, this self-registered technology can reduce source electrode and drain electrode contact resistance.However, with transistor
The contact area of the reduction of characteristic size, source electrode and drain electrode constantly reduces, and source electrode and drain electrode contact resistance is caused to increase.
Therefore, it is necessary to a kind of new construction, new process, Lai Zengjia source electrode and drain electrode areas, to reduce source electrode and drain electrode electricity
Resistance.
Summary of the invention
The object of the present invention is to provide a kind of manufacturing method of semiconductor devices and structures, can be dropped by this method and structure
Low source electrode and drain electrode resistance.
According to an aspect of the present invention, a kind of manufacturing method of semiconductor devices is provided, comprising: formed on a substrate
Grid, source electrode and drain electrode area and side wall；The hard exposure mask of the first side wall is formed on the outside of the side wall；In the source electrode and drain electrode area
Form semiconductor layer；The hard exposure mask of the second side wall is formed on the outside of the hard exposure mask of the first side wall；By the hard exposure mask of the second side wall
The semiconductor layer is etched as mask layer；The hard exposure mask of first side wall and the hard exposure mask of the second side wall are removed, thus described
The bulge-structure separated with the grid is formed in source electrode and drain electrode area.
According to an aspect of the present invention, in preceding method, semiconductor layer is silicon layer.
According to an aspect of the present invention, in preceding method, semiconductor layer includes directly connecing with the source electrode and drain electrode area
The SiGe layer of touching, the silicon layer in the SiGe layer.
According to an aspect of the present invention, in preceding method, semiconductor layer includes directly connecing with the source electrode and drain electrode area
First silicon layer of touching, the SiGe layer on first silicon layer, the second silicon layer in the SiGe layer.
According to an aspect of the present invention, in preceding method, etch the semiconductor layer include using the SiGe layer as
Etching stop layer etches the silicon layer in the SiGe layer.
According to an aspect of the present invention, in preceding method, the thickness of SiGe layer is greater than 10 angstroms.
According to an aspect of the present invention, preceding method further includes removing the SiGe after etching the semiconductor layer
Layer.
According to an aspect of the present invention, in preceding method, formed the hard exposure mask of the first side wall include the following steps in extremely
A few step: the first side wall of conformal deposited hardmask material over the substrate；Pass through anisotropic etch process etching first
Side wall hardmask material, since the first side wall hardmask material thickness in the grid, source electrode and drain electrode area is less than institute
State the thickness of mask layer on side wall two sides, thus etch away the grid, the hard exposure mask of the first side wall in source electrode and drain electrode area
After material layer, the hard exposure mask of the first side wall is formed on the side wall two sides.
According to an aspect of the present invention, in preceding method, formed the hard exposure mask of the second side wall include the following steps in extremely
A few step: the second side wall of conformal deposited hardmask material over the substrate；Pass through anisotropic etch process etching second
Side wall hardmask material, since the second side wall hardmask material thickness in the grid, source electrode and drain electrode area is less than institute
State the thickness of mask layer on the hard exposure mask two sides of the first side wall, thus etch away the grid, second in source electrode and drain electrode area
After side wall hardmask material, the hard exposure mask of the second side wall is formed on the hard exposure mask two sides of first side wall.
According to an aspect of the present invention, in preceding method, the hard exposure mask of the first side wall and the hard exposure mask of the second side wall
Width is greater than 30 angstroms.
According to an aspect of the present invention, in preceding method, be repeated several times it is described formed second side wall mask layer and
The step of etching semiconductor layer, to form multi-stage source electrode and drain electrode structure in the source electrode and drain electrode area.
According to an aspect of the present invention, in preceding method, the hard exposure mask of the first side wall and the hard exposure mask of the second side wall by
Any one of following material formation: silica, silicon nitride, SiON, amorphous carbon or their any combination.
According to an aspect of the present invention, in preceding method, the semiconductor layer is formed by epitaxial growth method.
According to another aspect of the present invention, a kind of semiconductor devices is provided, comprising: grid, source electrode and drain electrode area and side
Wall, wherein having the bulge-structure separated with the grid in the source electrode and drain electrode area.
Compared with prior art, the contact area of the source electrode and drain electrode according to the present invention for being formed by semiconductor devices is aobvious
It writes and increases, source electrode and drain electrode contact resistance is substantially reduced.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, it is exaggerated the thickness of layer and region.It is identical or
Corresponding component will be indicated with same or similar label.
Fig. 1 shows the cross-sectional view of the metal silicide formed on device in the prior art.
Fig. 2A to Fig. 2 F shows first embodiment according to the present invention and forms the process of bulge-structure in source electrode and drain electrode area
Diagrammatic cross-section.
Fig. 3 A to Fig. 3 F shows second embodiment according to the present invention and forms the process of bulge-structure in source electrode and drain electrode area
Diagrammatic cross-section.
Fig. 4 A to Fig. 4 F shows third embodiment according to the present invention by the thickness of control etching silicon epitaxial layers in source electrode
With the diagrammatic cross-section for the process for forming bulge-structure in drain region.
Fig. 5 shows the flow chart according to an embodiment of the invention that bulge-structure is formed in source electrode and drain electrode area.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
In order to increase source electrode and drain electrode area contact area to reduce source electrode and drain electrode contact resistance, the present inventor envisions one
Kind is by forming bulge-structure in source electrode and drain electrode area, to increase the method for source electrode and drain electrode area contact area.
Fig. 2A to Fig. 2 F shows first embodiment according to the present invention and forms the process of bulge-structure in source electrode and drain electrode area
Diagrammatic cross-section.
As shown in Figure 2 A, device 200 includes the grid 202 formed on substrate 201, source electrode and drain electrode area 203 and side wall
204.Device 200 can be formed by multiple steps, including for example, shallow-trench isolation step, polysiiicon deposition steps, gate patterning
Step, injection step, annealing steps etc..After carrying out shallow-trench isolation step to form multiple active areas, shape on substrate
At gate dielectric 205 and deposit polycrystalline silicon layer, it is then patterned to form grid 202.After forming side wall 204,
Ion implanting is carried out, to form source electrode and drain electrode area.In order to protrude emphasis of the invention, not to the forming process of device 200 into
Row detailed description.
Next, as shown in Figure 2 B, forming the hard exposure mask 206 of the first side wall on the outside of side wall 204.In one embodiment,
The material that can be used to form the hard exposure mask 206 of the first side wall includes silica, silicon nitride, SiON, amorphous carbon or their any group
It closes.In one embodiment, the width of the hard exposure mask 206 of the first side wall is greater than 30 angstroms.Available work similar with side wall 204 is formed
Skill forms the hard exposure mask 206 of the first side wall.In one embodiment, first on chip one layer of conformal deposited be used to form the first side
The material of the hard exposure mask 206 of wall, then etches the material layer by anisotropic etch process.Due to the first hard exposure mask on horizontal plane
The thickness of layer 206 is less than the thickness of hard mask layer 206 on 204 two sides of side wall, therefore the hard mask layer 206 on removal horizontal plane
Afterwards, the hard exposure mask 206 of the first side wall of 204 two sides of side wall is left.In other embodiments, the hard exposure mask 206 of the first side wall can also lead to
It crosses other materials or other techniques is formed.
Next, as shown in Figure 2 C, forming certain thickness SiGe layer 207 in source electrode and drain electrode area 203, and in SiGe layer
Si layer 208 is formed on 207.In one embodiment, the thickness of SiGe layer 207 is greater than 10 angstroms.In one embodiment, can pass through
Growth technology grows SiGe layer 207 and Si layer 208.In one embodiment, the thickness of Si layer 208 can be 30 to 100
Between angstrom.
For example, the process gas for being used to form epitaxial growth SiGe layer 207 may include SiH4；GeH4；HCl；BH6；And
H2, wherein H2Gas flow rate can be 0.1slm to 50slm, the flow velocity of other gases can be 1sccm to 1000sccm, instead
Answer temperature at 500-800 DEG C, pressure is held in the palm in 5-50, however the present invention is not limited to these listed process gas and technique to join
Number.These technological parameters can be changed, adjust the Ge content in SiGe alloy.
Next, as shown in Figure 2 D, forming the hard exposure mask 209 of the second side wall on the outside of the hard exposure mask 206 of the first side wall.At one
In embodiment, can be used to form the hard exposure mask 209 of the second side wall material can be silica, silicon nitride, SiON, amorphous carbon or it
Any combination.The forming process of the hard exposure mask 209 of second side wall and the forming process of the hard exposure mask 206 of the first side wall are detailed, because
This, is no longer described in further detail.
Next, it is used as etching stop layer as mask layer, and by SiGe layer 207 using the hard exposure mask 209 of the second side wall,
Etching Si layer 208 is formed as shown in Figure 2 E so that not being removed by the Si layer 208 that the hard exposure mask 209 of the second side wall covers
Structure.
The hard exposure mask 206,209 of the first and second side walls is finally removed, forms protrusion knot among source electrode and drain electrode area 203
Structure, as shown in Figure 2 F, to increase the effective area in source electrode and drain electrode area 203.Various dry or wet etch sides can be passed through
Method removes the hard exposure mask 206,209 of the first and second side walls.For example, in one embodiment of the invention, side wall 204 is silica
It is identical as side wall 204 as the material of the twin stack configuration of silicon nitride, the hard exposure mask 206,209 of the first and second side walls, it can pass through
Four step wet-etching technologies remove the hard exposure mask 206,209 of the first and second side walls: etching the nitrogen of the hard exposure mask 209 of the second side wall first
SiClx layer and using silicon oxide layer as etching stop layer, etches the silicon oxide layer of the hard exposure mask 209 of the second side wall and then with the first side
The silicon nitride layer of the hard exposure mask 206 of wall is etching stop layer, then etches the silicon nitride layer of the hard exposure mask 206 of the first side wall and with the first side
The silicon oxide layer of the hard exposure mask 206 of wall is etching stop layer, etches the silicon oxide layer of the hard exposure mask 206 of the first side wall and then with side wall
204 silicon nitride layer is etching stop layer, to completely remove the hard exposure mask 206,209 of the first and second side walls.However, of the invention
The hard exposure mask 206,209 of the first and second side wall of removal method it is without being limited thereto.
Due to there is SiGe layer 207 as etching stop layer, whole flow process is not exposed to substrate Si, so to the property of device
It can influence smaller.In the present invention, SiGe layer 207 is used as etching stop layer, thus, the source electrode with bulge-structure can formed
The exposed SiGe layer 207 with removal after drain region 203, however exposed SiGe layer 207 can also be retained.
Fig. 3 A to Fig. 3 F shows second embodiment according to the present invention and forms the process of bulge-structure in source electrode and drain electrode area
Diagrammatic cross-section.
It is similar to process shown in Fig. 2A to Fig. 2 F, device 300 include the grid 302 formed on substrate 301, source electrode and
Drain region 303 and side wall 304.The difference is that as shown in Figure 3 C, the semiconductor layer formed in source electrode and drain electrode area 303
It is folded to include: and the first silicon layer 311 directly contacted in source electrode and drain electrode area 303, the SiGe layer directly contacted with the first silicon layer 311
312 and the second silicon layer 313 for directly being contacted with SiGe layer 312.
Since the lattice constant of SiGe alloy is different from the lattice constant of Si crystal, SiGe alloy would generally make its week
Stress is generated in the silicon crystal enclosed.Therefore, the first Si floor 311 being formed between SiGe layer 312 and source electrode and drain electrode area 303 can make
SiGe layer 312 reduces the stress that SiGe layer 312 generates device far from source electrode and drain electrode area.SiGe layer 312 is as etching
The etching stop layer of 2nd Si layer 313, thickness are greater than 10 angstroms.In one embodiment, it can be grown by growth technology
First Si layer 311, SiGe layer 312 and the 2nd Si layer 313.In one embodiment, the first Si layer 311 and the 2nd Si layer 313
Thickness can be between 30 to 100 angstroms.
The process of Fig. 3 D to 3F is similar to process shown in Fig. 2 D to 2F, in order to simplify description of the invention, and no longer into
One step detailed description.
Fig. 4 A to Fig. 4 E shows third embodiment according to the present invention by the thickness of control etching silicon epitaxial layers in source electrode
With the diagrammatic cross-section for the process for forming bulge-structure in drain region.
Similar to Fig. 2A to 2B, device 400 includes the grid 402 formed on substrate 401,403 and of source electrode and drain electrode area
Side wall 404 forms the hard exposure mask 406 of the first side wall on the outside of side wall 404.
Next, as shown in Figure 4 C, forming certain thickness Si floor 411 in source electrode and drain electrode area 403, implement at one
In example, Si layer 411 can be grown by growth technology.In one embodiment, the thickness of Si layer 411 is at 30 angstroms to 100 angstroms
Between.
Next, as shown in Figure 4 D, forming the hard exposure mask 409 of the second side wall on the outside of the hard exposure mask 406 of the first side wall.
Next, etching Si layer 411 using the hard exposure mask 409 of the second side wall as mask layer.Under specific process conditions,
Etch rate to Si be it is constant, therefore, in the case where not formed etching stop layer, can be controlled by control etch period
It makes the depth of etching and etches or etch deficiency to avoid transition.So that the Si layer not covered by the hard exposure mask 409 of the second side wall
411 are removed, and form structure as shown in Figure 4 E.
The hard exposure mask 406,409 of the first and second side walls is finally removed, the source electrode and drain electrode area with bulge-structure is formed
403, as illustrated in figure 4f, to increase the effective area in source electrode and drain electrode area 403.The hard exposure mask 406 of first and second side walls,
409 minimizing technology and method shown in Fig. 2 F are detailed, therefore are no longer described in further detail.
In other embodiments of the invention, multiple hard mask structures of second side wall can be formed, and are directed to each second
The hard mask structure of side wall, is once etched, to form the source/drain regions structure with multi-stage bulge-structure.
Fig. 5 shows the flow chart according to an embodiment of the invention that bulge-structure is formed in source electrode and drain electrode area.
Firstly, in step 501, grid, source electrode and drain electrode area and side wall formed on a substrate.In step 502, in side wall
Outside forms the hard exposure mask of the first side wall.First side wall mask layer is formed using its autoregistration characteristic.In step 503, source electrode and leakage
Semiconductor layer is formed on polar region.According to the present invention first to 3rd embodiment, the semiconductor layer can be single layer structure or
Multilayer laminate constructions.For example, can be by epitaxial semiconductor layer, which can be 1) monolayer silicon；2) with source electrode and
The SiGe that drain region directly contacts and the silicon layer formed thereon；3) the first silicon layer for directly being contacted with source electrode and drain electrode area,
The SiGe layer formed on one silicon layer, the second silicon layer formed on the sige layer.SiGe is as etching stop layer and far from channel, drop
The stress that low SiGe layer generates channel forms raised source electrode and drain electrode area (raised source/drain, RSD).
In step 504, the hard exposure mask of the second side wall is formed on the outside of the hard exposure mask of the first side wall.
In step 505, using the hard exposure mask of the second side wall as mask layer etching semiconductor layer.In step 506, removal first
With the second side wall hard mask layer.
In the case where semiconductor layer is monolayer silicon, the depth of etching can be controlled to avoid mistake by control etch period
It crosses etching or etching is insufficient.In the case where semiconductor layer is the multilayered structure comprising SiGe layer, using SiGe layer as etch-stop
Only layer etches silicon layer.After completing etching, exposed SiGe layer is optionally removed.It is formed in source electrode and drain electrode area as a result,
Bulge-structure, the bulge-structure are separated with gate regions, so that being separated by the semiconductor multilayer being epitaxially-formed with channel.
It can stress multiple step 504 and 505 more, form multiple hard mask structures of second side wall, and be directed to each second side
The hard mask structure of wall, is once etched, to form the source/drain regions structure with multi-stage bulge-structure.
Finally, forming metal silicide in source electrode and drain electrode area and gate regions.Due to having in source electrode and drain electrode area
There is bulge-structure, therefore increase the real area in source electrode and drain electrode area, to reduce the contact resistance in source electrode and drain electrode area.
The foregoing description of the embodiment of the present invention is had been presented for for the purpose of illustration and description.It is not intended to be exhaustive to or incites somebody to action
The present invention is limited to disclosed precise forms.This specification and appended claims include such as left and right, top, bottom ... it
It is upper, exist ... under, top, lower part, the terms such as first, second, these are only used for the purpose of description and should not be construed as limiting.
For example, indicating that the term of opposite upright position refers to that the device-side (or active surface) of substrate or integrated circuit is the substrate
"top" face the case where；Substrate can be practically at any direction, so that the "top" side of substrate can in the referential of standard land
It lower than "bottom" side and still falls in the meaning of term "top".As used in this term " ... on " (it is included in right
In it is required that) do not indicate that the first layer on the second layer directly directly contacts on the second layer and with the second layer, unless specifically
It is bright such；Can there are third layer or other structures between the second layer on first layer and first layer.It can be in multiple positions and side
The embodiment of manufacture, use or transport device as described herein or product upwards.Those skilled in the relevant art can be more than
Teaching to understand many modification and variation be possible.Those skilled in the art will recognize that each component shown in the drawings
Various equivalent combinations and replacement.Therefore the scope of the present invention is limited by the detail specifications but by appended claims
It limits.
The foregoing describe several embodiments of the invention.However, the present invention can be embodied as other concrete forms without carrying on the back
From its spirit or essential characteristics.Described embodiment should all be to be considered merely as illustrative and not restrictive in all respects.
Therefore, the scope of the present invention is by the appended claims rather than foregoing description limits.Fall into the equivalent scheme of claims
All changes in meaning and scope are covered by the range of claims.
Claims (14)
1. a kind of manufacturing method of semiconductor devices, comprising:
Grid, source electrode and drain electrode area and side wall formed on a substrate；
The hard exposure mask of the first side wall is formed on the outside of the side wall；
Semiconductor layer is formed in the source electrode and drain electrode area after forming the hard exposure mask of the first side wall；
The hard exposure mask of the second side wall is formed on the outside of the hard exposure mask of the first side wall；
The semiconductor layer is etched using the hard exposure mask of the second side wall as mask layer；
Remove the hard exposure mask of first side wall and the hard exposure mask of the second side wall, thus in the source electrode and drain electrode area formed with it is described
The bulge-structure of grid separation.
2. the method as described in claim 1, which is characterized in that the semiconductor layer is silicon layer.
3. the method as described in claim 1, which is characterized in that the semiconductor layer includes direct with the source electrode and drain electrode area
The SiGe layer of contact, the silicon layer in the SiGe layer.
4. the method as described in claim 1, which is characterized in that the semiconductor layer includes direct with the source electrode and drain electrode area
First silicon layer of contact, the SiGe layer on first silicon layer, the second silicon layer in the SiGe layer.
5. the method as claimed in claim 3 or 4, which is characterized in that etching the semiconductor layer includes with SiGe layer work
For etching stop layer, the silicon layer in the SiGe layer is etched.
6. the method as claimed in claim 3 or 4, which is characterized in that the thickness of the SiGe layer is greater than 10 angstroms.
7. the method as claimed in claim 3 or 4, which is characterized in that further include after etching the semiconductor layer, described in removal
SiGe layer.
8. the method as described in claim 1, which is characterized in that formed the hard exposure mask of the first side wall include the following steps at least
One step:
The first side wall of conformal deposited hardmask material over the substrate；
The first side wall hardmask material is etched by anisotropic etch process, due in the grid, source electrode and drain electrode area
The first side wall hardmask material thickness be less than the thickness of mask layer on the side wall two sides, therefore etching away the grid
After the first side wall hardmask material on pole, source electrode and drain electrode area, the hard exposure mask of the first side wall is formed on the side wall two sides.
9. the method as described in claim 1, which is characterized in that formed the hard exposure mask of the second side wall include the following steps at least
One step:
The second side wall of conformal deposited hardmask material over the substrate；
The second side wall hardmask material is etched by anisotropic etch process, due in the grid, source electrode and drain electrode area
The second side wall hardmask material thickness be less than the thickness of mask layer on the hard exposure mask two sides of first side wall, therefore etching
After falling the grid, the second side wall hardmask material in source electrode and drain electrode area, on the hard exposure mask two sides of first side wall
Form the hard exposure mask of the second side wall.
10. the method as described in claim 1, which is characterized in that the hard exposure mask of the first side wall and second side wall are covered firmly
The width of film is greater than 30 angstroms.
11. method according to claim 8, which is characterized in that be repeated several times it is described formed second side wall mask layer and
The step of etching semiconductor layer, to form multi-stage source electrode and drain electrode structure in the source electrode and drain electrode area.
12. the method as described in claim 1, which is characterized in that the hard exposure mask of the first side wall and second side wall are covered firmly
Film is formed by any one of following material: silica, silicon nitride, SiON, amorphous carbon or their any combination.
13. the method as described in claim 1, which is characterized in that form the semiconductor layer by epitaxial growth method.
14. a kind of semiconductor devices, including the structure by method manufacture described in any one of claim 1 to 13.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034709A (en) * | 2009-09-25 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Method for amplifying process window of PMOS (P-channel metal oxide semiconductor) core device |
| CN102842614A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN103390644A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8273631B2 (en) * | 2009-12-14 | 2012-09-25 | United Microelectronics Corp. | Method of fabricating n-channel metal-oxide semiconductor transistor |
| US7989298B1 (en) * | 2010-01-25 | 2011-08-02 | International Business Machines Corporation | Transistor having V-shaped embedded stressor |
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- 2014-11-17 CN CN201410654361.8A patent/CN105590842B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034709A (en) * | 2009-09-25 | 2011-04-27 | 中芯国际集成电路制造(上海)有限公司 | Method for amplifying process window of PMOS (P-channel metal oxide semiconductor) core device |
| CN102842614A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN102842595A (en) * | 2011-06-20 | 2012-12-26 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN103390644A (en) * | 2012-05-08 | 2013-11-13 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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