CN105580083A

CN105580083A - Resistance-based memory cells with multiple source lines

Info

Publication number: CN105580083A
Application number: CN201480053554.6A
Authority: CN
Inventors: X·董
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2013-09-30
Filing date: 2014-09-18
Publication date: 2016-05-11
Anticipated expiration: 2034-09-18
Also published as: EP3022738A1; US9196339B2; EP3022738B1; WO2015047844A1; CN105580083B; US20150092479A1

Abstract

In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.

Description

Based on the memory cell with many source lines of resistance

The cross reference of related application

This application claims the U.S. Non-provisional Patent application No.14/041 submitted on September 30th, 2013 owned together, the right of priority of 868, the content of this non-provisional is all clearly included in this by quoting.

Field

The disclosure relates generally to the memory devices based on resistance.

Description of Related Art

Storer (such as magnetic random access memory (MRAM)) based on resistance can be used as nonvolatile RAM.MRAM equipment can use magnetic (reluctance type) memory element being called as MTJ (MTJ) element to store data.MTJ element is formed from two ferromagnetic layers separated by insulation course.A layer in these two layers can be magnetized to fixed polarity, and another layer by applying magnetic field via this layer of write alignment or making its magnetic polarization change by applying reset current to MTJ in spin-transfer torque MRAM (STT-MRAM) configuration in conventional MRAM configuration.Each MTJ element and the Circuits System (such as, access transistor) be associated thereof can form the mram cell of a storage information.

Data can read from mram cell based on the resistance of mram cell.Specific mram cell is selected by the biased access transistor be associated, and this access transistor enables electric current cross the MTJ of this unit from source linear flow.The resistance of mram cell depends on the orientation of the field in these two magnetospheres.By measure through MTJ reading electric current (such as, by reading electric current and reference current are compared), MTJ can have identical polar at these two magnetospheres and this unit is confirmed as under presenting more low-resistance situation being in parastate (such as, logical one) or be confirmed as being in antiparallel state (such as, logical zero) when these two magnetospheres have opposite polarity and MTJ presents high electrical resistance.

General introduction

Disclose the system and method by using the coupled configuration encoded radio based on the memory cell of resistance to carry out coded data.Memory cell based on resistance can have multiple access transistor.The coupled configuration encoded data value of the plurality of access transistor bar source line at the most.Such as, when the first access transistor in the plurality of access transistor is coupled to the first source line and the second access transistor in the plurality of access transistor is coupled to the second source line, this coupled configuration corresponds to the first data value.When the first access transistor is coupled to the second source line and the second access transistor is coupled to the first source line, this coupled configuration corresponds to the second data value.

In another specific embodiment, a kind of method for reading data comprises: at the memory cell place based on resistance relative at least one in bit line bias first source line or the second source line.The memory cell place that the method is also included in based on resistance activates based on the first access transistor of the memory cell of resistance.The first source line, the second source line and bit line should be coupled to based on the memory cell of resistance.Whether the method memory cell place be included in further based on resistance enables reading electric current flow through this memory cell based on resistance based on the first access transistor is carried out detect data value.

In another specific embodiment, a kind of equipment comprises: at the memory cell place based on resistance relative to the device of at least one in bit line bias first source line or the second source line.This equipment also comprises the device of the first access transistor for activating this memory cell based on resistance at the memory cell place based on resistance.The first source line, the second source line and bit line should be coupled to based on the memory cell of resistance.This equipment comprise further at the memory cell place based on resistance based on the first access transistor whether enable reading electric current flow through device that this memory cell based on resistance carrys out detect data value.

In another specific embodiment, stored energy performs with a computer readable storage devices for the instruction of executable operations by processor, and these operations are included in memory cell place based on resistance relative at least one in bit line bias first source line or the second source line.These operation memory cell places be also included in based on resistance activate first access transistor of this memory cell based on resistance, wherein should be coupled to the first source line, the second source line and bit line based on the memory cell of resistance.Whether these operation memory cell places be included in further based on resistance enable reading electric current flow through this memory cell based on resistance based on the first access transistor is carried out detect data value.

The specific advantages provided by least one embodiment in the disclosed embodiments is to provide the ability of the memory cell based on resistance, should can be used as random access memory (RAM) unit of the state based on resistive element based on the memory cell of resistance and also can be used as ROM (read-only memory) (ROM) unit.

Other aspects of the present disclosure, advantage and feature can become clear after having read whole application, and whole application comprises following chapters and sections: accompanying drawing summary, detailed description and claims.

Accompanying drawing is sketched

Fig. 1 is the diagram of two specific illustrative embodiments of the memory cell based on resistance being configured to encoded data value;

Fig. 2 is the diagram of the specific embodiment of the memory cell based on resistance being configured to encoded data value;

Fig. 3 is the diagram of the memory cell array based on resistance of the memory cell based on resistance that can comprise Fig. 1 or 2;

Fig. 4 be explain orally can with the table of the state of the wordline of the memory cell coupling based on resistance of Fig. 1 or 2, bit line and source line;

Fig. 5 is the process flow diagram explained orally for reading the specific embodiment of the method for data value from the memory cell based on resistance;

Fig. 6 is the process flow diagram explained orally for reading the second specific embodiment of the method for data value from the memory cell based on resistance;

Fig. 7 is the process flow diagram explained orally for reading the 3rd specific embodiment of the method for data value from the memory cell based on resistance;

Fig. 8 is the process flow diagram of the specific embodiment explained orally for the method to the memory cell write data value based on resistance;

Fig. 9 is the diagram of the communication facilities of the memory cell comprised based on resistance; And

Figure 10 is the process flow diagram of the specific illustrative embodiment of the manufacture process of electronic equipment for the manufacture of the memory cell comprised based on resistance.

Describe in detail

Fig. 1 has explained orally the specific embodiment 100 of the memory cell 101 based on resistance and the memory component 103 based on resistance.Memory cell 101 based on resistance is coupled to wordline 116 and wordline 118.Wordline 116 is coupled to the grid of the first access transistor 110, and wordline 118 is coupled to the grid of the second access transistor 112.Source line 104 is coupled to the first terminal of the second access transistor 112, and source line 106 is coupled to the first terminal of the first access transistor 110.Second terminal of the first access transistor 110 is coupled to the memory component 114 (such as, MTJ (MTJ)) based on resistance at node 102 place.Second terminal of the second access transistor 112 is also coupled to MTJ element 114 at node 102 place.MTJ element 114 is coupled to bit line 108 and flows between node 102 and bit line 108 via MTJ element 114 to enable electric current.Memory cell 101 based on resistance is configured to store data corresponding to random access memory (RAM) data value based on the state of MTJ element 114.

When the memory cell 101 based on resistance is used as the RAM memory cell based on resistance, source line 104 can drive or arrange by identical voltage and/or electric current (such as by source line 104 and source line 106 being coupled) with source line 106.The amount flowing through the reading electric current of MTJ element 114 can compare to determine the RAM data value corresponding with the state of MTJ element with reference current.MTJ element 114 can have the relatively high resistance of the RAM data value corresponded to can be relevant to logical zero state or correspond to the relative low-resistance of the 2nd RAM data value can be correlated with logical one state.The electric current flowing through MTJ element being derived from the reading voltage applied across MTJ cell via one or more access transistor be activated is called as " reading electric current ".Represent that the reading electric current of the logical one state of MTJ element can be identified as in the first current value range (such as, due to technique, voltage and/or temperature variation) and to represent that the reading electric current of the logical zero state of MTJ element can be identified as in the second current value range.

The state changing MTJ element 114 corresponds to the memory cell 101 of data value write based on resistance.In order to change the state of MTJ element 114, wordline 116 and wordline 118 are respectively applied for the grid of biased first access transistor 110 and the grid of the second access transistor 112.The first access transistor 110 be activated and the second access transistor 112 be activated allow electric current to flow through MTJ element 114, and this can cause the state of MTJ element 114 to change." reset current " refers to the electric current of the amplitude with the state being enough to change MTJ element and is greater than reading electric current (reading the state that electric current does not upset MTJ element).

Except the RAM value of the state based on MTJ element 114, the memory cell 101 based on resistance also can store read-only data based on source line 104 and source line 106 to the coupled configuration of the memory cell 101 based on resistance.In one embodiment, when the memory cell 101 based on resistance is used as ROM cell (that is, being just read in ROM operator scheme), source line 104 can be configured to read voltage and source line 106 and bit line 108 can be configured to ground connection.Source line 106 and bit line 108 are arranged to ground connection (or other common voltages) can comprise source line 106 and bit line 108 are coupled.

In one embodiment, when reading ROM data value from the memory cell 101 based on resistance, wordline 116 be biased to inactive access transistor 110 and wordline 118 be biased to activate access transistor 112 flow through access transistor 112 to enable electric current.If electric current (such as, having the electric current of the amplitude exceeding threshold value) detected at bit line 108 place, then the memory cell 101 based on resistance can be confirmed as storage first logical value (such as logical zero).If electric current (such as, not detecting that the amplitude of electric current or electric current is lower than threshold value) do not detected at bit line 108 place, then the memory cell 101 based on resistance can be confirmed as storage second logical value (such as logical one).Alternatively, detect electric current except detecting except electric current at bit line 108 place or being substituted in bit line 108 place, electric current can also be detected at source line 106 (or source line 104) place.

Source line 104 and source line 106 are coupled to access transistor with order different compared with the memory cell 101 based on resistance by the coupled configuration (as shown in memory cell 103 based on resistance) relevant with different ROM value.Memory cell 103 based on resistance is coupled to wordline 126 and wordline 128.Wordline 126 is coupled to the grid of the first access transistor 130, and wordline 128 is coupled to the grid of the second access transistor 136.Source line 120 is coupled to the first terminal of the first access transistor 130, and source line 122 is coupled to the first terminal of the second access transistor 136.Second terminal of the first access transistor 130 is coupled to memory component (such as, the MTJ) element 134 based on resistance at node 132 place.Second terminal of the second access transistor 136 is also coupled to node 132.MTJ element 134 is coupled to bit line 124 and flows between node 132 and bit line 124 via MTJ element 134 to enable electric current.Memory cell 103 based on resistance is configured to store data based on the state of MTJ element 134.

Operation based on the memory cell 103 of resistance can in response to the mode control signal such as coming self processor or controller, and can be used as RAM memory cell (in RAM operator scheme) based on resistance and the ROM memory cell (in ROM operator scheme) that can be used as based on resistance by the mode similar to about the mode described by the memory cell 101 based on resistance based on the memory cell 103 of resistance.But, because the first access transistor 130 is coupled to the first source line 120 and the second access transistor 136 is coupled to the second source line 122, so the value read from the memory cell 103 based on resistance being in ROM operator scheme (such as, logical one) be different from the value (such as, logical zero) read from the memory cell 101 based on resistance being in ROM operator scheme.

Source line is encoded to this ROM data value based on the memory cell of resistance by the current path of MTJ element to the coupled configuration based on the memory cell of resistance by enabling or disabling in ROM operator scheme.Therefore, it is be read as to have the first binary value (such as that this coupled configuration is determined based on the memory cell of resistance in ROM pattern, logical zero value about the memory cell 101 based on resistance) or the second binary value (such as, about the logical one value of the memory cell 103 based on resistance).

The ROM data value of the coupled configuration of the coupled configuration based on the memory cell 101 of resistance and the memory cell 103 based on resistance can be arranged for when using in a device by layout in the Circuits System for the memory cell 101 and 103 based on resistance.As a result, once be embodied in silicon integrated circuit or other semiconductor devices, be exactly non-programmable with the ROM data value be associated based on each in the memory cell 101 and 103 of resistance.ROM data value can be set up and/or change and/or be indicated in Computer Aided Design (CAD) file represented based on the memory cell 101 and 103 of resistance during the design phase.

Although the memory cell 101 based on resistance and the memory cell 103 based on resistance describe with two access transistors being coupled to two source lines, but in other embodiments, based on the memory cell of resistance can comprise be coupled to more than two source lines more than two access transistors to store a more than ROM value.Such as, the 3rd access transistor can be coupled to the 3rd source line.

Each memory cell based on resistance can be used to based on each in the memory cell 101 and 103 of resistance and store two values, thus compared with the single-bit memory unit based on resistance, available memory density be doubled effectively.Part value can be stored as ROM value, and part value can be stored as RAM value.The ROM value be stored in the memory cell 101 based on resistance and/or the memory cell 103 based on resistance can be encoded, as described in more detail about Fig. 9 to the data of mathematical table (such as table of trigonometric function or Fast Fourier Transform (FFT) (FFT) coefficient table).Because each memory cell based on resistance can keep RAM data value and ROM data value (such as simultaneously, the RAM value indicated by the state of MTJ element and the ROM value indicated by coupled configuration), thus increase the data available density of the memory array formed by the memory cell (such as based on the memory cell 101 and 103 of resistance) based on resistance compared with the single-bit memory unit based on resistance time.The memory array based on resistance formed by the memory cell (such as based on the memory cell 101 and 103 of resistance) based on resistance can form ROM value array and RAM value array, and can reduce the use of circuit board space and/or integrated circuit lead area, this can be useful in SoC (" SOC (system on a chip) ") design with other application that memory array column space is of great rarity wherein.

Fig. 2 explained orally comprise first based on the memory cell 240, second of resistance based on the memory cell 242 and the 3rd of resistance based on the part of the memory devices 200 based on resistance of the memory cell 244 of resistance.First is coupled to source line 204,206 based on the memory cell 240 of resistance, and second is coupled to source line 216,218 based on the memory cell 242 of resistance, and the 3rd is coupled to source line 222,224 based on the memory cell 246 of resistance.The first wordline 201 and the second wordline 202 is coupled to based on each in the memory cell 240-244 of resistance.First based on resistance memory cell 240 with the 3rd based on the memory cell 244 of resistance have with the coupled configuration identical based on the memory cell 101 of resistance of Fig. 1 (namely, " top " access transistor is coupled to the source line on " the right ", and " bottom " access transistor is coupled to the source line on " left side ").(namely second have the coupled configuration identical with the memory cell 103 based on resistance based on the memory cell 242 of resistance, " top " access transistor is coupled to the source line on " left side ", and " bottom " access transistor is coupled to the source line on " the right ").

In the first memory cell 240 based on resistance, source line 204 is coupled to the first terminal of the second access transistor 212, and source line 206 is coupled to the first terminal of the first access transistor 208.Second terminal of the second access transistor 212, based on the first terminal of storer (such as, the MTJ) element 210 of resistance and the second coupling terminals of the first access transistor 208 to node 248.Based on the second coupling terminals to the first bit line 214 of the memory component 210 of resistance.

In the second memory cell 242 based on resistance, source line 216 is coupled to the first terminal of the first access transistor 230, and source line 218 is coupled to the first terminal of the second access transistor 234.Second terminal of the first access transistor 230, based on the first terminal of storer (such as, the MTJ) element 232 of resistance and the second coupling terminals of the second access transistor 234 to node 250.Based on the second coupling terminals to the second bit line 220 of the memory component 232 of resistance.

In the 3rd memory cell 244 based on resistance, source line 222 is coupled to the first terminal of the second access transistor 241, and source line 224 is coupled to the first terminal of the first access transistor 236.Second terminal of the first access transistor 236, based on the first terminal of storer (such as, the MTJ) element 238 of resistance and the second coupling terminals of the second access transistor 241 to node 252.Based on the second coupling terminals of the memory component 238 of resistance to the 3rd bit line 226.

In RAM operator scheme (such as, in response to mode control signal first value), can by with for Fig. 1 based on resistance memory cell 101 and 103 described by RAM class of operation like mode and as described in more detail about Fig. 3 based on each state based on the memory component 210,232 and 238 of resistance access based on each in the memory cell 240,242 and 244 of resistance for digital independent and data write operation.

In ROM operator scheme (such as, the second value in response to mode control signal), memory cell 240 based on resistance can be accessed to determine and memory cell 240 to the source line 204 based on resistance, the data value that the coupled configuration of 206 is associated, memory cell 242 based on resistance can be accessed to determine with the memory cell based on resistance to source line 216, the data value that the coupled configuration of 218 is associated, and can be accessed to determine and memory cell 244 to the source line 222 based on resistance based on the memory cell 244 of resistance, the data value that the coupled configuration of 224 is associated.Such as, access transistor 208 can be coupled to by determining source line to the particular source line in 204,206 or be coupled to access transistor 212 and read first based on the ROM data value (such as, in mode like the ROM class of operation of the memory cell 100 based on resistance with Fig. 1 and as described in more detail about Fig. 3) of the memory cell 240 of resistance.Second can read by determining that source line is coupled to access transistor 230 to the particular source line in 216,218 or is coupled to access transistor 234 based on the ROM data value of the memory cell 242 of resistance.3rd can read by determining that source line is coupled to access transistor 236 to the particular source line in 222,224 or is coupled to access transistor 241 based on the ROM data value of the memory cell 244 of resistance.

Once for the Circuits System of the memory cell 240-244 based on resistance by layout and equipment 200 is manufactured, ROM data value (such as, the coupled configuration of each memory cell 240-244 based on resistance) just can be fixed.As a result, once in use be implemented as silicon integrated circuit or be implemented in the semiconductor device, the ROM data value be associated with based on each in the memory cell 240-244 of resistance just can keep fixing.ROM data value can be set up and/or change and/or the part of Computer Aided Design (CAD) file as indication equipment 200 during the design phase.

Fig. 3 has explained orally the system comprising memory array 300, and memory array 300 comprises multiple memory cell based on resistance (memory cell based on resistance of such as Fig. 1 and Fig. 2).Each memory cell based on resistance is positioned at the intersection of a pair wordline and a pair source line, and the example wherein based on the individual memory cell of resistance is illustrated as the memory cell 320 based on resistance, the memory cell 322 based on resistance and the memory cell 324 based on resistance in memory array 300.Such as, may correspond in the row 0 of memory array 300 and row 0 based on the memory cell 320 of resistance and be coupled to wordline 316 (wordline 316 may correspond to the wordline 116 in Fig. 1) and wordline 318 (wordline 318 may correspond to the wordline 118 in Fig. 1).The memory cell 320 based on resistance corresponding with the row 0 of memory array 300 and row 0 is also coupled to source line 310 (source line 310 may correspond to the source line 104 in Fig. 1) and source line 312 (source line 312 may correspond to the source line 106 in Fig. 1).The memory cell 320 based on resistance corresponding with the row 0 of memory array 300 and row 0 is coupled to bit line 314 further.

Row decoder 302 is configured to (such as, all or part of address) at least partially of receiver address and selects to correspond to the row (such as, corresponding to the row 0 of wordline 316 and wordline 318) of this address.Local data path 306 comprises column decoder, this column decoder be configured to receive all or part of address at least partially and select to correspond to the row (such as, corresponding to the row 0 of source line 310, source line 312 and bit line 314) of this all or part of address.Local data path 306 also can comprise additional circuitry, such as the sensing amplifier of unit reads data selected by from array 300.

Word line controller 304 comprise the output that is configured in response to row decoder 302 and further in response to operator scheme to control being selected and the Circuits System be biased of wordline of non-selected row of array 300.The word line circuit system comprising word line controller 304 and row decoder 302 can be configured to make it possible in random access memory (RAM) pattern, read data value from one or more memory cell based on resistance and make it possible to read data value from one or more memory cell based on resistance ROM (read-only memory) (ROM) pattern.Such as, in RAM operator scheme, word line controller 304 can be configured to all wordline providing identical being biased.Such as, word line circuit system can be coupled to multiple row, and the every a line wherein based on the memory cell of resistance is coupled to two wordline.When selecting to comprise the column of memory cells based on resistance of the memory cell 320 based on resistance of Fig. 3 in RAM operator scheme, word line controller 304 can be biased wordline 316,318 to make this based on the access transistor conducting of the memory cell of resistance.Access transistor based on the memory cell 320 of resistance may correspond to the access transistor 130 and 136 of the access transistor 110 and 112 of the memory cell 101 based on resistance in Fig. 1 or the memory cell 103 based on resistance of Fig. 1.When not selecting the row of the memory cell 101 based on resistance comprising Fig. 1 in RAM operator scheme, word line controller 304 can be biased wordline 316 and 318 to make two access transistor cut-offs of the memory cell 320 based on resistance.

In ROM operator scheme, word line controller 304 can be configured to provide different voltage to the wordline in a pair selected wordline.Such as, if similarly configure based on the memory cell 320 of resistance with the memory cell 101 based on resistance of Fig. 1 or the memory cell 103 based on resistance of Fig. 1 and selected when the Circuits System of array 300 just operates in ROM operator scheme, then word line controller 304 can with the first voltage (such as, ground connection) come biased wordline 316 with make first access transistor cut-off and available second voltage (such as, supply voltage (Vdd)) carrys out biased wordline 318 to make the second access transistor conducting.When not selecting to comprise the row based on the memory cell 320 of resistance in ROM operator scheme, word line controller 304 can be biased wordline 316 and 318 to make two access transistor cut-offs of the memory cell 320 based on resistance.

Source line/bit line controller 308 comprises and is configured in response to the column selection of local data path 306, operator scheme (such as, RAM or ROM) and action type (such as, read, write " 0 " or write " 1 ") controls being selected of array 300 and not by the biased Circuits System of the source line of row selected and bit line.In one example, two specific source lines and a specific bit line coupling are to the memory cell columns based on resistance, and wherein the different sets of two source lines and a bit lines corresponds to the different lines based on the memory cell of resistance.Such as, in RAM operator scheme, source line/bit line controller 308 can be configured to all sources line providing identical being biased.Such as, when selecting the row comprised based on the memory cell 320 of resistance in RAM operator scheme, source line 310 and 312 can be biased to ground connection and can apply to read voltage (V to bit line 314 by source line/bit line controller 308 _read).When not selecting to comprise the row based on the memory cell 320 of resistance in RAM operator scheme, source line 310 and 312 and bit line 314 can be biased to ground connection by source line/bit line controller 308.

In ROM operator scheme, source line/bit line controller 308 can be configured to provide different voltage to the source line of selected source line centering.Such as, when selecting to comprise the row based on the memory cell 320 (memory cell 320 wherein based on resistance configures similarly with the memory cell 101 based on resistance of Fig. 1 or the memory cell 103 based on resistance of Fig. 1) of resistance in ROM operator scheme, source line/bit line controller 308 can with the first voltage (such as, V _read) carry out bias source line 310 and available second voltage (such as, ground connection) comes bias source line 312 and bit line 314.When not selecting to comprise the row based on the memory cell 320 of resistance in ROM operator scheme, source line 310 and 312 can be biased to the voltage (such as, ground connection) identical with bit line 314 by source line/bit line controller 308.

RAM/ROM mode control circuit 330 can send and the mode control signal 332 that will the pattern of memory array 300 used wherein corresponding.Mode control signal 332 can be received by one or more assemblies of memory array 300 (such as word line controller 304, line control unit 302, source line/bit line controller 308 and/or local data path 306).In a specific embodiment, the first value instruction first mode (such as, ROM pattern) of mode control signal 332, and second of mode control signal 332 the value instruction second pattern (such as, pattern ram).In another embodiment, mode control signal 332 command memory array 300 overturns (such as between RAM and ROM pattern, if present mode is ROM pattern, then memory array 300 switches to pattern ram in response to mode control signal 332).In one embodiment, memory array 300 initialization in ROM pattern (such as, powering on, guide or when reboot).

The Circuits System of control store array 300 can comprise the assembly be made up of word line controller 304, line control unit 302, source line/bit line controller 308, local data path 306 and RAM/ROM mode control circuit 330.These assemblies can be integrated in single larger circuit whole or in part, may be implemented in common tube core, and/or can be on a common printed circuit board.

The example of the operation of array 300 is explained orally in the table 400 of Fig. 4.Table 400 explain orally in a specific embodiment with the voltage status of each wordline, source line and the bit line that are associated based on the memory cell of resistance.Table 400 comprises the state for RAM and ROM operator scheme.Article two, wordline is designated as WL0 (such as, wordline 116 in Fig. 1, wordline 201 in Fig. 2, and/or the wordline 316 in Fig. 3) and WL1 (such as, wordline 118 in Fig. 1, wordline 202 in Fig. 2, and/or the wordline 318 in Fig. 3), article two, source line is designated as SL0 (such as, source line 104 in Fig. 1, source line 204 in Fig. 2, one of 216 or 222, and/or the source line 310 in Fig. 3) and SL1 (such as, source line 106 in Fig. 1, the source line 206 of Fig. 2, one of 218 or 224, or the source line 312 in Fig. 3), and bit line is designated as BL (such as, bit line 108 in Fig. 1, the bit line 214 of Fig. 2, one of 220 or 226, or the bit line 314 of Fig. 3).The voltage being applied to WL0, WL1, SL0, SL1 and BL by word line controller 304 and source line/bit line controller 308 has been explained orally for RAM read operation 402, RAM write " 0 " operation 404, RAM write " 1 " operation 406 and ROM read operation 408.

Fig. 5 has explained orally the embodiment for reading the method 500 of ROM data value from the memory cell (as illustrative indefiniteness example, the memory cell 320,322 or 324 based on resistance of the memory cell 101 or 103 based on resistance of such as Fig. 1, the memory cell 240,242 and 244 based on resistance of Fig. 2 and/or Fig. 3) based on resistance.502, relative at least one in bit line bias first source line or the second source line.Memory cell based on resistance is coupled to the first source line and bit line.Such as, the source line/bit line controller 308 of Fig. 3 is configured to such as read 408 relative at least one in bit line bias first source line or the second source line according to the ROM of Fig. 4.In this case, 504, activate the first access transistor.Such as, the first access transistor can use the wordline 316 of Fig. 3 to activate by word line controller 304.

506, the memory cell that reading electric current can flow through based on resistance whether is made to carry out detect data value based on the first access transistor.Such as, data value can be detected by the sensing circuit system in the local data path logic 306 of Fig. 3.In order to explain orally, can make about flowing through the comparison whether exceeding threshold quantity based on the electric current of the memory cell of resistance.When the first access transistor is coupled to when biased source line, reading electric current can flow through the memory cell based on resistance.Otherwise when not being coupled to through biased source line the access transistor be activated, under the threshold more much smaller than reading electric current, leakage current can flow through the memory cell based on resistance.This threshold value can be set smaller than the minimum value (such as, minimum expect to read the half of electric current) expecting to read electric current and whether make to read electric current (instead of under threshold leakage current) can flow through memory cell based on resistance to detect activation first access transistor.

Fig. 6 has explained orally the embodiment for reading the method 600 of ROM value from the memory cell (memory cell based on resistance read according to ROM operator scheme such as, in Fig. 1,2 or 3) based on resistance.ROM reads to comprise and detects be encoded to based on the value in the memory cell of resistance based on its coupled configuration by reading the current value that is associated with the memory cell based on resistance.This current value can be different from least two based on the coupled configuration of the layout of the memory cell based on resistance logical value be associated (such as, corresponding to the memory cell 101 based on resistance of Fig. 1 and the coupled configuration be associated with the first logical value 0 or correspond to the memory cell 103 based on resistance of Fig. 1 and the coupled configuration be associated with the second logical value 1).

602, voltage and current can be applied to the first source line of the memory cell based on resistance.Memory cell based on resistance can comprise the MTJ (MTJ) as resistive element.Such as, the memory cell based on resistance can be one of memory cell based on resistance of Fig. 1-2.Memory cell based on resistance comprises the first access transistor, and source-coupled to the first source line of the first access transistor.The drain coupled of the first access transistor is to the first terminal of MTJ element.604, ground connection can be remained on being coupled to based on the second source line of the memory cell of resistance and bit line.Memory cell based on resistance can comprise the second access transistor, and the source electrode of the second access transistor can be coupled to the second source line.The drain electrode of the second access transistor can be coupled to the first terminal of MTJ element.Second terminal of MTJ element can be coupled to bit line.606, determination electric current being detected about whether from least one the second source line and bit line can be made.

In a specific embodiment, if if detect that the amplitude of electric current or detected electric current is greater than the threshold quantity of electric current at the second source line and/or bit line place, then 608, the memory cell based on resistance is detected as has the first coupled configuration.Such as, the electric current detecting bit line place can comprise the electric current detected higher than threshold current.In another embodiment, the detection to electric current is comprised to the detection of any electric current.610, the exportable ROM data value corresponding to the first logical value (such as, as in Fig. 1 the logical zero that explains orally).

If if do not detect that the amplitude of electric current or detected electric current is less than threshold quantity, then 612, the memory cell based on resistance is detected as has the second coupled configuration.In this case, 614, the exportable ROM data value corresponding to the second logical value (such as, as in Fig. 1 the logical one that explains orally).

Fig. 7 explained orally for when being in RAM operator scheme have MTJ (MTJ) element that resistance is provided as in Fig. 1,2 and 3 based on the method 700 of the memory cell of resistance carrying out read operation.Memory cell based on resistance may be operably coupled to many source lines.702, the first wordline being coupled to the first access transistor and the second wordline being coupled to the second access transistor are configured to these access transistors biased and flow through these access transistors to enable electric current.704, can detect at bit line place and read electric current, and bit line may be operably coupled to the memory cell based on resistance, can flow through MTJ element can detect at bit line place to make the electric current provided at the first and second line places, source.706, reading electric current and reference current are compared.If read electric current to be less than reference current, then MTJ is in the high electrical resistance antiparallel state corresponding to the first logical value (such as logical one RAM data value).If this electric current is greater than reference current, then MTJ is in the comparatively low resistance parastate corresponding to the second logical value (such as logical zero RAM data value).

Fig. 8 has explained orally for changing the method 800 comprising the state of the memory cell based on resistance of MTJ (MTJ) element.801, use the first wordline to carry out biased the first transistor and use the second wordline to carry out biased transistor seconds, thus enabling electric current flow through this two transistors.These transistors couple are to the first terminal of MTJ element, and bit line coupling is to the second terminal of MTJ element.Exemplarily, the memory cell 103 based on resistance of the memory cell 101 based on resistance in Fig. 1 or Fig. 1 is may correspond to based on the memory cell of resistance.

When logical zero being write the memory cell based on resistance 802,803, first electric current and voltage can be applied to the first source line and the second source line.First source line is coupled to the first transistor and the second source line is coupled to transistor seconds.Bit line can be biased by the voltage (such as by local ground voltage level) more relatively low than source line.The electric current that result obtains may correspond in logic zero data value being write the reset current based on the memory cell of resistance.

When 802 will by the memory cell of logical one write based on resistance time, 804, second electric current and voltage are applied to bit line, the voltage of its neutrality line is higher than the voltage of the first and second source lines.First and second source lines can be set to local ground voltage level.Compared with the reset current for writing logic zero data value, MTJ element can be flow through in the opposite direction for the reset current writing logic one data value.

806, reset current can flow to bit line (if write logic zero data value) through MTJ element or flow to the first and second source lines (if write logic one data value) from bit line through MTJ element from the first and second source lines.808, the electric current flowing through MTJ element can cause and the MTJ memory cell based on resistance is arranged to logical zero or the corresponding resistance of logical one value changes.

With reference to figure 9, depict a kind of block diagram of specific illustrative embodiment of equipment, and this equipment is usually appointed as 900.Equipment 900 can comprise the processor 910 (such as, digital signal processor (DSP)) being coupled to memory devices 930.As explanation indefiniteness example, memory devices 930 can comprise the memory array 920 with one or more memory cells based on resistance (such as Fig. 1 based on the memory cell 100 of resistance, the memory cell 200 of the multiple of Fig. 2 based on resistance or the memory cell array 300 based on resistance of Fig. 3) that can use in RAM and ROM operator scheme.

Memory array 920 can comprise non-transient tangible computer readable unit with formation processing device readable storage medium storing program for executing.Memory array 920 can store the instruction 908 that can be performed by the processor 934 in Memory Controller 932.Alternatively or cumulatively, instruction 908 can be performed by processor 910.Instruction 908 can perform operation for reading ROM data value from the memory cell based on resistance of the first source line being coupled to memory array 920 of memory array 920, the second source line and bit line by processor 934 and/or processor 910.Instruction 908 can be performed with relative at least one in bit line bias first source line and the second source line.Instruction 908 can be performed first access transistor at the memory cell place activated based on resistance.Instruction 908 can be performed further performs detection to data value whether to make to read the electric current memory cell that can flow through based on resistance based on the first access transistor.Be stored in memory array 920 although instruction 908 is explained as, in other embodiments, instruction 908 partly or entirely can be stored in memory array 920 outside, be such as stored in the ROM936 that can be used by processor 934.

In one embodiment, instruction 908 in memory array 920 can be stored in the memory cell place based on resistance that can use as RAM and ROM cell, some of them instruction can use that the RAM based on the storer of resistance is functional to be read from the storer based on resistance, and other instruction set (such as guidance code) can use, and the ROM based on the storer of resistance is functional to be read.Memory array 920 also can use the functional information to any type of ROM based on the storer of resistance to encode, such as to store one or more table 928 (such as one or more table of trigonometric function).Trigonometric function by by table 928 as searching medium to evaluate, instead of whenever calling trigonometric function, make purpose processor 910 or mathematics processor (explanation) calculate trigonometric function.The indefiniteness example as illustrative, use sine or cosine function exemplarily, lookup result from table 928 can spend for about 10 nanoseconds (ns) fetched, and the calculating in processor 910 or math co-processor (explanation) can spend about 100ns to calculate identical result.Replace trigonometric function or except trigonometric function, this one or more table 928 can store one or more mathematical function.Such as, Fast Fourier Transform (FFT) coefficient and/or other mathematical function data can be stored in table 928.Because each memory cell based on resistance can keep data as RAM and ROM simultaneously, thus compared with there is the storer of only RAM or only ROM cell, increase the data available density of memory array 920, and storer 928 can realize using the minimizing of plate or chip space.Alternatively or cumulatively, with do not store the storer of ROM value based on coupled configuration compared with, more data can be stored in the size not increasing memory array 920 in memory array 920 (such as table 928 and/or instruction 908).

Fig. 9 also show the display controller 916 being coupled to processor 910 and display 928.Encoder/decoder (CODEC) 904 can be coupled to processor 910.Loudspeaker 906 and microphone 912 can be coupled to CODEC904.

Fig. 9 indicates wireless controller 926 can be coupled to processor 910 and antenna 922.In a specific embodiment, processor 910, display controller 916, memory array 920, CODEC904 and wireless controller 926 are included in system in package or system-on-chip apparatus 902.In a specific embodiment, input equipment 918 and power supply 924 are coupled to system-on-chip apparatus 902.In addition, in a particular embodiment, as shown in Figure 9 in the commentary, display 914, input equipment 918, loudspeaker 906, microphone 912, antenna 922 and power supply 924 are outside at system-on-chip apparatus 902.But each in display 914, input equipment 918, loudspeaker 906, microphone 912, antenna 922 and power supply 924 can be coupled to the assembly of system-on-chip apparatus 902, such as interface or controller.

In conjunction with described by embodiment, disclose a kind of equipment, it can comprise for the device relative at least one in bit line bias first source line and the second source line, and the memory cell wherein based on resistance is coupled to the first source line and bit line.Such as, the source line/bit line controller 308 of Fig. 3 can be comprised for biased device or be configured to any other controller and/or the Circuits System of at least one in biased first source line and the second source line.This equipment also can comprise the device of the first access transistor for activating the memory cell based on resistance.Such as, the device for activating can comprise the word line controller 304 of Fig. 3 or be configured to any other controller and/or the Circuits System of activation first access transistor.This equipment also can comprise reading for whether making based on the first access transistor the device that the electric current memory cell that can flow through based on resistance carrys out detect data value.Such as, whether the device for detecting can comprise the sensing circuit system in the local data path logic 306 of Fig. 3 or be configured to make to read any other data path logic and/or the Circuits System that the electric current memory cell that can flow through based on resistance carrys out detect data value based on the first access transistor.

Above-disclosed equipment and be functionally designed and be configured in the computer documents (such as, RTL, GDSII, GERBER etc.) be stored on computer-readable medium.Some or all these class files can be provided to the manufacture treatment people carrying out manufacturing equipment based on this class file.The product that result obtains comprises semiconductor wafer, and it is cut into semiconductor element subsequently and is packaged into semi-conductor chip.These chips are used in equipment described above subsequently.Figure 10 depicts the specific illustrative embodiment of electronic equipment manufacturing process 1000.

Physical device information 1002 is received manufacture process 1000 place (such as at research computing machine 1006 place).Physical device information 1002 can comprise the design information of at least one physical property representing semiconductor devices, the memory cell based on resistance of all Fig. 1 in this way of this semiconductor devices, Fig. 2 based on the memory cell of resistance, the memory array of Fig. 3 or its any combination.Such as, physical device information 1002 can comprise the physical parameter, material behavior and the structural information that input via the user interface 1004 being coupled to research computing machine 1006.Research computing machine 1006 comprises the processor 1008 being coupled to computer-readable medium (such as storer 1010), such as one or more process core.Storer 1010 can store computer-readable instruction, and it can be performed that physical device information 1002 is converted to by processor 1008 and follows a certain file layout and generate library file 1012.

In a specific embodiment, library file 1012 comprises the data file that at least one comprises the design information through conversion.Such as, library file 1012 can comprise the storehouse comprising the semiconductor devices of a device be provided to the coupling of electric design automation (EDA) instrument 1020, this device comprise Fig. 1 based on the memory cell 100 of resistance, the multiple of Fig. 2 based on the memory cell 200 of resistance, Fig. 3 based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination.

Library file 1012 can design a calculating machine 1014 places and eda tool 1020 is collaborative uses, and designs a calculating machine 1014 to comprise the processor 1016 being coupled to storer 1018, such as one or more process core.Eda tool 1020 can be used as processor executable be stored in storer 1018 sentence make to design a calculating machine 1014 user can the circuit of design library file 1012, this circuit comprise Fig. 1 based on the memory cell 100 of resistance, the multiple of Fig. 2 based on the memory cell 200 of resistance, Fig. 3 based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination.Such as, design a calculating machine 1014 user can via be coupled to design a calculating machine 1014 user interface 1024 carry out input circuit design information 1022.Circuit-design information 1022 can comprise the design information of at least one physical property representing semiconductor devices, all Fig. 1 in this way of this semiconductor devices based on the memory cell 100 of resistance, the multiple of Fig. 2 based on the memory cell 200 of resistance, Fig. 3 based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination.As explanation, circuit design character can comprise particular electrical circuit mark and with the relation of other elements in circuit design, locating information, characteristic dimension information, interconnect information or other information of physical property representing semiconductor devices.

Design a calculating machine and 1014 can be configured to conversion designs information (comprising circuit-design information 1022) to follow a certain file layout.As explanation, this document formatting can comprise and represent database binary file format about the plane geometric shape of circuit layout, text mark and other information, such as graphic data system (GDSII) file layout with hierarchical format.Except other circuit or information, design a calculating machine and 1014 can be configured to generate the data file of design information comprised through conversion, such as comprise describe Fig. 1 based on the memory cell 100 of resistance, the multiple of Fig. 2 based on the GDSII file 1026 of the information based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination of the memory cell 200 of resistance, Fig. 3.In order to explain orally, data file can comprise the information corresponding with SOC (system on a chip) (SOC), this SOC comprises the memory array of the memory cell based on resistance of RAM and the ROM300 use that can be used as Fig. 3, and also comprises additional electronic circuit and assembly in this SOC.

GDSII file 1026 can be received at manufacture process 1028 place with come according to the transitional information in GDSII file 1026 shop drawings 1 based on the memory cell 100 of resistance, the multiple of Fig. 2 based on the memory cell 200 of resistance, Fig. 3 based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination.Such as, equipment Manufacture Process can comprise GDSII file 1026 is supplied to mask manufacturer 1030 to create one or more mask, and such as the mask with photoetching treatment coupling, it is explained as representative mask 1032.Mask 1032 can be used to generate one or more wafer 1034 during manufacture process, and wafer 1034 can be tested and be divided into tube core, such as representative tube core 1036.Tube core 1036 comprises the circuit comprising a device, this device comprise Fig. 1 based on the MTJ memory cell 100 of resistance, the multiple of Fig. 2 based on the memory cell 200 of resistance, Fig. 3 based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination.

Tube core 1036 can be provided to encapsulation process 1038, and wherein tube core 1036 is included in representative encapsulation 1040.Such as, encapsulation 1040 can comprise singulated dies 1036 or multiple tube core, and such as system in package (SiP) arranges.Encapsulation 1040 can be configured to follow one or more standard or specification, such as joint electron device engineering council (JEDEC) standard.

Information about encapsulation 1040 such as can be distributed to each product designer via the Component Gallery being stored in computing machine 1046 place.Computing machine 1046 can comprise the processor 1048 being coupled to storer 1050, such as one or more process core.Printed circuit board (PCB) (PCB) instrument can be used as processor executable and is stored in storer 1050 and sentences and process the PCB design information 1042 that receives from the user of computing machine 1046 via user interface 1044.PCB design information 1042 can comprise through encapsulated semiconductor device physical positioning information on circuit boards, corresponding with encapsulation 1040 through encapsulated semiconductor device comprise Fig. 1 based on the memory cell 100 of resistance, the multiple of Fig. 2 based on the memory cell 200 of resistance, Fig. 3 based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination.

Computing machine 1046 can be configured to conversion PCB design information 1042 to generate data file, such as there is the semiconductor devices physical positioning information on circuit boards comprised through encapsulation, and the GERBER file 1052 of the data of the layout of electrical connection (such as trace and through hole), semiconductor devices wherein through encapsulation corresponds to encapsulation 1040, encapsulation 1040 comprises the memory cell 100 based on resistance of Fig. 1, multiple memory cells 200 based on resistance of Fig. 2, the memory cell array 300 based on resistance of Fig. 3, the memory array 920 of Fig. 9 and/or memory devices 930, or its any combination.In other embodiments, the data file generated by the PCB design information through conversion can have the extended formatting beyond GERBER form.

GERBER file 1052 can be received at plate assembling process 1054 place and be used to create the PCB manufactured according to the design information stored in GERBER file 1052, such as representative PCB1056.Such as, GERBER file 1052 can be uploaded to one or more machine to perform each step of PCB production run.PCB1056 can be filled with electronic package (comprising encapsulation 1040) to form representative P.e.c. assembly (PCA) 1058.

PCA1058 can be received at manufacture course of products 1060 place, and is integrated in one or more electronic equipment, such as the first representative electronic device 1062 and the second representative electronic device 1064.As illustrative but not indefiniteness example, first representative electronic device 1062, second representative electronic device 1064 or both can be selected from the group comprising the following: the memory cell 100 based on resistance being wherein integrated with Fig. 1, multiple memory cells 200 based on resistance of Fig. 2, the memory cell array 300 based on resistance of Fig. 3, the memory array 920 of Fig. 9 and/or memory devices 930, or the tablet device of its any combination, cell phone, laptop computer, Set Top Box, music player, video player, amusement unit, navigator, communication facilities, personal digital assistant (PDA), the data cell of fixed position, and computing machine.The indefiniteness example as another illustrative, one or more in electronic equipment 1062 and 1064 can be remote unit (such as mobile phone), handheld personal communication systems (PCS) unit, portable data units (such as personal digital assistant), the equipment enabling GPS (GPS), navigator, the data cell (such as meter reading equipment) of fixed position or any other equipment of storage or retrieve data or computer instruction or its any combination.Although Figure 10 has explained orally the remote unit according to instruction of the present disclosure, the disclosure has been not limited to these unit explained orally.Embodiment of the present disclosure can be used in any equipment comprising the active integrated circuit system with storer and on-chip circuit system suitably.

Described by illustrative process 1000, comprise Fig. 1 based on the memory cell 100 of resistance, the multiple of Fig. 2 based on the memory cell 200 of resistance, Fig. 3 the device based on the memory cell array 300 of resistance, the memory array 920 of Fig. 9 and/or memory devices 930 or its any combination can manufactured, process and bring in electronic equipment.About embodiment each disclosed in Fig. 1-8 one or more in can be included in each processing stage, such as be included in library file 1012, GDSII file 1026, and in GERBER file 1052, and be stored in the storer 1010 of research computing machine 1016, design a calculating machine 1014 storer 1018, the storer 1050 of computing machine 1046, other computing machines one or more used in each stage (such as at plate packaging technology 1054 place) or the storer (not shown) place of processor, and be included in other physical embodiments one or more, such as mask 1032, tube core 1036, encapsulation 1040, PCA1058, in other products (such as prototype circuit or equipment (not shown)), or its any combination.Although depict each the representative production phase being designed into final products from physical device, but the less stage can be used in other embodiments maybe can to comprise additional phase.Similarly, process 1000 can perform by single entity or by one or more entities in each stage of implementation 1000.

Technician will understand further, and the various illustrative boxes described in conjunction with embodiment disclosed herein, configuration, module, circuit and algorithm steps can be embodied as electronic hardware, the computer software performed by processor or the combination of both.Various illustrative components, frame, configuration, module, circuit and step have done vague generalization description above with its functional form.This type of is functional is implemented as hardware or processor executable depends on embody rule and is added to the design constraint of total system.Technician can realize described functional by different way for often kind of application-specific, but this type of realizes decision-making and is not to be read as and causes disengaging the scope of the present disclosure.

The method described in conjunction with embodiment disclosed herein or each step of algorithm can directly realize with hardware, the software module performed by processor or both combinations.Software module can reside in the non-transient memory device of random access memory (RAM), flash memory, ROM (read-only memory) (ROM), programmable read only memory (PROM), erasable type programmable read only memory (EPROM), electric erasable type programmable read only memory (EEPROM), register, hard disk, removable dish, compact disk ROM (read-only memory) (CD-ROM) or any other form known in the art.Exemplary memory device is coupled to processor, can read information and to this memory device written information to make processor from this memory device.In alternative, memory device can be integrated into processor.Processor and memory device can reside in special IC (ASIC).ASIC can reside in computing equipment or user terminal.In alternative, processor and memory device can be used as discrete assembly and reside in computing equipment or user terminal.

To make those skilled in the art all can make or use the disclosed embodiments to the description of the disclosed embodiments before providing.Can be apparent to those skilled in the art to the various amendments of these embodiments, and the principle defined herein can be applied to other embodiments and can not depart from the scope of the present disclosure.Therefore, the disclosure not intended to be is defined to the embodiment illustrated herein, but the widest possible range consistent with principle as defined by the accompanying claims and novel features should be awarded.

Claims

1. an equipment, comprising:

There is the memory cell based on resistance of multiple access transistor, the coupled configuration encoded data value of wherein said multiple access transistor bar source line at the most.

2. equipment as claimed in claim 1, it is characterized in that, described coupled configuration comprises the first configuration, the first access transistor described in described first configuration in multiple access transistor is coupled to the first source line and the second access transistor in described multiple access transistor is coupled to the second source line, and wherein said first configuration corresponds to described data value has the first value.

3. equipment as claimed in claim 2, it is characterized in that, the described memory cell based on resistance comprises MTJ (MTJ) element and wherein the second data value is stored in described MTJ element.

4. equipment as claimed in claim 3, it is characterized in that, described MTJ element is coupled to described first source line and described second source line further.

5. equipment as claimed in claim 3, it is characterized in that, comprise further and be arranged so that can read described data value in a first mode of operation and make it possible to read in this second mode of operation word line controller and the source line/bit line controller of described second data value.

6. equipment as claimed in claim 1, it is characterized in that, described data value has the first binary value or the second binary value.

7. equipment as claimed in claim 2, it is characterized in that, described equipment comprises and has second of more than second access transistor and the second coupled configuration based on the memory cell of resistance, the first access transistor in more than second access transistor described in described second coupled configuration is coupled to the 3rd source line and the second access transistor in described more than second access transistor is coupled to the 4th source line, and wherein said second configuration corresponds to described data value has the second value.

8. an equipment, comprising:

Word line controller; And

Be coupled to the column of memory cells based on resistance of described word line controller, wherein saidly comprise multiple access transistor based on the memory cell based on resistance in the column of memory cells of resistance, the coupled configuration encode first data value of wherein said multiple access transistor bar source line at the most.

9. equipment as claimed in claim 8, it is characterized in that, comprise further and be coupled to the first source line and the memory cell columns based on resistance being coupled to the second source line, wherein said based on described in the column of memory cells of resistance based on the memory cell of resistance described based in the memory cell columns of resistance.

10. equipment as claimed in claim 9, it is characterized in that, comprise multiple column of memory cells based on resistance and multiple memory cell columns based on resistance further, described multiple row and multiple row are configured to operate as ROM (read-only memory) (ROM) in a kind of operator scheme and operate as random access memory (RAM) in another kind of operator scheme.

11. equipment as claimed in claim 10, is characterized in that, described multiple row and described multiple row are encapsulated as one single chip.

12. equipment as claimed in claim 11, is characterized in that, described data value corresponds to the first binary value or the second binary value.

13. 1 kinds for reading the method for data, described method comprises:

Relative at least one in bit line bias first source line and the second source line, wherein said first source line and described bit line coupling are to the memory cell based on resistance;

Activate described the first access transistor based on the memory cell of resistance; And

Whether make reading electric current can flow through the described memory cell based on resistance based on described first access transistor and carry out detect data value.

14. methods as claimed in claim 13, is characterized in that, described data value corresponds to the first binary value or the second binary value.

15. methods as claimed in claim 13, is characterized in that, comprise further:

Biased first wordline and the second wordline are to change the described state based on MTJ (MTJ) element of the memory cell of resistance.

16. methods as claimed in claim 15, is characterized in that, the described state of described MTJ element corresponds to the first binary value or the second binary value.

17. methods as claimed in claim 15, is characterized in that, the state detecting described MTJ element is included in the voltage that read operations detects bit line place further.

18. 1 kinds of equipment, comprising:

For the device relative at least one in bit line bias first source line and the second source line;

For activating the device of the first access transistor of the memory cell based on resistance, the wherein said memory cell based on resistance is coupled to described first source line and described bit line; And

The device that the described memory cell based on resistance carrys out detect data value can be flow through for whether making to read electric current based on described first access transistor.

19. equipment as claimed in claim 18, it is characterized in that, being describedly integrated in following one for biased device, described device for activating and the described device for detecting: the data cell of tablet device, cell phone, laptop computer, Set Top Box, music player, video player, amusement unit, navigator, communication facilities, personal digital assistant (PDA), fixed position and computing machine.

20. 1 kinds of computer readable storage devices storing instruction, described instruction can perform with executable operations by processor, and described operation comprises:

Relative at least one in bit line bias first source line and the second source line;

Activate the first access transistor based on the memory cell of resistance, the wherein said memory cell based on resistance is coupled to described first source line and described bit line; And

Whether make reading electric current can flow through the described memory cell based on resistance based on described first access transistor and detect the described data value based on the memory cell of resistance.

21. computer readable storage devices as claimed in claim 20, it is characterized in that, described instruction can be performed by the processor be integrated in following one: the data cell of tablet device, cell phone, laptop computer, Set Top Box, music player, video player, amusement unit, navigator, communication facilities, personal digital assistant (PDA), fixed position and computing machine.

22. 1 kinds of methods, comprising:

For the first step relative at least one in bit line bias first source line and the second source line, the memory cell wherein based on resistance is coupled to described first source line, described second source line and described bit line;

For activating the described second step based on the first access transistor of the memory cell of resistance; And

The third step that the described memory cell based on resistance carrys out detect data value can be flow through for whether making to read electric current based on described first access transistor.

23. methods as claimed in claim 22, is characterized in that, described first step, described second step and described third step are performed by the processor be integrated in electronic equipment.

24. 1 kinds of methods, comprising:

Receive design information, described design information comprises through encapsulated semiconductor device physical positioning information on circuit boards, describedly comprise the memory cell based on resistance with multiple access transistor through encapsulated semiconductor device, the coupled configuration encoded data value of wherein said multiple access transistor bar source line at the most; And

Change described design information to generate data file.

25. methods as claimed in claim 24, it is characterized in that, described data file has GERBER form.

26. methods as claimed in claim 24, it is characterized in that, described data file comprises GDSII form.