CN105578689A - Power saver with power line carrier unit - Google Patents
Power saver with power line carrier unit Download PDFInfo
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- CN105578689A CN105578689A CN201610102922.2A CN201610102922A CN105578689A CN 105578689 A CN105578689 A CN 105578689A CN 201610102922 A CN201610102922 A CN 201610102922A CN 105578689 A CN105578689 A CN 105578689A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a power saver with a power line carrier unit. The power saver comprises a first relay, a second relay, a first inductor and a second inductor which are connected in series, an MCU (Micro-programmed Control Unit) module, and a power supply module, an acquisition module, a power line carrier module and a driving unit which are connected with the MCU module respectively, wherein the first inductor is an overvoltage winding; the second inductor is a power-reducing winding; the power supply module is used for providing working voltage to the MCU module; the power line carrier module is used for receiving a power line carrier signal transmitted by an integrated controller, demodulating the power line carrier signal and transmitting the power line carrier signal to the MCU module; the power line carrier module is also used for receiving a feedback instruction fed back by the MCU module, converting the feedback instruction to the power line carrier signal, coupling the power line carrier signal to an alternating-current power line and then transmitting the power line carrier signal to the integrated controller; and the feedback instruction is working state information of a current discharging lamp. The power saver with the power line carrier unit has the advantages of simplicity in operation and convenience for utilization.
Description
Technical Field
The invention relates to a power saver with a power carrier unit.
Background
With the continuous improvement of living standard, people have higher and higher requirements on urban lighting environment, so that not only safety lighting is required, but also lighting for improving urban image is added. The relevant departments stipulate: during normal lighting periods, the standard specified illuminance should be achieved, and during periods when normal lighting is not required (e.g., the next midnight), only the safe illuminance may be retained, with the illuminance value generally held at half of the standard. The image illumination of the city is several times of the standard illumination at present, far exceeds the national standard, and wastes a large amount of energy under the condition of only needing to keep the safe illumination. Therefore, in the time period without the need of urban image illumination, the illumination is reduced to the safe illumination so as to achieve the purpose of energy saving.
Disclosure of Invention
The present invention is directed to a power saver with a power carrier unit, which can solve the above-mentioned disadvantages of the prior art.
The invention adopts the following technical scheme:
an electricity saver having a power carrier unit, comprising: the system comprises a first relay, a second relay, a first inductor, a second inductor, an MCU module, a power supply module, an acquisition module, a power carrier module and a driving unit, wherein the first inductor and the second inductor are connected in series;
the first inductor is an overvoltage winding, and the second inductor is a power reduction winding;
the power supply module provides working voltage for the MCU module;
the power carrier module receives a power carrier signal sent by the centralized controller, demodulates the power carrier signal and sends the demodulated power carrier signal to the MCU module; receiving a feedback instruction fed back by the MCU module, converting the feedback instruction into a power carrier signal, and sending the power carrier signal to the centralized controller by coupling the power carrier signal to an alternating current power line; the feedback instruction is the current working state information of the discharge lamp: the power carrier module comprises a first power carrier coupling channel and a second power carrier coupling channel; the first power carrier coupling channel is arranged between the live wire and the zero line of the alternating current cable, and receives and transmits a first carrier signal between the live wire and the zero line of the alternating current cable; the second power carrier coupling channel is arranged between the ground wire and the zero line of the alternating current cable, the second carrier signal is received and sent between the ground wire and the zero line of the alternating current cable, the second power carrier coupling channel further comprises a filter circuit, a power carrier processing circuit and a carrier power amplifier circuit, the first power carrier coupling channel and the second power carrier coupling channel are connected in parallel and are connected with one end of the filter circuit, the other end of the filter circuit is connected with the input end of the power carrier processing circuit, the output end of the power carrier processing circuit is connected with the input end of the carrier power amplifier circuit, and the output end of the carrier power amplifier circuit is respectively connected with the first power carrier coupling channel and the second power carrier coupling channel;
the MCU module generates a corresponding MCU instruction according to the power carrier signal sent by the power carrier module or the received voltage signal which is acquired by the acquisition module and subjected to isolation protection;
the driving unit receives the MCU instruction and drives the first relay or the second relay to act, and the driving unit comprises a pulse square wave generator and at least one driving module;
the output end of the pulse square wave generator is connected with the first input end of the driving module, the pulse square wave generator inputs a high-frequency square wave pulse signal to the first input end of the driving module, the driving module is also provided with a second input end for inputting a low-frequency driving signal, the driving module comprises a signal conversion circuit unit and a driving circuit unit, and the signal conversion circuit unit is connected with the driving circuit unit through a pulse transformer;
when the second input end of the driving module is at a high level, the signal conversion circuit unit converts the input low-frequency driving signal and the input high-frequency square wave pulse signal into an alternating-current high-frequency pulse signal, and the pulse transformer outputs a driving voltage signal through the driving circuit unit after isolating and transforming the alternating-current high-frequency pulse signal; the number of the driving modules is at least two, the first input end of each driving module is respectively connected with the output end of the pulse square wave generator, and the second input end of each driving module is respectively used for inputting corresponding low-frequency driving signals;
the power module comprises a voltage conversion unit, an overvoltage protection unit and a power supply, wherein the input end of the voltage conversion unit is connected with the power supply to receive a first voltage provided by the power supply, and the output end of the voltage conversion unit is connected with the electronic element; the overvoltage protection unit comprises a signal input end, a signal processing circuit, a low-voltage amplitude limiting circuit and a high-voltage amplitude limiting circuit, wherein the signal input end is connected with an input resistor; the low-voltage amplitude limiting circuit comprises a first amplitude limiting control voltage, a first voltage dividing resistor, a second voltage dividing resistor, a first amplitude limiting capacitor and an NPN bipolar transistor; the high-voltage amplitude limiting circuit comprises a second amplitude limiting control voltage, a third voltage dividing resistor, a fourth voltage dividing resistor, a second amplitude limiting capacitor and a PNP bipolar transistor.
The connecting point of the first relay and the second relay is connected with one end of the first inductor and one end of the second inductor which are connected in series; the other end of the first inductor is connected with a first static contact of the first relay, and the other end of the second inductor is connected with a second static contact of the second relay; the movable contact of the first relay is connected with the acquisition module, and the movable contact of the second relay is connected with the standard inductor.
The voltage conversion unit includes: the device comprises a power supply circuit, an energy storage booster circuit, a positive voltage generating circuit, a negative voltage generating circuit and a reference voltage generating circuit; the energy storage booster circuit comprises a booster chip and an inductor;
the output end of the power supply circuit is respectively connected with the input end of the boosting chip and the first end of the inductor;
the second end of the inductor is respectively connected with the control end of the boosting chip, the input end of the positive voltage generating circuit, the input end of the negative voltage generating circuit and the input end of the reference voltage generating circuit;
the power supply circuit is used for providing a unipolar input voltage;
the boosting chip is used for controlling the voltage at two ends of the inductor and respectively providing the voltage at two ends of the inductor to the positive voltage generating circuit, the negative voltage generating circuit and the reference voltage generating circuit;
the positive voltage generating circuit is used for generating a positive voltage according to the voltage at two ends of the inductor;
the negative voltage generating circuit is used for generating a negative voltage according to the voltage at two ends of the inductor;
the reference voltage generating circuit is used for generating reference voltage according to the voltage at two ends of the inductor.
The positive voltage generating circuit is a first charge pump circuit, wherein the first charge pump circuit is used for generating a positive voltage according to the voltage at two ends of the inductor, the first charge pump circuit comprises an N-level charge pump circuit, and N is a positive integer greater than or equal to 1.
The Nth-stage charge pump circuit of the first charge pump circuit comprises a first capacitor, a first diode and a second diode; wherein,
the cathode of the first capacitor is connected with the second end of the inductor, and the anode of the first capacitor is respectively connected with the anode of the first diode and the cathode of the second diode; the anode of the second diode is connected with the cathode of the first diode in the N-1 st level charge pump circuit of the first charge pump circuit;
and the negative electrode of the first diode outputs the positive voltage according to the voltage at the two ends of the inductor and the voltage of the positive electrode of the first capacitor.
The emitter of the NPN bipolar transistor and the emitter of the PNP bipolar transistor are both connected to the input end of the signal processing circuit; the first voltage dividing resistor is connected in series between the first amplitude limiting control voltage and the base electrode of the NPN bipolar transistor; the second voltage-dividing resistor is connected with the first amplitude limiting capacitor in parallel, and one end of the second voltage-dividing resistor and one end of the first amplitude limiting capacitor are both connected with the base electrode of the NPN bipolar transistor; the other ends of the second voltage-dividing resistor and the first amplitude-limiting capacitor and the collector of the NPN bipolar transistor are connected to a reference ground; the third voltage dividing resistor is connected in series between the second amplitude limiting control voltage and the base electrode of the PNP bipolar transistor; the fourth voltage-dividing resistor is connected with the second amplitude limiting capacitor in parallel, and one end of the fourth voltage-dividing resistor and one end of the second amplitude limiting capacitor are both connected with the base electrode of the PNP bipolar transistor; and the other ends of the fourth voltage-dividing resistor and the second amplitude limiting capacitor and the collector of the PNP bipolar transistor are connected to a reference ground.
The first amplitude limiting control voltage and the second amplitude limiting control voltage are both external direct-current voltage sources, the first amplitude limiting control voltage is lower than a reference ground voltage, and the second amplitude limiting control voltage is higher than the reference ground voltage.
The negative voltage generating circuit is a second charge pump circuit, wherein the second charge pump circuit is used for outputting the negative voltage according to the voltage at two ends of the inductor, the second charge pump circuit comprises M stages of charge pump circuits, and M is a positive integer greater than or equal to 1.
The pulse transformer is provided with a primary winding and a secondary winding, two output ends of the full-bridge inverter circuit unit are respectively connected with two input ends of the primary winding, and two output ends of the secondary winding are respectively connected with two input ends of the driving circuit unit;
when the second input end of the driving module is at a high level, the nand gate unit converts the low-frequency driving signal and the high-frequency square wave pulse signal into two complementary direct-current high-frequency pulse signals, the frequency and the pulse width of the direct-current high-frequency pulse signals are the same as those of the high-frequency square wave pulse signals, and the full-bridge inverter circuit unit inverts the two complementary direct-current high-frequency pulse signals into alternating-current high-frequency pulse signals.
IN the nand gate unit, a first input end of the nand gate device UA is a first input end IN1 of the driving module, a second input end of the nand gate device UA is connected with a first input end of the nand gate device UB, the first input end of the nand gate device UB is a second input end IN2 of the driving module, and the second input end of the nand gate device UB is connected with an output end of the nand gate device UA.
The invention has the advantages that: the operation is simple and the use is convenient.
Drawings
The invention is described in detail below with reference to examples and figures, in which:
fig. 1 is a schematic structural view of the present invention.
Fig. 2 is a block diagram of the power supply circuit.
Fig. 3 is a circuit diagram of fig. 2.
Fig. 4 is a schematic structural diagram of the voltage conversion unit.
Fig. 5 is a circuit diagram of the driving unit of the present invention.
Fig. 6 is a circuit diagram of the driving module of fig. 5.
Fig. 7 is a circuit diagram of a power carrier module of the present invention.
Detailed Description
The embodiments of the invention are further illustrated in the following figures:
as shown in fig. 1, an electricity saver with a power line carrier unit disclosed for an embodiment of the present invention mainly includes: the device comprises a first relay KA1, a first inductor L2, a first relay coil 101, a second relay KA2, a second inductor L3, a second relay coil 102, an MCU module 103, a power module 104, a power carrier module 105, an acquisition module 106 and a driving unit 107.
The power module 104, the power carrier module 105, the collection module 106, and the driving unit 107 are respectively connected to the MCU module 103, and the power module 104 receives a voltage of AC220V ± 20% in a power grid (L in fig. 1 represents a live wire, and N represents a zero wire), and converts the received voltage into a working voltage of the MCU module 103, so that the MCU module 103 works normally. The power carrier module 105 communicates with a centralized controller (not shown) at the discharge lamp control box for sending and receiving power carrier signals. When the centralized controller sends a power carrier signal to the power saver of the present invention, the power carrier module 105 receives the power carrier signal sent by the centralized controller, demodulates the power carrier signal and sends the demodulated power carrier signal to the MCU module 103, and then the MCU module 103 generates a corresponding MCU command to drive an output signal. When the MCU module 103 needs to feed back corresponding information to the centralized controller, that is, the current operating state information of the discharge lamp, the MCU module 103 sends a relevant instruction to the power carrier module 105, and the power carrier module 105 converts the received instruction into a power carrier signal and sends the power carrier signal to the centralized controller by coupling the power carrier signal to the ac power line. The power carrier module 105 communicates with the centralized controller, so that the discharge lamp 108 can be remotely controlled, that is, the intelligent control of the lighting of the discharge lamp 108 can be completed.
The sampling module 106 is mainly used for collecting voltage signals in a line, and transmitting the collected voltage signals to the MCU module 103 after isolation protection. The MCU module 103 is mainly configured to receive the voltage signal processed by the sampling module 106 and the power carrier signal sent by the power carrier module 105, generate a corresponding MCU command according to the received signal, and feed back the current operating state information of the discharge lamp 108 to the centralized controller through the power carrier module 105.
The driving unit 107 is mainly used for receiving an MCU instruction sent by the MCU module 103, and then powering on or powering off the first relay coil 101 or the second relay coil 102 according to the MCU instruction, so as to drive the first relay KA1 or the second relay KA2 to operate. As shown in fig. 1, the first relay coil 101 and the second relay coil 102 are connected to a driving unit 107, respectively.
The first relay KA1 and the second relay KA2 are provided with three contacts, namely a movable contact, a first fixed contact and a second fixed contact. In the embodiment disclosed in the invention, the second stationary contact of the first relay KA1 is connected with the first stationary contact of the second relay KA2, the first inductor L2 is connected in series with the second inductor L3, and the connection point of the first relay KA1 and the second relay KA2 is connected with one end of the first inductor L2 connected in series with the second inductor L3, as shown in fig. 1.
In addition, the other end of the first inductor L2 is connected with the first stationary contact of the first relay KA1, and the other end of the second inductor L3 is connected with the second stationary contact of the second relay KA 2; the movable contact of the first relay KA1 is connected with the acquisition module 106, and the movable contact of the second relay KA2 is connected with the original standard inductor L1 in the discharge lamp circuit.
It should be noted that the first inductor L2 is an overvoltage winding, and when the line voltage is too high, the MCU module 103 sends a corresponding MCU command to make the driving unit 107 drive the first relay KA1 to operate, so as to connect the first inductor L2 to the line.
The second inductor L3 is a power reduction winding, and when the power of the discharge lamp needs to be reduced, the MCU module 103 controls the operation of the second relay KA2 to connect the second inductor L3 to the line.
As shown in fig. 2 and 3, the power module 10 includes a voltage converting unit 12, an overvoltage protection unit 16, and a power supply 18. The voltage conversion unit 12 is connected to the overvoltage protection unit 16. The power supply 18 is connected to both the voltage converting unit 12 and the over-voltage protection unit 16. The voltage converting unit 12 is configured to convert the first voltage provided by the power supply 18 into an operating voltage, and output the converted voltage from an output terminal of the voltage converting unit 12. The overvoltage protection unit 16 is configured to control the power supply 18 to stop outputting the voltage when the voltage output by the output terminal of the voltage conversion unit 12 is greater than the working voltage, so as to protect the voltage.
The overvoltage protection unit 16 comprises an overvoltage protection circuit, the overvoltage protection circuit comprises a signal input end Vs, a signal processing circuit, a low-voltage amplitude limiting circuit and a high-voltage amplitude limiting circuit, wherein the signal input end Vs is connected with an input resistor Ri; the low-voltage amplitude limiting circuit comprises a first amplitude limiting control voltage Ve, a first voltage-dividing resistor R11, a second voltage-dividing resistor R12, a first amplitude limiting capacitor C11 and an NPN bipolar transistor Q1; the high-voltage amplitude limiting circuit comprises a second amplitude limiting control voltage Vc, a third voltage-dividing resistor R13, a fourth voltage-dividing resistor R14, a second amplitude limiting capacitor C12 and a PNP bipolar transistor Q2; the emitter of the NPN bipolar transistor Q1 and the emitter of the PNP bipolar transistor Q2 are both connected to the input end Vi of the signal processing circuit; the first voltage-dividing resistor R1 is connected in series between the first amplitude-limiting control voltage Ve and the base of the NPN bipolar transistor Q1; the second voltage-dividing resistor R2 is connected in parallel with the first amplitude limiting capacitor C11, and one end of the second voltage-dividing resistor R12 and one end of the first amplitude limiting capacitor C11 are both connected with the base electrode of the NPN bipolar transistor Q1; the second voltage-dividing resistor R12, the other end of the first limiting capacitor C11 and the collector of the NPN bipolar transistor Q1 are connected to the ground GND; the third voltage-dividing resistor R13 is connected in series between the second amplitude-limiting control voltage Vc and the base of the PNP bipolar transistor Q2; the fourth voltage-dividing resistor R14 is connected in parallel with the second amplitude limiting capacitor C12, and one end of the fourth voltage-dividing resistor R14 and one end of the second amplitude limiting capacitor C12 are both connected with the base electrode of the PNP bipolar transistor Q2; the fourth voltage-dividing resistor R14, the other end of the second clipping capacitor C12 and the collector of the PNP bipolar transistor Q2 are both connected to the ground GND.
The first amplitude limiting control voltage Ve and the second amplitude limiting control voltage Vc are both external direct-current voltage sources, the first amplitude limiting control voltage Ve is lower than the reference ground GND voltage, and the second amplitude limiting control voltage Vc is higher than the reference ground GND voltage.
Given a first amplitude limiting control voltage Ve and a second amplitude limiting control voltage Vc, the base voltage of an NPN bipolar transistor Q1 is fixed at Va, where Ve × R12/(R11+ R12), the base voltage of a PNP bipolar transistor Q2 is fixed at Vb, and Vb × Vc × R14/(R13+ R14); when the input end voltage Vi of the signal processing circuit is lower than the base voltage Va of the NPN bipolar transistor Q1, the emitter junction and the collector junction of the NPN bipolar transistor Q1 are forward biased and reversely biased, the NPN bipolar transistor Q1 works in an amplifying state, and the input end voltage Vi of the signal processing circuit is limited to the base voltage Va of the NPN bipolar transistor Q1 minus the emitter junction voltage thereof; when the input terminal voltage Vi of the signal processing circuit is higher than the base voltage Vb of the PNP bipolar transistor Q2, the emitter junction and collector junction of the PNP bipolar transistor Q2 are forward biased and reverse biased, the PNP bipolar transistor Q2 operates in an amplified state, and the input terminal voltage Vi of the signal processing circuit is limited to the base voltage Vb of the PNP bipolar transistor Q2 plus the emitter junction voltage thereof. The first clipping capacitor C11 and the second clipping capacitor C12 filter Va and Vb, respectively. The overvoltage protection circuit has the advantages of simple circuit structure, high amplitude limiting precision and capability of conveniently changing amplitude limiting voltage.
As shown in fig. 4, the negative voltage generating circuit 4 is a 1-stage charge pump circuit capable of generating a negative voltage, wherein the capacitor C2 and the diodes D2 and D3 form a charge pump circuit, the second capacitor C2 is a positive electrode, the left end of the second capacitor C2 is a negative electrode, the right end of the second capacitor C2 is a negative electrode, the third diode D2 is a negative electrode, and the fourth diode D3 is a positive electrode. The anode of the second capacitor C2 is connected to the right end of the inductor L1, the cathode of the second capacitor C2 is connected to the anode of the third diode D2 and the cathode of the fourth diode D3, respectively, the anode of the fourth diode D3 outputs a negative voltage, and the cathode of the third diode D2 is grounded. The specific operating principle of the negative voltage generating circuit 4 is as follows: the capacitor C2 is charged through the output voltage of the inductor L1, the polarity of the capacitor C2 is positive left and negative right, and then a charging path of the inductor L1 to the capacitor C2 is disconnected; because the voltage across the capacitor C2 cannot change abruptly, the right negative voltage is output through the diode D3 to obtain the negative voltage VGL. If M is greater than or equal to 2, the cathode of the third diode D2 is connected with the anode of the third diode in the M-1 st stage charge pump circuit, so that the multi-stage charge pump circuit is formed. The negative voltage generating circuit 4 may further include a capacitor C3 and a zener diode D8 at the output end of the M-stage charge pump circuit, the capacitor C3 is used for filtering the output negative voltage, and the zener diode D8 realizes voltage stabilization output. The reference voltage generating circuit comprises at least one voltage stabilizing diode, the anode of the voltage stabilizing diode is connected with the second end of the inductor, and the cathode of the voltage stabilizing diode outputs reference voltage according to the anode voltage of the voltage stabilizing diode.
The reference voltage generating circuit 5 includes a zener diode D1, an anode of the zener diode D1 is connected to the right end of the inductor L1, and a cathode thereof outputs a negative voltage VGL. The reference voltage generating circuit 5 may further include a capacitor C1, and the capacitor C1 is used for filtering the output negative voltage.
The voltage conversion circuit provided by the embodiment adopts the multi-stage charge pump circuit to respectively realize the output of positive voltage and negative voltage, changes the magnitude of the output positive voltage and negative voltage by changing the stage number of the charge pump circuit, and has the advantages of simple circuit structure, flexibility and adjustability. The driving circuit realizes signal isolation by using the pulse transformer through the design of the whole circuit, so that compared with the traditional driving circuit which adopts a photoelectric coupling signal isolation mode, the driving circuit of the invention does not need an additional independent power supply, thereby saving the power supply and having better working stability.
As shown in fig. 5 and 6, the driving unit of the present invention comprises a driving circuit including a pulse square wave generator MD1 and a driving module MD 2; the output terminal OUT of the pulse square wave generator MD1 is connected to the first input terminal IN1 of the driving module MD2, the driving module MD2 further has a second input terminal IN2 for inputting the low-frequency driving signal DRIVEA, the driving module includes a signal conversion circuit unit 100 and a driving circuit unit 200, and the signal conversion circuit unit 100 and the driving circuit unit 200 are connected through a pulse transformer T1.
The signal conversion circuit unit 100 includes a nand gate unit 111 and a full-bridge inverter circuit unit 112, two output ends of the nand gate unit 101 are respectively connected to two input ends of the full-bridge inverter circuit unit 112, the pulse transformer T1 has a primary winding and a secondary winding, two output ends of the full-bridge inverter circuit unit 112 are respectively connected to two input ends of the primary winding, and two output ends of the secondary winding are respectively connected to two input ends of the driving circuit unit 200; the driving circuit unit 200 includes a full-bridge rectifier circuit 201 and an output circuit 202, the full-bridge rectifier circuit 201 is connected to two output terminals of the secondary winding of the pulse transformer T1, the full-bridge rectifier circuit 201 has a positive output terminal and a negative output terminal, and the output circuit 202 is connected to the positive output terminal and the negative output terminal.
IN the nand gate unit 111, a first input end of the nand gate device UA is a first input end IN1 of the driving module MD2, a second input end of the nand gate device UA is connected to a first input end of the nand gate device UB, the first input end of the nand gate device UB is a second input end IN2 of the driving module MD2, and the second input end of the nand gate device UB is connected to an output end of the nand gate device UA. In the above-mentioned full-bridge inverter circuit unit 112, one end of the gate resistor R101 and one end of the gate resistor R103 are respectively connected to the output end of the nand gate device UB, the other end of the gate resistor R101 is connected to the gate of the P-channel fet V1, the source of the P-channel fet V1 is connected to one end of the current-limiting resistor R105, the other end of the current-limiting resistor R105 is connected to the power source VCC, the power source VCC is further connected to the current-limiting resistor R106, the other end of the current-limiting resistor R106 is connected to the source of the P-channel fet V2, the gate of the P-channel fet V2 is connected to the gate resistor R102, the other end of the gate resistor R102 is connected to the output end of the nand gate device UA, the output end of the nand gate device UA is further connected to the gate resistor R104, the other end of the gate resistor R104 is connected to the gate of the N-channel fet V4, the source of the N, the source electrode of the N-channel field effect transistor V3 is also connected with a power ground, the drain electrode of the P-channel field effect transistor V2 and the drain electrode of the N-channel field effect transistor V4 are respectively connected with one end of the primary winding of the pulse transformer T1, and the drain electrode of the P-channel field effect transistor V1 and the drain electrode of the N-channel field effect transistor V3 are respectively connected with the other end of the primary winding of the pulse transformer T1.
The full-bridge rectifier circuit 201 includes four diodes D101, D102, D10103, D104, one end of the secondary winding of the pulse transformer T1 is connected to the anode of the diode D101 and the cathode of the diode D10103 respectively, the cathode of the diode D101 is connected to the cathode of the diode D102, the anode of the diode D102 and the cathode of the diode D104 are connected to the other end of the secondary winding of the pulse transformer T1 respectively, the anode of the diode D104 is connected to the anode of the diode D10103, in the full-bridge rectifier circuit 201, the anode of the diode D101 or the diode D102 is the positive output terminal, and the cathode of the diode D10103 or the diode D104 is the negative output terminal.
The output circuit 202 includes a diode D105, a P-channel fet V5, a resistor R107, and a resistor R108, wherein the _ anode of the diode D105 is connected to the positive output terminal, the gate of the P-channel fet V5, and the resistor R107, the other end of the resistor R107 is connected to the negative output terminal and the drain of the P-channel fet V5, the cathode of the diode D105 is connected to the source of the P-channel fet V5 and the resistor R108, and a driving voltage signal output terminal is formed between the other end G of the resistor R108 and the negative output terminal E. The field effect transistors V1, V2, V3, V4, and V5 may be MOSFETs.
The driving circuit mainly adopts the working principle that a driving module is as follows: a first input IN1 of the driving module MD2 is connected to the output OUT of the pulsed square wave generator MD1, and a second input IN2 of the driving module MD2 is connected to an external low-frequency driving signal, typically a pulsed square wave generator MD1 outputting a pulsed square wave with a frequency IN the range of tens of khz to tens of khz, and an external low-frequency driving signal DRIVEA connected to the input IN2 with a frequency IN the range of a few tenths of hz to hundreds of hz; under the condition that the second input terminal IN2 of the driving module MD2 is high: when the first input terminal IN1 of the driving module MD2 is at a high level, the output pin of the nand gate device UA is at a low level, and the output pin of the nand gate device UB is at a high level; when the first input terminal IN1 of the driving module MD2 is at a low level, the output pin of the nand gate device UA is at a high level, and the output pin of the nand gate device UB is at a low level. Therefore, when the input terminal IN2 is at high level, the output pins of the nand gate devices UA and UB output two complementary dc high frequency pulse signals with the same frequency and pulse width as the first input terminal IN1, the two complementary dc high frequency pulse signals drive the full bridge inverter circuit composed of P-channel fets V1, V2 and N-channel fets V3, V4 through the gate resistors R101, R102, R103 and R104, and then the dc high frequency pulse signals are inverted into ac high frequency pulse signals, the ac high frequency pulse signals are isolated and transformed by the pulse transformer T1, the ac high frequency pulse signals output by the pulse transformer T1 are rectified by the full bridge rectifier circuit 201 composed of diodes D101, D102, D10103 and D104, the positive output terminal of the gate thereof has positive voltage, the P-channel fet V5 is IN cut-off state due to the same source voltage, and thus there is driving voltage at the output terminals G and E of the driving voltage signals, finally, the driven power tube is conducted; under the condition that the second input terminal IN2 of the driving module MD2 is low: the output pins of the nand gate devices UA and UB both output high levels, so that the field effect transistors V3 and V4 on the inverter bridge are turned on, and thus both ends of the primary winding of the pulse transformer T1 are connected to the power ground without voltage, and at this time, the output terminal of the pulse transformer T1 has no voltage, so that a voltage difference is generated between the gate and the source of the P-channel field effect transistor V5 to turn on the P-channel field effect transistor V, and the driving voltage signal output terminals G and E are turned on through R108, that is, a voltage is lost between G and E, and finally, the driven power transistor is in a blocking state. IN summary, the driving voltage signal outputted between the driving voltage signal output terminals G and E follows the low frequency driving signal at the second input terminal IN2 of the driving module MD2, when the second input terminal IN2 is at high level, there is driving signal at G and E of the driving module, otherwise there is no driving signal, so as to achieve the purpose of driving circuit. The voltage conversion circuit provided by the embodiment adopts the multi-stage charge pump circuit to respectively realize the output of positive voltage and negative voltage, changes the magnitude of the output positive voltage and negative voltage by changing the stage number of the charge pump circuit, and has the advantages of simple circuit structure, flexibility and adjustability. The driving circuit realizes signal isolation by using the pulse transformer through the design of the whole circuit, so that compared with the traditional driving circuit which adopts a photoelectric coupling signal isolation mode, the driving circuit of the invention does not need an additional independent power supply, thereby saving the power supply and having better working stability.
As shown in fig. 7, the first power carrier coupling channel 1051, the second power carrier coupling channel 1052, the filter circuit 1053, the power carrier processing circuit 1054, and the carrier power amplifier circuit 1055, where the first power carrier coupling channel 1051 is disposed between the live line AC _ L and the neutral line AC _ N of the AC cable, and receives and transmits a first carrier signal between the live line AC _ L and the neutral line AC _ N of the AC cable; the second power carrier coupling channel 1052 is disposed between the ground line AC _ PE and the neutral line AC _ N of the AC cable, and receives and transmits a second carrier signal between the ground line AC _ PE and the neutral line AC _ N of the AC cable. Because the existing noise and interference are mainly between the live wire and the zero wire, high-frequency interference signals are serious, and the signals are coupled to the zero wire and the ground wire, because no voltage or high-frequency interference exists between the zero wire and the ground wire, relatively speaking, no interference signals between the live wire and the zero wire are large. After the power carrier signal is sent by the carrier power amplifier circuit, the power carrier signal is coupled into two channels, namely a first power carrier coupling channel 1051 and a second power carrier coupling channel 1052, if an interference signal between a live wire and a zero line is large, the power carrier signal can be transmitted to next equipment through the channels of the zero line and the ground wire, the coupling signals of the two channels are received in the next equipment at the same time, as long as one channel can normally receive the signal, communication is carried out, and the problem that information cannot be transmitted due to interference when single-channel data transmission is carried out is well solved. Meanwhile, the circuit can realize multi-channel carrier coupling by only adding one power carrier coupling channel, and has small modification and low cost on the existing circuit.
Meanwhile, signals can be transmitted through the two channels, data transmission can be performed between the ground wire AC _ PE and the zero line AC _ N under the condition of direct current or no voltage, and compared with the existing method, data transmission can be performed only under the condition of alternating current, and the practicability is enlarged.
The first power carrier coupling channel 1051 comprises a fifth inductor L51, a fifth capacitor C51 and a first coupling transformer T1, the fifth inductor L51 and the fifth capacitor C51 are connected in series, one end of the fifth inductor L51 is connected with a live wire AC _ L, the other end of the fifth inductor C51 is connected with a first coupling transformer T1, one side of the first coupling transformer T1 is connected with the live wire AC _ L and a null wire AC _ N, respectively, and the other side of the first coupling transformer T1 is connected with an output end of the carrier power amplification circuit 1055 and the filter circuit 1053. The second power carrier coupling channel 1052 includes a second inductor L52, a fifth second capacitor C52 and a second coupling transformer T2, the second inductor L52 and the fifth second capacitor C52 are connected in series, one end of the second inductor L52 is connected to the ground line AC _ PE, the other end of the second inductor L52 is connected to the second coupling transformer T2, one side of the second coupling transformer T2 is connected to the ground line AC _ PE and the neutral line AC _ N, respectively, and the other side of the second coupling transformer T2 is connected to the output end of the carrier power amplifier circuit 1055 and the filter circuit 1053.
The coupling mode of the invention can carry out high-low voltage isolation, and the insulation withstand voltage can reach 4 KV. And a triple insulated wire double-wire winding mode is adopted. Because the invention is coupled 1:1, will not amplify noise or interfere with, utilize the triple insulated wire to carry on the bifilar and wound at the same time, compare with traditional single winding way, can reduce the interference, guarantee the signal is undistorted. The first power carrier coupling channel 1051 and the second power carrier coupling channel 1052 are connected in parallel and connected to one end of the filter circuit 1053, the other end of the filter circuit 1053 is connected to an input end of the power carrier processing circuit 1054, an output end of the power carrier processing circuit 1054 is connected to an input end of the carrier power amplifier circuit 1055, and an output end of the carrier power amplifier circuit 1055 is connected to the first power carrier coupling channel 1051 and the second power carrier coupling channel 1052, respectively.
The filter circuit comprises a high-resistance and low-resistance third-order filter, an attenuator and an amplitude limiting circuit, wherein the high-resistance and low-resistance third-order filter comprises: the inductor comprises a fifth fourth capacitor C54 and a fifth fourth inductor L54 which are connected in parallel, a fifth capacitor C55 and a fifth inductor L55 which are connected in parallel, a fifth sixth capacitor C56 and a sixth inductor L6 which are connected in parallel, and a fifth seventh capacitor C57 and a fifth eight capacitor C58 which are connected in parallel, wherein one end of the fifth capacitor C55 and the fifth inductor L55 which are connected in parallel is connected with the ground terminal, the other end of the fifth capacitor C54 and one end of the fifth fourth inductor L54 which are connected in parallel is connected with one end of the fifth eight capacitor C58, one end of the fifth capacitor C57 is connected with the coupling channel, the other end of the fifth capacitor C57 is connected with the other end of the fifth capacitor C54 and the fifth inductor L54 which are connected in parallel, and the other end of the fifth eight capacitor C58 is connected with one end of the fifth capacitor C56 and one end of the fifth inductor L56 which are connected in parallel. In the embodiment, the T-type third-order filter is adopted for filtering, so that the bandwidth is wide, the filtering effect is better, and in other embodiments, the traditional pi-type filtering can also be adopted. The fifth fourth inductor L54 is connected with the fifth fourth capacitor C54 in parallel, and the fifth sixth inductor L56 is connected with the fifth sixth capacitor C56 in parallel, so that high-frequency waves above 140K are blocked; the fifth inductor L55 is connected in parallel with the fifth capacitor C55, high-frequency waves below 120K are blocked, and therefore high-resistance and low-resistance filtering is achieved.
The attenuator includes fifth resistance R51, fifth second resistance R52, fifth switch tube Q51 and control signal end CAGC, the one end ground connection of fifth resistance R51, the other end of fifth resistance R51 is connected with control signal end CAGC, the control of fifth switch tube Q51, the one end ground connection of fifth switch tube Q51, the other end links to each other with the one end of fifth second resistance R52, power carrier processing circuit 1054 is connected to the other end of fifth second resistance R52. The power carrier signal may be attenuated by 60db through the circuit by an attenuator to attenuate the interfering signal.
The amplitude limiting circuit comprises two diodes D51 and D52 which are in opposite directions and connected in parallel, one end of the diode connected in parallel is grounded, and the other end of the diode connected in parallel is connected with the power carrier processing circuit. Because the conduction voltage of the diode is 0.7V, the amplitude of the carrier signal is limited within 0.7V, so that the carrier chip is prevented from being burnt down due to overlarge signal.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. An electricity-saving appliance having a power carrier unit, comprising: the system comprises a first relay, a second relay, a first inductor, a second inductor, an MCU module, a power supply module, an acquisition module, a power carrier module and a driving unit, wherein the first inductor and the second inductor are connected in series;
the first inductor is an overvoltage winding, and the second inductor is a power reduction winding;
the power supply module provides working voltage for the MCU module;
the power carrier module receives a power carrier signal sent by the centralized controller, demodulates the power carrier signal and sends the demodulated power carrier signal to the MCU module; receiving a feedback instruction fed back by the MCU module, converting the feedback instruction into a power carrier signal, and sending the power carrier signal to the centralized controller by coupling the power carrier signal to an alternating current power line; the feedback instruction is the current working state information of the discharge lamp: the power carrier module comprises a first power carrier coupling channel and a second power carrier coupling channel; the first power carrier coupling channel is arranged between the live wire and the zero line of the alternating current cable, and receives and transmits a first carrier signal between the live wire and the zero line of the alternating current cable; the second power carrier coupling channel is arranged between the ground wire and the zero line of the alternating current cable, the second carrier signal is received and sent between the ground wire and the zero line of the alternating current cable, the second power carrier coupling channel further comprises a filter circuit, a power carrier processing circuit and a carrier power amplifier circuit, the first power carrier coupling channel and the second power carrier coupling channel are connected in parallel and are connected with one end of the filter circuit, the other end of the filter circuit is connected with the input end of the power carrier processing circuit, the output end of the power carrier processing circuit is connected with the input end of the carrier power amplifier circuit, and the output end of the carrier power amplifier circuit is respectively connected with the first power carrier coupling channel and the second power carrier coupling channel;
the MCU module generates a corresponding MCU instruction according to the power carrier signal sent by the power carrier module or the received voltage signal which is acquired by the acquisition module and subjected to isolation protection;
the driving unit receives the MCU instruction and drives the first relay or the second relay to act, and the driving unit comprises a pulse square wave generator and at least one driving module;
the output end of the pulse square wave generator is connected with the first input end of the driving module, the pulse square wave generator inputs a high-frequency square wave pulse signal to the first input end of the driving module, the driving module is also provided with a second input end for inputting a low-frequency driving signal, the driving module comprises a signal conversion circuit unit and a driving circuit unit, and the signal conversion circuit unit is connected with the driving circuit unit through a pulse transformer;
when the second input end of the driving module is at a high level, the signal conversion circuit unit converts the input low-frequency driving signal and the input high-frequency square wave pulse signal into an alternating-current high-frequency pulse signal, and the pulse transformer outputs a driving voltage signal through the driving circuit unit after isolating and transforming the alternating-current high-frequency pulse signal; the number of the driving modules is at least two, the first input end of each driving module is respectively connected with the output end of the pulse square wave generator, and the second input end of each driving module is respectively used for inputting corresponding low-frequency driving signals;
the power module comprises a voltage conversion unit, an overvoltage protection unit and a power supply, wherein the input end of the voltage conversion unit is connected with the power supply to receive a first voltage provided by the power supply, and the output end of the voltage conversion unit is connected with the electronic element; the overvoltage protection unit comprises a signal input end, a signal processing circuit, a low-voltage amplitude limiting circuit and a high-voltage amplitude limiting circuit, wherein the signal input end is connected with an input resistor; the low-voltage amplitude limiting circuit comprises a first amplitude limiting control voltage, a first voltage dividing resistor, a second voltage dividing resistor, a first amplitude limiting capacitor and an NPN bipolar transistor; the high-voltage amplitude limiting circuit comprises a second amplitude limiting control voltage, a third voltage dividing resistor, a fourth voltage dividing resistor, a second amplitude limiting capacitor and a PNP bipolar transistor.
2. The power saver with the power carrier unit according to claim 1, wherein a connection point of the first relay and the second relay is connected with one end of the first inductor and the second inductor which are connected in series; the other end of the first inductor is connected with a first static contact of the first relay, and the other end of the second inductor is connected with a second static contact of the second relay; the movable contact of the first relay is connected with the acquisition module, and the movable contact of the second relay is connected with the standard inductor.
3. The power saver of claim 2 wherein the voltage conversion unit comprises: the device comprises a power supply circuit, an energy storage booster circuit, a positive voltage generating circuit, a negative voltage generating circuit and a reference voltage generating circuit; the energy storage booster circuit comprises a booster chip and an inductor;
the output end of the power supply circuit is respectively connected with the input end of the boosting chip and the first end of the inductor;
the second end of the inductor is respectively connected with the control end of the boosting chip, the input end of the positive voltage generating circuit, the input end of the negative voltage generating circuit and the input end of the reference voltage generating circuit;
the power supply circuit is used for providing a unipolar input voltage;
the boosting chip is used for controlling the voltage at two ends of the inductor and respectively providing the voltage at two ends of the inductor to the positive voltage generating circuit, the negative voltage generating circuit and the reference voltage generating circuit;
the positive voltage generating circuit is used for generating a positive voltage according to the voltage at two ends of the inductor;
the negative voltage generating circuit is used for generating a negative voltage according to the voltage at two ends of the inductor;
the reference voltage generating circuit is used for generating reference voltage according to the voltage at two ends of the inductor.
4. The power saver of claim 3 wherein the positive voltage generating circuit is a first charge pump circuit, wherein the first charge pump circuit is configured to generate a positive voltage according to the voltage across the inductor, and the first charge pump circuit comprises N stages of charge pump circuits, where N is a positive integer greater than or equal to 1.
5. The power saver of claim 4 wherein the Nth stage charge pump circuit of the first charge pump circuit comprises a first capacitor, a first diode, and a second diode; wherein,
the cathode of the first capacitor is connected with the second end of the inductor, and the anode of the first capacitor is respectively connected with the anode of the first diode and the cathode of the second diode; the anode of the second diode is connected with the cathode of the first diode in the N-1 st level charge pump circuit of the first charge pump circuit;
and the negative electrode of the first diode outputs the positive voltage according to the voltage at the two ends of the inductor and the voltage of the positive electrode of the first capacitor.
6. The power saver with the power carrier unit according to claim 5, wherein an emitter of the NPN bipolar transistor and an emitter of the PNP bipolar transistor are both connected to the input end of the signal processing circuit; the first voltage dividing resistor is connected in series between the first amplitude limiting control voltage and the base electrode of the NPN bipolar transistor; the second voltage-dividing resistor is connected with the first amplitude limiting capacitor in parallel, and one end of the second voltage-dividing resistor and one end of the first amplitude limiting capacitor are both connected with the base electrode of the NPN bipolar transistor; the other ends of the second voltage-dividing resistor and the first amplitude-limiting capacitor and the collector of the NPN bipolar transistor are connected to a reference ground; the third voltage dividing resistor is connected in series between the second amplitude limiting control voltage and the base electrode of the PNP bipolar transistor; the fourth voltage-dividing resistor is connected with the second amplitude limiting capacitor in parallel, and one end of the fourth voltage-dividing resistor and one end of the second amplitude limiting capacitor are both connected with the base electrode of the PNP bipolar transistor; and the other ends of the fourth voltage-dividing resistor and the second amplitude limiting capacitor and the collector of the PNP bipolar transistor are connected to a reference ground.
7. The power saver of claim 6, wherein the first and second clipping control voltages are external DC voltage sources, and the first clipping control voltage is lower than a reference ground voltage and the second clipping control voltage is higher than the reference ground voltage.
8. The power saver of claim 7 wherein the negative voltage generation circuit is a second charge pump circuit, wherein the second charge pump circuit is configured to output the negative voltage according to the voltage across the inductor, and the second charge pump circuit comprises M stages of charge pump circuits, wherein M is a positive integer greater than or equal to 1.
9. The power saver according to claim 8, wherein the signal conversion circuit unit comprises a nand gate unit and a full-bridge inverter circuit unit, two output terminals of the nand gate unit are respectively connected to two input terminals of the full-bridge inverter circuit unit, the pulse transformer has a primary winding and a secondary winding, two output terminals of the full-bridge inverter circuit unit are respectively connected to two input terminals of the primary winding, and two output terminals of the secondary winding are respectively connected to two input terminals of the driving circuit unit;
when the second input end of the driving module is at a high level, the nand gate unit converts the low-frequency driving signal and the high-frequency square wave pulse signal into two complementary direct-current high-frequency pulse signals, the frequency and the pulse width of the direct-current high-frequency pulse signals are the same as those of the high-frequency square wave pulse signals, and the full-bridge inverter circuit unit inverts the two complementary direct-current high-frequency pulse signals into alternating-current high-frequency pulse signals.
10. The power saver of claim 9, wherein IN the nand gate unit, a first input of the nand gate UA is the first input IN1 of the driving module, a second input of the nand gate UA is connected to a first input of the nand gate UB, the first input of the nand gate UB is the second input IN2 of the driving module, and the second input of the nand gate UB is connected to the output of the nand gate UA.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610102922.2A CN105578689A (en) | 2016-02-25 | 2016-02-25 | Power saver with power line carrier unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610102922.2A CN105578689A (en) | 2016-02-25 | 2016-02-25 | Power saver with power line carrier unit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106711923A (en) * | 2017-02-17 | 2017-05-24 | 中领世能（天津）科技有限公司 | Isolation protection device and power supply system |
| CN106711922A (en) * | 2017-02-17 | 2017-05-24 | 中领世能（天津）科技有限公司 | Electrical shock protection device and power supply system |
| CN109814399A (en) * | 2019-01-30 | 2019-05-28 | 吕树人 | The smart home system of carrier wave between a kind of zero curve based on ground |
| CN115134978A (en) * | 2021-04-16 | 2022-09-30 | 深圳市紫光新能源技术有限公司 | a light control system |
| CN117908627A (en) * | 2024-03-19 | 2024-04-19 | 成都市思叠科技有限公司 | Negative pressure benchmark thick film hybrid integrated circuit based on reverser principle |
| CN118842455A (en) * | 2024-09-20 | 2024-10-25 | 苏州联讯仪器股份有限公司 | Pulse width modulation driving circuit, method and test equipment |
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2016
- 2016-02-25 CN CN201610102922.2A patent/CN105578689A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106711923A (en) * | 2017-02-17 | 2017-05-24 | 中领世能（天津）科技有限公司 | Isolation protection device and power supply system |
| CN106711922A (en) * | 2017-02-17 | 2017-05-24 | 中领世能（天津）科技有限公司 | Electrical shock protection device and power supply system |
| CN109814399A (en) * | 2019-01-30 | 2019-05-28 | 吕树人 | The smart home system of carrier wave between a kind of zero curve based on ground |
| CN115134978A (en) * | 2021-04-16 | 2022-09-30 | 深圳市紫光新能源技术有限公司 | a light control system |
| CN117908627A (en) * | 2024-03-19 | 2024-04-19 | 成都市思叠科技有限公司 | Negative pressure benchmark thick film hybrid integrated circuit based on reverser principle |
| CN117908627B (en) * | 2024-03-19 | 2024-05-24 | 成都市思叠科技有限公司 | Negative pressure benchmark thick film hybrid integrated circuit based on reverser principle |
| CN118842455A (en) * | 2024-09-20 | 2024-10-25 | 苏州联讯仪器股份有限公司 | Pulse width modulation driving circuit, method and test equipment |
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