CN105575944B - A kind of mixing interconnection structure and its manufacturing method, electronic device - Google Patents
A kind of mixing interconnection structure and its manufacturing method, electronic device Download PDFInfo
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- CN105575944B CN105575944B CN201410537822.3A CN201410537822A CN105575944B CN 105575944 B CN105575944 B CN 105575944B CN 201410537822 A CN201410537822 A CN 201410537822A CN 105575944 B CN105575944 B CN 105575944B
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Abstract
A kind of mixing interconnection structure of present invention offer and its manufacturing method, electronic device.The method includes：Semiconductor substrate is provided；The first interlayer dielectric layer is formed on the semiconductor substrate；And it is respectively formed aluminum interconnecting and copper interconnecting line in first interlayer dielectric layer, wherein the aluminum interconnecting is used as signal wire, and the copper interconnecting line is used as power cord.Compared with simple copper interconnection structure, this mixing interconnection structure has lower resistance on the whole, while electromigration reliability does not also decline, and can be adapted for smaller and smaller semiconductor processing dimensions.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of mixing interconnection structure and its manufacturing method, electricity
Sub-device.
Background technology
In semiconductor integrated circuit, the signal transmission between semiconductor devices needs highdensity metal interconnecting wires.It passes
The metal interconnection of system realized by aluminium, but with the development of semiconductor technology, traditional aluminium interconnection technique by
Gradually replaced by copper interconnection technology.As the size reduction of cmos device in integrated circuit is to 14nm and hereinafter, copper interconnection technology
In RC retardation ratio become and restrict the key factor that further increases of performance of integrated circuits, attracted more and more concerns.
Wherein, resistance R depends greatly on crystallite dimension and intrinsic resistance.It is expected that dimensional effect, including surface and crystal boundary scattering,
The effective resistivity of copper interconnection structure will be increased considerably.In addition, diffusion impervious layer is excessively poor conductor, shared by metal
The score of line volume is also increasing.
Therefore, to solve the above problems, it is necessary to propose a kind of manufacturing method of improved interconnection structure.
Invention content
In view of the deficiencies of the prior art, a kind of mixing interconnection structure of present invention offer and its manufacturing method, electronic device, should
Interconnection structure has lower resistance and preferable electromigration reliability.
According to an aspect of the present invention, a kind of manufacturing method of mixing interconnection structure is provided, the method includes：It provides
Semiconductor substrate；The first interlayer dielectric layer is formed on the semiconductor substrate；And divide in first interlayer dielectric layer
It Xing Cheng aluminum interconnecting and copper interconnecting line, wherein the aluminum interconnecting is used as signal wire, and the copper interconnecting line is used as power cord.
Optionally, it is respectively formed aluminum interconnecting on first interlayer dielectric layer and copper interconnecting line includes：Described in etching
First interlayer dielectric layer, to form copper-connection through-hole and aluminium through-hole interconnection in first interlayer dielectric layer；It is mutual in the copper
Aluminum metal layer in intercommunicating pore and the aluminium through-hole interconnection and on first interlayer dielectric layer；Etch the aluminum metal
Layer, to form the aluminum interconnecting；The deposited sacrificial layer on first interlayer dielectric layer and the aluminum interconnecting；Described in etching
Sacrificial layer, to form copper interconnection groove in the sacrificial layer；The deposited copper metal layer in the copper interconnection groove, to form copper
Interconnection line；And the sacrificial layer is removed, with the exposure copper interconnecting line and the aluminum interconnecting.
Optionally, the method further includes：After removing the sacrificial layer, in the copper interconnecting line and the aluminium
The top of interconnection line and side wall deposition diffusion impervious layer.
Optionally, the material of the diffusion impervious layer is graphene.
Optionally, the diffusion impervious layer is deposited using laser writing technology.
Optionally, the method further includes：After depositing the diffusion impervious layer, on the diffusion impervious layer
Deposit the second interlayer dielectric layer.
According to another aspect of the present invention, a kind of mixing interconnection structure manufactured according to the above method is provided.
According to another aspect of the invention, a kind of electronic device is provided, includes the mixing manufactured according to the above method
Interconnection structure.
According to the manufacturing method of mixing interconnection structure provided by the invention, using aluminum interconnecting as signal wire, with copper-connection
Line is as power cord.What it is due to signal wire conduction is bidirectional current, is not influenced by electromigration effect, therefore may be used anti-
The poor aluminium interconnection structure of electric migration performance.And diffusion impervious layer need not be added in aluminium interconnection structure, therefore can be in nanometer
The volume for reducing interconnection line under grade scale, to reduce the resistance of interconnection structure.Power cord conduction is unidirectional current (direct current),
It is affected by electromigration effect, therefore using the preferable copper interconnection structure of deelectric transferred performance as power cord.With it is simple
Copper interconnection structure compare, this mixing interconnection structure has lower resistance on the whole, while electromigration reliability does not have yet
Decline, can be adapted for smaller and smaller semiconductor processing dimensions.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Fig. 1 a to Fig. 1 i show the committed step of the manufacturing method of mixing interconnection structure according to an embodiment of the invention
Obtained in semiconductor devices diagrammatic cross-section；And
Fig. 2 shows the flow charts of the manufacturing method of mixing interconnection structure according to the ... of the embodiment of the present invention.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
In order to thoroughly understand the present invention, detailed step will be proposed in following description, to illustrate proposition of the present invention
Mixing interconnection structure manufacturing method.Obviously, execution of the invention be not limited to semiconductor applications technical staff institute it is ripe
The specific details of habit.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, the present invention may be used also
With with other embodiment.
It should be understood that when the term " comprising " and/or " including " is used in this specification, indicating described in presence
Feature, entirety, step, operation, element and/or component, but do not preclude the presence or addition of other one or more features, entirety,
Step, operation, element, component and/or combination thereof.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.
Embodiment one
Fig. 1 a to Fig. 1 i show the committed step of the manufacturing method of mixing interconnection structure according to an embodiment of the invention
Obtained in semiconductor devices diagrammatic cross-section.It is mutual in conjunction with the mixing provided by the present invention of Fig. 1 a to Fig. 1 f detailed descriptions
Link the manufacturing method of structure.
With reference to figure 1a, semiconductor substrate 101 is provided.The constituent material of the semiconductor substrate 101 may be used undoped
Monocrystalline silicon, the monocrystalline silicon doped with impurity, silicon-on-insulator (SOI) etc..It could be formed in the semiconductor substrate 101
Isolation channel, buried layer, various traps (well) structure or lower part interconnection structure, to put it more simply, being omitted in diagram.
A is continued to refer to figure 1, forms the first interlayer dielectric layer 102 in the semiconductor substrate 101.First interlayer
Dielectric layer 102 can be low k or ultra-low-k dielectric layer, and material can be such as silicon oxide carbide (SiOC).
Later, the method includes：It is respectively formed aluminum interconnecting and copper-connection on first interlayer dielectric layer 102
Line, wherein the aluminum interconnecting is used as signal wire, and the copper interconnecting line is used as power cord.It will be understood by those skilled in the art that
" power cord " described herein may include ground wire.What it is due to signal wire conduction is bidirectional current, is not imitated by electromigration
The influence answered, therefore the poor aluminium interconnection structure of deelectric transferred performance may be used.And expansion need not be added in aluminium interconnection structure
Barrier layer is dissipated, therefore the volume of interconnection line can be reduced under nano-scale dimension, to reduce the resistance of interconnection structure.Power cord
Conduction is unidirectional current (direct current), is affected by electromigration effect, therefore mutual with the preferable copper of deelectric transferred performance
Link structure as power cord.Compared with simple copper interconnection structure, this mixing interconnection structure has lower resistance on the whole,
Electromigration reliability does not also decline simultaneously, can be adapted for smaller and smaller semiconductor processing dimensions.The step is specifically wrapped
Include following step.
With reference to figure 1b, first interlayer dielectric layer 102 is etched, to form copper in first interlayer dielectric layer 102
Through-hole interconnection 104 and aluminium through-hole interconnection 103.The etching can be dry etch process, and used etching gas can wrap
Include fluoro-gas (CF4、CHF3、CH2F2Deng), diluent gas (He, N2Deng) and oxygen.
With reference to figure 1c, in the copper-connection through-hole 104 and the aluminium through-hole interconnection 103 and first interlayer dielectric
Aluminum metal layer 105 on layer 102.Flowability al deposition process deposits may be used in the deposition of the aluminum metal layer 105.Tool
The realization of Amber metal deposition techniques may be used in body.It is by the physical vaporous deposition of selectivity come deposited metal layer so that
In the bottom deposit of the groove and/or through-hole metal thicker than at the top of it.This can be to avoid the top of groove and/or through-hole heavy
It is blocked by metal during product, causes to leave cavity below groove and/or through-hole.Later during reflux, due to
Capillary effect makes metal be filled from the bottom of groove and/or through-hole to top-direction, therefore zero defect may be implemented, without cavity
Filling.The vertical wide ratio of groove and/or through-hole is bigger, and filling effect is better.Therefore, the Amber metal deposition techniques can
Adapt to the vertical wide ratio of smaller and smaller dimensions of semiconductor devices and interconnection line increasing therewith.
With reference to figure 1d, the aluminum metal layer 105 is etched, to form aluminum interconnecting 106.Subraction figure may be used herein
Change the mode of (subtractive patterning) to etch the aluminum metal layer 105.It is graphically obtained using subraction
Crystal grain in metal interconnection structure is bigger, therefore electron scattering effect is small, and resistivity is also smaller.
With reference to figure 1e, the deposited sacrificial layer 107 on first interlayer dielectric layer 102 and the aluminum interconnecting 106.It sacrifices
Layer 107 can be siliceous bottom anti-reflection layer (Si-BARC) or ultra-deep oxide skin(coating) (Deep Ultra Oxidation,
DUO) etc..
With reference to figure 1f, the sacrificial layer 107 is etched, to form copper interconnection groove 108 in the sacrificial layer 107.Copper is mutual
Even groove 108 can define the position of copper interconnecting line.
With reference to figure 1g, the deposited copper metal layer in the copper interconnection groove 108, to form copper interconnecting line 110.This field skill
Art personnel are appreciated that after depositing the copper metal layer, method may further include to the copper metal layer
The step of learning mechanical lapping, details are not described herein.According to one embodiment of present invention, the deposition of the copper metal layer can adopt
It is deposited with flowability copper deposition process.Amber metal deposition techniques as described above specifically may be used, it is no longer superfluous herein
It states.
G is continued to refer to figure 1, the sacrificial layer 107 is removed, with the exposure copper interconnecting line 109 and the aluminum interconnecting
106。
Optionally, the method may further include：After removing the sacrificial layer 107, in the copper interconnecting line
109 and the aluminum interconnecting 106 top and side wall deposition diffusion impervious layer.With reference to figure 1h, the diffusion impervious layer is shown as
Diffusion impervious layer 110.In one embodiment, the material of the diffusion impervious layer is graphene.It is mutual as copper using graphene
Link the diffusion impervious layer of structure, it is possible to reduce the oxidation of copper metal and the diffusion into the surface of copper ion, therefore interconnection can be improved
The electro migration resistance of structure.In one embodiment, laser writing technology may be used depositing described can reduce copper metal
Oxidation and the diffusion into the surface of copper ion, therefore the electro migration resistance layer 110 of interconnection structure can be improved.
Optionally, the method may further include：After depositing the diffusion impervious layer 110, in the diffusion
The second interlayer dielectric layer is deposited on barrier layer 110.As shown in figure 1i, second interlayer dielectric layer is shown as the second interlayer dielectric
Layer 111.The material of second interlayer dielectric layer 111 can be such as silica.
Fig. 2 shows the flow charts of the manufacturing method 200 of mixing interconnection structure according to the ... of the embodiment of the present invention.As shown in Fig. 2,
The method 200 includes：
Step S201：Semiconductor substrate is provided.
Step S202：The first interlayer dielectric layer is formed on the semiconductor substrate.
Step S203：It is respectively formed aluminum interconnecting and copper interconnecting line on first interlayer dielectric layer, wherein the aluminium
Interconnection line is used as signal wire, and the copper interconnecting line is used as power cord.
According to the manufacturing method of mixing interconnection structure provided by the invention, using aluminum interconnecting as signal wire, with copper-connection
Line is as power cord.Compared with simple copper interconnection structure, this mixing interconnection structure has lower resistance on the whole, simultaneously
Electromigration reliability does not also decline, and can be adapted for smaller and smaller semiconductor processing dimensions.
Embodiment two
The present invention also provides a kind of mixing interconnection structure, the mixing interconnection structure selects the side described in above-described embodiment
Method manufactures.According to mixing interconnection structure provided by the invention, using aluminum interconnecting as signal wire, using copper interconnecting line as power supply
Line.Compared with simple copper interconnection structure, this mixing interconnection structure has lower resistance on the whole, while electromigration is reliable
Property does not also decline, and can be adapted for smaller and smaller semiconductor processing dimensions.
Embodiment three
The present invention also provides a kind of electronic devices, including the mixing interconnection structure described in embodiment two.Wherein, mixing is mutual
It is the mixing interconnection structure described in embodiment two to link structure, or the mixing interconnection that the manufacturing method according to embodiment one obtains
Structure.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products for including the mixing interconnection structure.The electronic device of the embodiment of the present invention mixes due to the use of above-mentioned
Interconnection structure is closed, thus there is better performance.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (8)
1. a kind of manufacturing method of mixing interconnection structure, including：
Semiconductor substrate is provided；
The first interlayer dielectric layer is formed on the semiconductor substrate；And
It is respectively formed aluminum interconnecting and copper interconnecting line on first interlayer dielectric layer, wherein the aluminum interconnecting is used as letter
Number line, the copper interconnecting line are used as power cord, and compared with simple copper interconnection structure, the mixing interconnection structure has on the whole
Low resistance, while electromigration reliability does not also decline.
2. according to the method described in claim 1, it is characterized in that, being respectively formed aluminium interconnection on first interlayer dielectric layer
Line and copper interconnecting line include：
Etch first interlayer dielectric layer, in first interlayer dielectric layer formed copper-connection through-hole and aluminium it is intercommunicated
Hole；
Aluminum metal layer in the copper-connection through-hole and the aluminium through-hole interconnection and on first interlayer dielectric layer；
The aluminum metal layer is etched, to form the aluminum interconnecting；
The deposited sacrificial layer on first interlayer dielectric layer and the aluminum interconnecting；
The sacrificial layer is etched, to form copper interconnection groove in the sacrificial layer；
The deposited copper metal layer in the copper interconnection groove, to form copper interconnecting line；And
The sacrificial layer is removed, with the exposure copper interconnecting line and the aluminum interconnecting.
3. according to the method described in claim 2, it is characterized in that, the method further includes：
After removing the sacrificial layer, at the top and side wall deposition diffusion barrier of the copper interconnecting line and the aluminum interconnecting
Layer.
4. according to the method described in claim 3, it is characterized in that, the material of the diffusion impervious layer is graphene.
5. according to the method described in claim 3, it is characterized in that, depositing the diffusion impervious layer using laser writing technology.
6. according to the method described in claim 3, it is characterized in that, the method further includes：Depositing the diffusion resistance
After barrier, the second interlayer dielectric layer is deposited on the diffusion impervious layer.
7. a kind of mixing interconnection structure of manufacturing method manufacture according to one of claim 1-6.
8. a kind of electronic device, including the mixing interconnection structure described in claim 7.
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| CN117888076B (en) * | 2023-12-28 | 2024-10-18 | 苏州海思利福生物医疗科技有限公司 | Hot wire for thermal conductivity detector and preparation method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777320B1 (en) * | 1998-11-13 | 2004-08-17 | Intel Corporation | In-plane on-chip decoupling capacitors and method for making same |
| CN1815728A (en) * | 2005-01-14 | 2006-08-09 | 恩益禧电子股份有限公司 | Semiconductor device, and method for manufacturing the same |
| US7199472B2 (en) * | 2002-09-20 | 2007-04-03 | Hitachi, Ltd. | Semiconductor device |
| CN1945817A (en) * | 2005-10-07 | 2007-04-11 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method thereof |
| CN101383333A (en) * | 2007-09-05 | 2009-03-11 | 台湾积体电路制造股份有限公司 | semiconductor packaging |
-
2014
- 2014-10-13 CN CN201410537822.3A patent/CN105575944B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777320B1 (en) * | 1998-11-13 | 2004-08-17 | Intel Corporation | In-plane on-chip decoupling capacitors and method for making same |
| US7199472B2 (en) * | 2002-09-20 | 2007-04-03 | Hitachi, Ltd. | Semiconductor device |
| CN1815728A (en) * | 2005-01-14 | 2006-08-09 | 恩益禧电子股份有限公司 | Semiconductor device, and method for manufacturing the same |
| CN1945817A (en) * | 2005-10-07 | 2007-04-11 | 株式会社瑞萨科技 | Semiconductor device and manufacturing method thereof |
| CN101383333A (en) * | 2007-09-05 | 2009-03-11 | 台湾积体电路制造股份有限公司 | semiconductor packaging |
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