CN105573856A - Method for solving instruction reading error problem - Google Patents
Method for solving instruction reading error problem Download PDFInfo
- Publication number
- CN105573856A CN105573856A CN201610046651.3A CN201610046651A CN105573856A CN 105573856 A CN105573856 A CN 105573856A CN 201610046651 A CN201610046651 A CN 201610046651A CN 105573856 A CN105573856 A CN 105573856A
- Authority
- CN
- China
- Prior art keywords
- instruction
- command
- wave filter
- abnormal problem
- fetch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Abstract
The invention discloses a method for solving an instruction reading error problem. The method is characterized in that when an instruction is read, a processor continuously reads the instruction for N times and compares the instructions of the N times, and if comparison is consistent, the instruction is decoded and executed. The method avoids the situation that when the processor obtains the instruction, due to outside interference and other factors, 0/1 errors happen to a certain bit or certain bits in the instruction, and loses instructions incorrectly read under error conditions through two or more times of reading of the instructions at the same address and pre-and-post consistency comparison of bits.
Description
Technical field
The invention belongs to integrated circuit (IC) design field, particularly the disposal route of instruction fetch abnormal problem in processor application process.
Background technology
Often can occur in the processor application process of reality owing to causing program from instruction fetch error in data when program's memory space instruction fetch from the fluctuation of power supply.Especially electrostatic (ESD) event under electric fast transient/pulse train (EFT) event or duty, robustness due to program storage itself will be starkly lower than the robustness of digital logic unit, thus causes instruction fetch mistake.
As patented claim 201210577051.1 discloses a kind of method of debugging central processing unit and crashing, the system using described debugging central processing unit to crash, comprising: open the first central processing unit; The counter of the first central processing unit counts down; When described counter counts counts to zero, reset module and notify that described counter resets; Described replacement module judges whether described counter completes replacement, if complete replacement, illustrate that described first central processing unit normally runs, if do not complete replacement, illustrate that described first central processing unit is abnormal to crash, then described replacement module sends an enabled instruction to one second central processing unit; After receiving described enabled instruction, the second central processing unit is debugged described first central processing unit.The method is the method process by resetting, and this understands treatment effeciency and the speed of delay disposal device greatly, affects the normal operation of equipment.
Summary of the invention
For solving the problem, the object of the present invention is to provide a kind of method solving instruction fetch abnormal problem, this method avoid certain bit in instruction fetch process because in the instruction that causes of the factor such as external disturbance of processor or 0/1 mistake appears in certain several bit, ensure the correctness of reading command.
The object of the present invention is to provide a kind of method solving instruction fetch abnormal problem, the method can be verified reading command rapidly, and realizes easy, with low cost.
The method solving instruction fetch abnormal problem is that processor reads a N instruction from identical address continuously, and the bit of N instruction is under normal circumstances on all four.But some bit once or in certain instruction several times of certain in an abnormal situation, in N instruction there will be 0/1 mistake.
Under the circumstances, for achieving the above object, technical scheme of the present invention is as follows.
A kind of method solving instruction fetch abnormal problem, it is characterized in that in the process of reading command, processor reads N instruction (N >=2) continuously, compares N instruction, if when more consistent, this instruction is carried out to the execution of decoding and instruction.
Described N instruction to be compared, be by instruction wave filter by carrying out filtering to N the same instructions of getting, judge which bar is only correct instruction and performs.
Further, instruction wave filter is by carrying out filtering to N the same instructions of getting, if more inconsistent, and number of times inconsistent is continuously no more than L time (L >=2), processor falls clearly original instruction of reading, and returns and again carries out instruction fetch from program storage;
If more inconsistent, and number of times inconsistent is continuously more than L time (L >=2), processor can report an error, and carry out subsequent treatment according to the applicable cases of reality, such as program stopped perform and by again reading this instruction etc. again after pin misdirection or the standby certain hour of program.
Instruction wave filter can pass through accomplished in many ways.Instruction wave filter finally judges that N time needed for right instructions is not fixing, depends on that instruction wave filter judges the time of right instructions.But instruction wave filter has one minimumly to set up number M, and M depends on the structure of instruction wave filter, and is more than or equal to 2.
The simplest instruction wave filter of one can realize like this.This wave filter M=2, instruction is L bit, and two instructions of successively getting are respectively M1, M2.
M1 and M2, by bit comparison, if comparative result is identical, carries out decoding and execution to command M 2.If not identical, get the 3rd article of command M 3, M2 and M3 by bit comparison, if comparative result is identical, decoding and execution are carried out to command M 3.If not identical, get the 4th article of command M 4, M3 and M4 by bit comparison, if comparative result is identical, decoding and execution are carried out to M4.By that analogy.After this instruction correctly performs, from next address reading command, by instruction wave filter, filtering is carried out to next instruction.By that analogy, the structures shape processor jamproof robustness of instruction wave filter.
This method avoids certain bit in instruction fetch process because in the instruction that causes of the factor such as external disturbance of processor or 0/1 mistake appears in certain several bit, by reading and the contrast of bit self-consistentency of 2 times and above identical address instruction, thus the incorrect instruction of reading under losing exception condition.
Accompanying drawing explanation
Fig. 1 is the system control process figure that the present invention implements.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
As shown in Figure 1, realize by the present invention the major control process flow diagram of the method solving instruction fetch abnormal problem, shown in figure, the method that the present invention implements is in the process of reading command, processor reads N instruction (N >=2) continuously, N instruction is compared, if more consistent when, this instruction is carried out to the execution of decoding and instruction.
Specifically, N instruction is compared, be pass through to carry out filtering to N the same instructions of getting by instruction wave filter, judge which bar is only correct instruction and performs.
Instruction wave filter is by carrying out filtering to N the same instructions of getting, if more inconsistent, and number of times inconsistent is continuously no more than L time (L >=2), and processor falls clearly original instruction of reading, and returns and again carries out instruction fetch from program storage;
If more inconsistent, and number of times inconsistent is continuously more than L time, processor can report an error, and carries out subsequent treatment according to the applicable cases of reality, such as program stopped perform and by again reading this instruction etc. again after pin misdirection or the standby certain hour of program.
Such as: instruction wave filter M=2, instruction is L bit, and two instructions of successively getting are respectively M1, M2.
M1 and M2, by bit comparison, if comparative result is identical, carries out decoding and execution to command M 2.If not identical, get the 3rd article of command M 3, M2 and M3 by bit comparison, if comparative result is identical, decoding and execution are carried out to command M 3.If not identical, get the 4th article of command M 4, M3 and M4 by bit comparison, if comparative result is identical, decoding and execution are carried out to M4.By that analogy.After this instruction correctly performs, from next address reading command, by instruction wave filter, filtering is carried out to next instruction.By that analogy, the structures shape processor jamproof robustness of instruction wave filter.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. solve a method for instruction fetch abnormal problem, it is characterized in that in the process of reading command, processor reads N instruction continuously, compares N instruction, if more consistent when, this instruction is carried out to the execution of decoding and instruction.
2. the as claimed in claim 1 method solving instruction fetch abnormal problem, it is characterized in that describedly comparing N instruction, be pass through to carry out filtering to N the same instructions of getting by instruction wave filter, judgement is that correct instruction just performs.
3. the method solving instruction fetch abnormal problem as claimed in claim 2, is characterized in that described N command N >=2.
4. the method solving instruction fetch abnormal problem as claimed in claim 2, it is characterized in that instruction wave filter is by carrying out filtering to N the same instructions of getting, if more inconsistent, and number of times inconsistent is continuously no more than L time, processor falls clearly original instruction of reading, and returns and again carries out instruction fetch from program storage;
If more inconsistent, and number of times inconsistent is continuously more than L time, processor can report an error, and carries out subsequent treatment according to the applicable cases of reality, such as program stopped perform and by again reading this instruction etc. again after pin misdirection or the standby certain hour of program.
5. the method solving instruction fetch abnormal problem as claimed in claim 4, is characterized in that described L >=2.
6. the as claimed in claim 2 method solving instruction fetch abnormal problem, it is characterized in that instruction wave filter has one minimumly to set up number M, M depends on the structure of instruction wave filter, and is more than or equal to 2.
7. the method solving instruction fetch abnormal problem as claimed in claim 2, it is characterized in that instruction wave filter M=2, instruction is L bit, and two instructions of successively getting are respectively M1, M2;
M1 and M2, by bit comparison, if comparative result is identical, carries out decoding and execution to command M 2;
If not identical, get the 3rd article of command M 3, M2 and M3 by bit comparison, if comparative result is identical, decoding and execution are carried out to command M 3;
If not identical, get the 4th article of command M 4, M3 and M4 by bit comparison, if comparative result is identical, decoding and execution are carried out to M4, by that analogy, after this instruction correctly performs, from next address reading command, by instruction wave filter, filtering is carried out to next instruction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610046651.3A CN105573856A (en) | 2016-01-22 | 2016-01-22 | Method for solving instruction reading error problem |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610046651.3A CN105573856A (en) | 2016-01-22 | 2016-01-22 | Method for solving instruction reading error problem |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105573856A true CN105573856A (en) | 2016-05-11 |
Family
ID=55884024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610046651.3A Pending CN105573856A (en) | 2016-01-22 | 2016-01-22 | Method for solving instruction reading error problem |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105573856A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101313281A (en) * | 2005-11-18 | 2008-11-26 | 罗伯特·博世有限公司 | Device and method for eliminating errors in a system comprising at least two execution units with registers |
| CN102027482A (en) * | 2008-05-15 | 2011-04-20 | Nxp股份有限公司 | A method for secure data reading and a data handling system |
| CN102541673A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Security processing method and circuit for central processing unit (CPU) fetch instruction abnormity |
| CN103902423A (en) * | 2012-12-26 | 2014-07-02 | 联芯科技有限公司 | Method and system for debugging crash of central processor |
-
2016
- 2016-01-22 CN CN201610046651.3A patent/CN105573856A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101313281A (en) * | 2005-11-18 | 2008-11-26 | 罗伯特·博世有限公司 | Device and method for eliminating errors in a system comprising at least two execution units with registers |
| CN102027482A (en) * | 2008-05-15 | 2011-04-20 | Nxp股份有限公司 | A method for secure data reading and a data handling system |
| CN102541673A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Security processing method and circuit for central processing unit (CPU) fetch instruction abnormity |
| CN103902423A (en) * | 2012-12-26 | 2014-07-02 | 联芯科技有限公司 | Method and system for debugging crash of central processor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101606289B1 (en) | Programmable controller | |
| CN102831028B (en) | Based on ECC error correction method and the system of data bus | |
| CN104123167B (en) | MCU method for energizing and starting and its self checking method with configuration words self-checking function | |
| US20180101304A1 (en) | Configuration control system and configuration control method | |
| CN104579313A (en) | A fault detection and repair method for on-orbit SRAM FPGA based on configuration frame | |
| CN107704067A (en) | A kind of SoC chip repositioning method and reset system | |
| KR101667400B1 (en) | Apparatus and method for generating and detecting single event upset | |
| CN108027780A (en) | A memory content protection circuit | |
| JP6290934B2 (en) | Programmable device, error holding system, and electronic system apparatus | |
| US9400708B2 (en) | Integrated circuit and method of detecting a data integrity error | |
| CN103810051A (en) | Watchdog abnormity recovery device and method | |
| CN103092717A (en) | Flash memory data processing method and device | |
| CN103257905B (en) | A kind of embedded computer system internal storage data checking circuit and method | |
| CN104597807A (en) | Space-borne integrated electronic CPU (central processing unit) turnover reinforcement system and method | |
| CN105573856A (en) | Method for solving instruction reading error problem | |
| CN104484260A (en) | Simulation monitoring circuit based on GJB289 bus interface SoC (system on a chip) | |
| CN103577154B (en) | Based on the interpretation method of the instruction of ARINC659 agreement | |
| CN103577155B (en) | Based on the implementation method of the instruction decoding circuit of ARINC659 agreement | |
| US11847077B2 (en) | Serial peripheral interface integrated circuit and operation method thereof | |
| CN105183676A (en) | Memory write protection system and method | |
| CN104914784A (en) | Numerical controller | |
| Carvalho et al. | Enhancing I2C robustness to soft errors | |
| US10031825B2 (en) | Electronic device having multiplexed input/output terminals | |
| CN107291639A (en) | It is a kind of to improve the method and apparatus that bus reads and writes stability | |
| CN103034558A (en) | Controller of Power PC (Personal Computer) system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160511 |