CN105571749A - Forming method of pressure sensor - Google Patents
Forming method of pressure sensor Download PDFInfo
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- CN105571749A CN105571749A CN201410545227.4A CN201410545227A CN105571749A CN 105571749 A CN105571749 A CN 105571749A CN 201410545227 A CN201410545227 A CN 201410545227A CN 105571749 A CN105571749 A CN 105571749A
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Abstract
The provided invention provides a forming method for a pressure sensor. The forming method comprises: a first semiconductor substrate is provided; an insulating layer covering the surface of the first semiconductor substrate and a substrate layer covering the surface of the insulating layer are formed; a device layer covering the surface of the substrate layer is formed, wherein a piezoresistive structure is formed in the device layer; a dielectric layer covering the device layer is formed; a protection layer covering the surface of the dielectric layer is formed, wherein a connecting zone is formed in the protection layer; a first groove penetrating the protection layer and the dielectric layer is formed, wherein the part of surface of the piezoresistive structure is exposed by the first groove; a second semiconductor substrate having a connecting surface is provided, wherein a second groove is formed in the surface of the connecting surface; the connecting zone and the connecting surface are bonded and connected to form a cavity; and the first semiconductor substrate is removed to expose the insulating layer. With the method, the production cost of the pressure sensor can be lowered.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of pressure transducer formation method.
Background technology
Pressure transducer is based on MEMS (micro electro mechanical system) (MicroElectroMechanicalSystem, MEMS) microdevice grown up, it is a kind of sensor the most conventional in industrial practice, instrument and meter control, also be widely used in various industrial automatic control environment, relate to numerous industries such as water conservancy and hydropower, railway traffic, production automatic control, Aero-Space, military project, petrochemical industry, oil well, electric power, boats and ships, lathe, pipeline.It integrate microsensor, actuator and signal transacting with control circuit, interface circuit, communicate and power supply, based on semiconductor fabrication, manufacturing process and integrated circuit technique are compatible.Pressure transducer of a great variety, as resistance strain gage pressure transducer, semiconductor gauge pressure transducer, piezoresistive pressure sensor, inductance pressure transducer, capacitance pressure transducer, resonance type pressure sensor and capacitance acceleration transducer etc.
Piezoresistive pressure sensor, has high precision and good linear characteristic, gains great popularity in the use of pressure transducer.Usually, piezoresistive pressure sensor has the film of deflection, for this film provides the cavity of deflection space, film deflection deformation can be caused when described film experiences external pressure change, change the resistivity of membraneous material, thus by measuring the resistance variations of film, linear relationship can be set up with external pressure.Described pressure transducer has higher quality requirements to cavity, usually adopts cavity-silicon-on-insulator as substrate, there is problem with high costs.
Summary of the invention
The problem that the present invention solves is, by providing a kind of formation method of pressure transducer, reducing manufacturing cost, meeting device quality requirement simultaneously.
For solving the problem, the invention provides a kind of pressure transducer formation method, comprising: the first Semiconductor substrate is provided; Form the insulation course covering described first semiconductor substrate surface and the substrate layer covering described surface of insulating layer; Form the device layer covering described substrate layer surface, in described device layer, be formed with pressure drag structure; Form the dielectric layer covering described device layer; Form the protective seam covering described dielectric layer surface, be formed with bonding pad in described protective seam, described bonding pad end face flushes with protective layer, and the projection of bonding pad on device layer is positioned at pressure drag structural perimeter position; Form the first groove running through described protective seam and dielectric layer, described first groove exposes pressure drag structure division surface; There is provided second Semiconductor substrate with connecting surface, described connecting surface is formed with the second groove, and described second grooved position is corresponding with the first grooved position; Bonding connects described bonding pad and connecting surface, forms cavity; Remove the first Semiconductor substrate, expose insulation course.
Optionally, described insulation course is monox, and thickness is 1 micron ~ 5 microns.
Optionally, described substrate layer is silicon or germanium, and the technique forming described substrate layer is epitaxial growth, and technological temperature is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas is silicon source gas SiH
4or SiH
2cl
2, or germanium source gas GeH
4, the flow of described silicon source gas or germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
Optionally, the transistor being positioned at pressure drag structural perimeter position is also formed with in described device layer.
Optionally, be formed with interconnection structure in described dielectric layer, described interconnection structure runs through dielectric layer and is connected with described pressure drag structure and transistor, is positioned at pressure drag structural edge region with the interconnection structure of pressure drag anatomical connectivity.
Optionally, described protective seam is the insulating material of thickness 100nm ~ 5000nm, and described insulating material is the low k-value material of monox, silicon nitride, silicon oxynitride, silicon oxide carbide or specific inductive capacity 2.0 ~ 4.0.
Optionally, the material of described bonding pad is metallic copper, aluminium, nickel etc., is suitable for being connected with the connecting surface bonding of the second Semiconductor substrate.
Optionally, the technique forming described first groove is dry etching, and the etching gas of described dry etching comprises CF
4, CH
3f, CH
2f
2, CHF
3, SF
6, NF
3, SO
2, H
2, O
2, N
2, in Ar and He one or more, the flow of etching gas is 50 mark condition milliliter per minute ~ 600 mark condition milliliter per minutes, and bias voltage is 100V ~ 500V, and power is 200W ~ 600W, and temperature is 40 DEG C ~ 70 DEG C.
Optionally, the sectional width of described first groove is less than the sectional width of pressure drag structure, the horizontal range of an one lateral edges lateral edges corresponding to pressure drag structure of the first groove is 200nm ~ 2000nm, is suitable for avoiding the interconnection structure to being connected to pressure drag structural edge to cause damage.
Optionally, the technique forming described second groove is dry etching, and the etching gas of described dry etching comprises HBr, Cl
2, SF
6, NF
3, O
2, Ar, He, CH
2f
2and CHF
3in one or more, the flow of etching gas is 50 mark condition milliliter per minute ~ 500 mark condition milliliter per minutes, and bias voltage is 100V ~ 650V, and power is 200W ~ 600W, and temperature is 40 DEG C ~ 70 DEG C.
Optionally, the degree of depth of described second groove is 500nm ~ 10000nm, and the sectional width of the second groove is greater than the sectional width of the first groove.
Optionally, the bonding Joining Technology of described bonding pad and connecting surface is that metal is diffusion interlinked, and bonding temperature is 300 DEG C ~ 400 DEG C, the second Semiconductor substrate is applied to the pressure of 5,000 Ns ~ 100,000 Ns simultaneously.
Optionally, described metal is diffusion interlinked to be completed under vacuum conditions, is vacuum in described cavity.
Optionally, the technique of described removal first Semiconductor substrate is chemically mechanical polishing, wet etching or dry etching.
Optionally, described first Semiconductor substrate is silicon substrate or germanium substrate, and the first Semiconductor substrate is not adulterated, and is suitable for insulation course, substrate layer, device layer provide physical support.
Optionally, the material of described dielectric layer is the low k-value material of specific inductive capacity 2.0 ~ 4.0 or the ultra low k material of specific inductive capacity <2.0.
Optionally, the material of described interconnection structure is copper, aluminium, nickel or tungsten, and formation process is physical vapour deposition (PVD) or electrochemical deposition.
Optionally, the top dimension of described interconnection structure section is greater than bottom size.
Optionally, the top dimension of described first trench profile is greater than, is equal to or less than bottom size.
Compared with prior art, technical scheme of the present invention has the following advantages:
In pressure transducer formation method provided by the invention; first Semiconductor substrate forms insulation course and substrate layer successively; on substrate layer, form the device layer comprising pressure drag structure and some transistors again, and covering device layer forms dielectric layer and protective seam successively.Form the epitaxial growth that described substrate layer adopts, its technical maturity, cheap for manufacturing cost, the insulation course of acquisition and substrate layer also can meet the request for utilization of device layer, thus when not sacrificing device function, greatly save production cost.
Further; in technical solution of the present invention; the first groove is formed at pressure drag superstructure by etch-protecting layer and dielectric layer; described first groove forms cavity with the second follow-up groove after bonding is connected; described cavity can bend provide activity space by external pressure effect for pressure drag structure; compared with cavity-silicon-on-insulator, device can be made to obtain identical function and effect, and the process costs forming described cavity is than directly using the cost of cavity-silicon-on-insulator greatly to reduce.
Further, in technical solution of the present invention, by removing the first Semiconductor substrate to expose insulation course, the partial insulative layer corresponding with empty cavity position, portions of substrate layer and part thereof structure define flexible films, the process of described formation flexible films is simple, low cost of manufacture.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the pressure transducer of one embodiment of the invention;
Fig. 2 to Fig. 9 is the cross-sectional view of the pressure transducer formation procedure of another embodiment of the present invention.
Embodiment
From background technology, in the prior art, pressure transducer has higher quality requirements to cavity, usually adopts cavity-silicon-on-insulator as substrate, there is problem with high costs.
In order to further illustrate, the invention provides the embodiment of a pressure sensor structure, please refer to Fig. 1, comprising:
Basalis 10, described basalis 10 surface is formed with cavity 13, and described cavity 13 end face flushes with basalis 10 surface;
Be positioned at the insulation course 11 on described basalis 10 surface;
Be positioned at the device layer 12 on described insulation course 11 surface, be formed with pressure drag structure 14 and the transistor 15 being positioned at described pressure drag structure 14 peripheral position in described device layer 12, described pressure drag structure 14 is positioned at above cavity 13;
Be positioned at the dielectric layer 18 on described device layer 12 surface, be formed in described dielectric layer 18 and run through dielectric layer 18 and the interconnection structure 16 be connected with pressure drag structure 14 and transistor 15;
Be positioned at the groove 17 of described dielectric layer 18, described groove 17 is positioned at above pressure drag structure 14, and exposes device layer 12 part surface.
Described basalis 10 is silicon substrate or germanium substrate, is suitable for follow-up insulation course 11 and device layer 12 provides physical support.Be airtight vacuum in described cavity 13.
Described insulation course 11 is monox, is suitable for making subsequent device layer 12 produce raceway groove depletion effect, simultaneously for follow-up pressure drag structure 14 provides physical support, makes it being unlikely to rupture by during external pressure effect deflection deformation.
Described pressure drag structure 14 can bend under external pressure, and its resistivity and resistance value also can change, and just can set up by the change of measured resistance value the relation changed with external pressure, indirectly obtains the situation of external pressure change.
Described transistor 15 and pressure drag structure 14 co-operation are to form the pressure sensitive device of complex function, wherein transistor 15 can be the control circuit of pressure drag structure 14, also can input for pressure drag structure 14, export and memory circuit complete computing, also can be power amplifying device, be suitable for the output signal optimizing pressure drag structure 14.
Described interconnection structure 16 end face flushes with dielectric layer 18 surface, interconnection structure 16 for transistor 15 electric signal is provided and receiving feedback signals to complete device function, simultaneously also for pressure drag structure 14 provides electric signal with measuring resistance.The interconnection structure 16 be connected with pressure drag structure 14 is positioned at pressure drag structural edge region.
The partial insulative layer 11 corresponding with cavity 13 position and part thereof structure 14 define the flexible films of pressure sensor structure.Described flexible films can bend under the effect of external pressure, and the pressure drag structure 14 in flexible films is also bent, thus changes the resistance value of pressure drag structure 14, just can be obtained the change of corresponding external pressure by the change of measuring its resistance value.
Carry out research to above-described embodiment to find, when forming described pressure transducer, the method covering basalis 10 surface formation insulation course 11 mostly is physical vapour deposition (PVD) or chemical vapor deposition, in insulation course 11 poor flatness formed with cavity 13 corresponding position, thickness uniformity is low, even easily occur to the collapse-deformation in cavity 13, cause the pressure drag structure poor flatness of follow-up formation, uniformity coefficient is low even lost efficacy.Described collapse-deformation also greatly reduces the volume of cavity 13 simultaneously, is unfavorable for the flexure activity of pressure drag structure, reduces the accuracy of device induction pressure.The insulation course 11 that flatness is good in order to obtain, thickness uniformity is high and pressure drag structure 14, the silicon-on-insulator that adopts manufactures described pressure transducer more at present.Described silicon-on-insulator is generally divided into three layers, comprise substrate silicon layer, be positioned at the silicon oxide layer of substrate silicon surface and be positioned at the substrate silicon layer on silicon oxide layer surface, wherein substrate silicon layer can as the basalis 10 in Fig. 1, silicon oxide layer as the insulation course 11 in Fig. 1, can form transistor and the pressure drag structure also further device layer 12 obtained in Fig. 1 on substrate silicon layer surface.In actual applications, a kind of method adopts cavity-silicon-on-insulator, and described cavity-silicon-on-insulator has been pre-formed cavity between substrate silicon layer and silicon oxide layer, only need manufacture device layer in corresponding region, substrate silicon layer surface and complete subsequent technique.But the cost of described cavity-silicon-on-insulator is too high, and the parameters such as preformed empty cavity position, size, the degree of depth are that manufacturer provides, and cannot meet changeable chip design demand, have significant limitation in actual applications.Another kind method is, general wafer is provided and its surface formed needed for groove; Reoffer silicon-on-insulator wafer, thinning back side is carried out to remove substrate silicon layer and to expose silicon oxide layer to it; Connect the silicon oxide layer surface that described general wafer forms fluted surface and silicon-on-insulator, obtain required cavity.But the conventional silicon-on-insulator cost in described method is also higher, the stability of Joining Technology is not high and easily occur defect and flaw, can cause negative effect to device.
For solving the problem; the invention provides a kind of embodiment of pressure transducer formation method; first Semiconductor substrate forms insulation course and substrate layer successively; on substrate layer, form the device layer comprising pressure drag structure and some transistors again, and covering device layer forms dielectric layer and protective seam successively.Form the epitaxial growth that described substrate layer adopts, its technical maturity, cheap for manufacturing cost, the insulation course of acquisition and substrate layer also can meet the user demand of device layer, thus when not sacrificing device function, greatly save production cost.The first groove is formed at pressure drag superstructure by etch-protecting layer and dielectric layer; described first groove forms cavity with the second follow-up groove after bonding is connected; described cavity can bend provide activity space by external pressure effect for pressure drag structure; compared with cavity-silicon-on-insulator; device can be made to obtain identical function and effect, and the process costs forming described cavity reduce greatly than the cost directly buying cavity-silicon-on-insulator.And by removal first Semiconductor substrate to expose insulation course, the partial insulative layer corresponding with empty cavity position, portions of substrate layer and part thereof structure define flexible films, the process of described formation flexible films is simple, low cost of manufacture.
For enabling above-mentioned purpose, the feature and advantage of this method more become apparent, be described in detail below in conjunction with the embodiment of accompanying drawing to this method.When describing the embodiment of the present invention in detail, for ease of illustrating, schematic diagram can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, and it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
With reference to figure 2, provide the first Semiconductor substrate 100.
Described first Semiconductor substrate 100 is silicon substrate or germanium substrate, and the first Semiconductor substrate 100 is not adulterated, and is suitable for insulation course 101, substrate layer 100a, device layer 102 and subsequent technique and provides physical support.
Please continue to refer to Fig. 2, form the insulation course 101 covering described first Semiconductor substrate 100 surface and the substrate layer 100a covering described insulation course 101 surface.
Described insulation course 101 is monox, and thickness is 1 micron ~ 5 microns, and insulation course 101 technique forming monox is thermal oxide, physical vapour deposition (PVD) or ald.
Described insulation course 101 is suitable for isolating device layer 102 and produces raceway groove depletion effect, and fine and close silica material can better improve device performance, in the present embodiment, take insulation course 101 as the situation of dense oxide silicon, the explanation of presenting a demonstration property.As an embodiment, insulation course 101 formation process of described dense oxide silicon is ald.Described ald comprises the following steps: A, in reaction chamber, pass into SiCl
4gas, at first Semiconductor substrate 100 surface deposition one deck SiCl
4after, take out the remaining SiCl in reaction chamber
4gas; B, in reaction chamber, pass into water vapor, form SiCl with the first Semiconductor substrate 100 surface
4reaction takes out the residual water vapor in reaction chamber after generating one deck monox; To steps A and B carry out N time circulation, N be greater than 1 integer, until obtain the insulating layer of silicon oxide 101 of 1 micron ~ 5 microns.The insulating layer of silicon oxide 101 that described ald is formed, finer and close compared with the monox deposited with methods such as physical vapour deposition (PVD)s, the lattice mismatch of its lattice parameter and silicon crystal lattices parameter is less, be conducive to subsequently epitaxial growing crystalline silicon, insulation course 101 is also the supporting layer of pressure drag structure 104 simultaneously, and pressure drag structure 104 can be avoided to rupture when bending.
Described thickness of insulating layer adopts 1 micron ~ 5 microns, if thickness is too thin, does not only have the effect of effective isolating device layer 102, also cannot provide enough anchorage forces to pressure drag structure 104; If thickness is too thick, although can effective isolating device layer 102, the deflection deformation of pressure drag structure 104 can be hindered, cause device sensitivity to decline.
Described substrate layer 100a is crystalline silicon, as an embodiment, described substrate layer 100a can by being formed at the surperficial epitaxial growth crystal silicon of insulation course 101, the epitaxial growth technology of the substrate layer 100a of described formation crystalline silicon, technological temperature is 500 DEG C ~ 800 DEG C, air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas is silicon source gas SiH
4or SiH
2cl
2, the flow of described silicon source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.Described epitaxially grown method, insulating layer of silicon oxide 101 superficial growth that can obtain at described ald obtains required crystalline silicon substrate layer 100a, and described crystalline silicon substrate layer 100a can meet the follow-up requirement preparing transistor device.It should be noted that, the transition bed of certain thickness monox-crystalline silicon can be there is near the interface of insulation course 101 and substrate layer 100a, but described transition bed exists only near the interface of insulation course 101 and substrate layer 100a, do not affect and utilize substrate layer 100a to prepare transistor device.
The insulation course 101 adopting the present embodiment method to be formed and substrate layer 100a, with low cost compared with silicon-on-insulator, insulation course 101 and substrate layer 100a also can meet the request for utilization of subsequent device layer 102 simultaneously, thus when not sacrificing device function, greatly save production cost.
Please continue to refer to Fig. 2, form the device layer 102 covering described substrate layer 100a surface, in described device layer 102, be formed with pressure drag structure.
Can also be formed with the transistor being positioned at described pressure drag structure 104 peripheral position in described device layer 102, in the present embodiment, comprise the situation of described pressure drag structure 104 and transistor 103 for device layer 102, presenting a demonstration property illustrates, please refer to Fig. 2.
Described pressure drag structure 104 comprises the separation layer being positioned at substrate layer 100a surface and the piezoresistance layer being positioned at described insulation surface, and described separation layer and piezoresistance layer are not shown in Figure 2.
Described insolated layer materials can be silicon nitride, monox, silicon oxynitride or silicon oxide carbide, and separation layer is suitable for isolation piezoresistance layer and substrate layer 100a, avoids substrate layer 100a to affect the resistance value of piezoresistance layer material.Described piezoresistance layer material is polysilicon, and the technique forming described piezoresistance layer is epitaxial growth.When pressure drag structure 104 is by external pressure deflection deformation, described piezoresistance layer is deflection deformation thereupon also, the resistivity of piezoresistance layer and resistance value all can change, and just can set up by the change of measured resistance value the relation changed with external pressure, indirectly obtain the situation of external pressure change.
The step forming described device layer 102 comprises: form transistor 103 and pressure drag structure 104 on substrate layer 100a surface; Form the device medium layer covering substrate layer 100a surface, transistor 103 and pressure drag structure 104, described device medium layer is not shown in Figure 2; Chemically mechanical polishing is carried out to described device medium layer until expose transistor 103 and pressure drag structure 104 surface.Described device medium layer is silica material, and formation process is chemical vapor deposition, physical vapour deposition (PVD) or ald.
Described transistor 103 and pressure drag structure 104 co-operation are to form the pressure sensitive device of complex function, wherein transistor 103 can as the control circuit of pressure drag structure 104, also can be pressure drag structure 104 input and output signal, storage information complete some simple operations, simultaneously can also as the output signal in order to optimize pressure drag structure 104 such as power amplifying device.
With reference to figure 3, form the dielectric layer 106 covering described device layer 102.
Interconnection structure can also be formed with, in the present embodiment, to be formed with the situation of interconnection structure 105 in dielectric layer 106, the explanation of presenting a demonstration property in described dielectric layer 106.Described interconnection structure 105 runs through dielectric layer 106 and is connected with pressure drag structure 104 and transistor 103, and the interconnection structure 105 be connected with pressure drag structure 104 is positioned at pressure drag structural edge region.
The material of described dielectric layer 106 is the low k-value material of specific inductive capacity 2.0 ~ 4.0 or the ultra low k material of specific inductive capacity <2.0, as an embodiment, the low k-value material of described specific inductive capacity 2.0 ~ 4.0 is organic polymer, amorphous chlorination carbon, include organic polymer Silicon On Insulator, be doped with the Si oxide of carbon or be doped with the Si oxide of chlorine.
The material of described interconnection structure 105 is copper, aluminium, nickel or tungsten, and formation process is physical vapour deposition (PVD) or electrochemical deposition.
The described interconnection structure 105 be connected with pressure drag structure 104 is positioned at the fringe region of pressure drag structure 104, and link position is also at the edge of pressure drag structure 104, and the Edge Distance of described link position side corresponding to pressure drag structure 104 is 100nm ~ 1000nm.The position distribution of described interconnection structure 105, be the upper dielectric layer 106 in order to reserve pressure drag structure 104 central area, rear extended meeting forms groove and exposes pressure drag structure 104 part surface above pressure drag structure 104 central area.The interconnection structure 105 be connected with pressure drag structure 104, its link position side corresponding to pressure drag structure 104 Edge Distance 100nm ~ 1000nm, object ensures that the interconnection structure 105 of this part stablely can be connected with pressure drag structure 104, not to occur position deviation, thus the unnecessary fluctuation of pressure drag structure 104 resistance value that reduction is measured.
In the present embodiment, the top dimension of described interconnection structure 105 section is greater than bottom size, its reason is: interconnection structure 105 needs to connect each transistor 103 and pressure drag structure 104 exactly, will avoid producing large stray capacitance, therefore the section bottom size of interconnection structure 105 is less simultaneously; And after transistor 103 and pressure drag structure 104 are connected to upper strata, stray capacitance herein can not produce large impact to device, the continuation simultaneously for the ease of subsequent technique connects, and therefore the profile top size of interconnection structure 105 is larger.In the present embodiment, with the section shape of interconnection structure 105 for below rectangle and presenting a demonstration property of the situation explanation being positioned at the top rectangle stacked combination on the rectangle of below, wherein the sectional width of top rectangle is greater than the sectional width of below rectangle.
As an embodiment, the step forming described interconnection structure 105 comprises: in described dielectric layer 106, etching forms shallow interconnection structure groove; Continue the described shallow interconnection structure groove of etching, form dark interconnection structure groove, described dark interconnection structure trench profile size is less than shallow interconnection structure trench profile size, and dark interconnection structure groove exposes pressure drag structure 104 part surface or transistor 103 part surface; Form the interconnection structure 105 of filling full described shallow interconnection structure groove and dark interconnection structure groove.Described shallow interconnection structure groove and dark interconnection structure groove not shown in Figure 3.The lithographic method of the shallow interconnection structure groove of described formation and dark interconnection structure groove is dry etching, and etching gas comprises CF
4, CH
3f, CH
2f
2, CHF
3, SF
6, NF
3, SO
2, H
2, O
2, N
2, in Ar and He one or more, the flow of etching gas is 10 mark condition milliliter per minute ~ 400 mark condition milliliter per minutes, and bias voltage is 50V ~ 500V, and power is 100W ~ 600W, and temperature is 30 DEG C ~ 70 DEG C.
With reference to figure 4; form the protective seam 107 covering described dielectric layer 106 surface; be formed with bonding pad 108 in described protective seam 107, described bonding pad 108 end face flushes with protective seam 107 surface, and the projection of bonding pad 108 on device layer 102 is positioned at pressure drag structure 104 peripheral position.
Described protective seam 107 is the insulating material of thickness 100nm ~ 5000nm; described insulating material is the low k-value material of monox, silicon nitride, silicon oxynitride, silicon oxide carbide or specific inductive capacity 2.0 ~ 4.0; in the present embodiment; the situation of the low k-value material being specific inductive capacity 2.0 ~ 4.0 for protective seam 107 material, the explanation of presenting a demonstration property.As an embodiment, described low k-value material is organic polymer, amorphous chlorination carbon, include organic polymer Silicon On Insulator, be doped with the Si oxide of carbon or be doped with the Si oxide of chlorine.
The material of described bonding pad 108 is metallic copper, aluminium, nickel etc., is suitable for being connected with the second follow-up Semiconductor substrate bonding, in the present embodiment, and presenting a demonstration property of the situation explanation being aluminium with the material of bonding pad 108.
The step forming described bonding pad 108 comprises: in protective seam 107, dry etching forms bonding pad groove; Plated metal aluminium is until fill full described bonding pad groove.The technique of described plated metal aluminium is physical vapour deposition (PVD), electrochemical deposition or ald.
The projection of described bonding pad 108 on device layer 102 is positioned at pressure drag structure 104 peripheral position, its objective is in order to avoid covering above pressure drag structure 104, thus hinders and follow-uply above pressure drag structure 104, form the first groove.
With reference to figure 5, form the first groove 109 running through described protective seam 107 and dielectric layer 106, described first groove 109 exposes pressure drag structure 104 part surface.
The sectional width of described first groove 109 is less than the sectional width of pressure drag structure 104, the horizontal range of an one lateral edges lateral edges corresponding to pressure drag structure 104 of described first groove 109 is 200nm ~ 2000nm, is suitable for avoiding the interconnection structure 105 to being connected to pressure drag structure 104 edge to cause damage.
The top dimension of the first groove 109 section can be greater than, be equal to or less than bottom size, in the present embodiment, have employed presenting a demonstration property of the situation explanation that top dimension equals bottom size.Described first groove 109 is suitable for jointly forming cavity follow-up with the second groove, is therefore not particularly limited section shape.
The technique forming described first groove 109 is dry etching, and as an embodiment, the etching gas of described dry etching comprises CF
4, CH
3f, CH
2f
2, CHF
3, SF
6, NF
3, SO
2, H
2, O
2, N
2, in Ar and He one or more, the flow of etching gas is 50 mark condition milliliter per minute ~ 600 mark condition milliliter per minutes, and bias voltage is 100V ~ 500V, and power is 200W ~ 600W, and temperature is 40 DEG C ~ 70 DEG C.
With reference to figure 6, provide second Semiconductor substrate 110 with connecting surface 111, described connecting surface 111 is formed with the second groove 112, and described second groove 112 position is corresponding with the first groove 109 position.
Described second Semiconductor substrate 110 is silicon substrate or germanium substrate.
The degree of depth of described second groove 112 is 500nm ~ 10000nm, and the sectional width of the second groove 112 is greater than the sectional width of the first groove 109 (please refer to Fig. 5).After described second groove 112, extended meeting and the first groove 109 form cavity jointly.
The technique forming described second groove 112 is dry etching, and the etching gas of described dry etching comprises HBr, Cl
2, SF
6, NF
3, O
2, Ar, He, CH
2f
2and CHF
3in one or more, the flow of etching gas is 50 mark condition milliliter per minute ~ 500 mark condition milliliter per minutes, and bias voltage is 100V ~ 650V, and power is 200W ~ 600W, and temperature is 40 DEG C ~ 70 DEG C.
With reference to figure 7, bonding connects described bonding pad 108 and connecting surface 111, forms cavity 113.
Be vacuum in described cavity 113, be suitable for pressure drag structure 104 and provide space by external pressure deflection deformation.
The technique that described bonding connects is that metal is diffusion interlinked, thermocompression bonding or metal melting bonding, in the present embodiment, with diffusion interlinked the presenting a demonstration property explanation of metal, the bonding Joining Technology that described metal is diffusion interlinked, bonding temperature is 300 DEG C ~ 400 DEG C, second Semiconductor substrate 110 is applied to the pressure of 5,000 Ns ~ 100,000 Ns, described pressure points to connecting surface 111 simultaneously.Under the described conditions, the aluminium atoms permeating in articulamentum 108 enters the second Semiconductor substrate 110 connecting surface, and form silicon-aluminium transition bed, bonding pad 108 can firmly be connected with connecting surface 111 by described transition bed, and has good impermeability.Bonding connection procedure completes under vacuum conditions, is vacuum in the cavity 113 of formation.
With reference to figure 8, remove the first Semiconductor substrate 100, expose insulation course 101.
The technique removing the first Semiconductor substrate 100 can be chemically mechanical polishing, wet etching or dry etching, in the present embodiment, adopts chemically mechanical polishing to grind the first Semiconductor substrate 100, until expose insulation course 101.
The partial insulative layer 101 corresponding with cavity 113 position, portions of substrate layer 100a and part thereof structure 104 constitute flexible films, can deflection deformation be there is in described flexible films under external pressure P effect, also there is deflection deformation in the piezoresistance layer in pressure drag structure 104, cause resistivity and the resistance change of piezoresistance layer, by measuring the change of described resistance value, just can change with external pressure and set up linear relationship, thus obtain the pressure value of external pressure.
The cavity 103 of described formation, compared with cavity-silicon-on-insulator, can make device obtain identical function and effect, and the process costs forming described cavity 103 reduces greatly than the cost directly buying cavity-silicon-on-insulator.
In removal first Semiconductor substrate 100, after exposing insulation course 101, further comprises formation and run through insulation course 101, substrate layer 100a, device layer 102 and certain media layer 106, and the deep via structure 114 be connected with interconnection structure 105, please refer to Fig. 9.Fig. 9, as cross-sectional view, only depicts a deep via structure 114, and the deep via structure that in reality, each interconnection structure 105 is corresponding with it is interconnected, but not shown in fig .9.
The material of described deep via structure 114 is identical with interconnection structure 105 material, and can be copper, aluminium, nickel or tungsten, formation process be physical vapour deposition (PVD) or electrochemical deposition.Described deep via 114 is convenient to the follow-up electrical connection to transistor 103 and pressure drag structure 104.
To sum up; pressure transducer provided by the invention is formed in embodiment of the method; first Semiconductor substrate forms insulation course and substrate layer successively, then on substrate layer, forms the device layer comprising pressure drag structure and some transistors, and covering device layer forms dielectric layer and protective seam successively.Form the epitaxial growth that described substrate layer adopts, its technical maturity, cheap for manufacturing cost, the insulation course of acquisition and substrate layer also can meet the request for utilization of device layer, thus when not sacrificing device function, greatly save production cost.Further; in the embodiment of the present invention; the first groove is formed at pressure drag superstructure by etch-protecting layer and dielectric layer; described first groove forms cavity with the second follow-up groove after bonding is connected; described cavity can bend provide activity space by external pressure effect for pressure drag structure; compared with cavity-silicon-on-insulator, device can be made to obtain identical function and effect, and the process costs forming described cavity reduce greatly than the cost directly buying cavity-silicon-on-insulator.Further, in the embodiment of the present invention, by removing the first Semiconductor substrate to expose insulation course, the partial insulative layer corresponding with empty cavity position, portions of substrate layer and part thereof structure define flexible films, the process of described formation flexible films is simple, low cost of manufacture.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (19)
1. a pressure transducer formation method, is characterized in that, comprising:
First Semiconductor substrate is provided;
Form the insulation course covering described first semiconductor substrate surface and the substrate layer covering described surface of insulating layer;
Form the device layer covering described substrate layer surface, in described device layer, be formed with pressure drag structure;
Form the dielectric layer covering described device layer;
Form the protective seam covering described dielectric layer surface, be formed with bonding pad in described protective seam, described bonding pad end face flushes with protective layer, and the projection of bonding pad on device layer is positioned at pressure drag structural perimeter position;
Form the first groove running through described protective seam and dielectric layer, described first groove exposes pressure drag structure division surface;
There is provided second Semiconductor substrate with connecting surface, described connecting surface is formed with the second groove, and described second grooved position is corresponding with the first grooved position;
Bonding connects described bonding pad and connecting surface, forms cavity;
Remove the first Semiconductor substrate, expose insulation course.
2. pressure transducer formation method as claimed in claim 1, it is characterized in that, described insulation course is monox, and thickness is 1 micron ~ 5 microns.
3. pressure transducer formation method as claimed in claim 1, it is characterized in that, described substrate layer is silicon or germanium, the technique forming described substrate layer is epitaxial growth, technological temperature is 500 DEG C ~ 800 DEG C, and air pressure is that 1 holder ~ 100 are held in the palm, and reacting gas is silicon source gas SiH
4or SiH
2cl
2, or germanium source gas GeH
4, the flow of described silicon source gas or germanium source gas is 1 mark condition milliliter per minute ~ 1000 mark condition milliliter per minute.
4. pressure transducer formation method as claimed in claim 1, is characterized in that, be also formed with the transistor being positioned at pressure drag structural perimeter position in described device layer.
5. pressure transducer formation method as claimed in claim 1, it is characterized in that, be formed with interconnection structure in described dielectric layer, described interconnection structure runs through dielectric layer and is connected with described pressure drag structure and transistor, is positioned at pressure drag structural edge region with the interconnection structure of pressure drag anatomical connectivity.
6. pressure transducer formation method as claimed in claim 1; it is characterized in that; described protective seam is the insulating material of thickness 100nm ~ 5000nm, and described insulating material is the low k-value material of monox, silicon nitride, silicon oxynitride, silicon oxide carbide or specific inductive capacity 2.0 ~ 4.0.
7. pressure transducer formation method as claimed in claim 6, it is characterized in that, the material of described bonding pad is metallic copper, aluminium, nickel etc., is suitable for being connected with the connecting surface bonding of the second Semiconductor substrate.
8. pressure transducer formation method as claimed in claim 1, it is characterized in that, the technique forming described first groove is dry etching, and the etching gas of described dry etching comprises CF
4, CH
3f, CH
2f
2, CHF
3, SF
6, NF
3, SO
2, H
2, O
2, N
2, in Ar and He one or more, the flow of etching gas is 50 mark condition milliliter per minute ~ 600 mark condition milliliter per minutes, and bias voltage is 100V ~ 500V, and power is 200W ~ 600W, and temperature is 40 DEG C ~ 70 DEG C.
9. pressure transducer formation method as claimed in claim 8, it is characterized in that, the sectional width of described first groove is less than the sectional width of pressure drag structure, the horizontal range of an one lateral edges lateral edges corresponding to pressure drag structure of the first groove is 200nm ~ 2000nm, is suitable for avoiding the interconnection structure to being connected to pressure drag structural edge to cause damage.
10. pressure transducer formation method as claimed in claim 1, it is characterized in that, the technique forming described second groove is dry etching, and the etching gas of described dry etching comprises HBr, Cl
2, SF
6, NF
3, O
2, Ar, He, CH
2f
2and CHF
3in one or more, the flow of etching gas is 50 mark condition milliliter per minute ~ 500 mark condition milliliter per minutes, and bias voltage is 100V ~ 650V, and power is 200W ~ 600W, and temperature is 40 DEG C ~ 70 DEG C.
11. pressure transducer formation methods as claimed in claim 10, is characterized in that, the degree of depth of described second groove is 500nm ~ 10000nm, and the sectional width of the second groove is greater than the sectional width of the first groove.
12. pressure transducer formation methods as claimed in claim 1, it is characterized in that, the bonding Joining Technology of described bonding pad and connecting surface is that metal is diffusion interlinked, and bonding temperature is 300 DEG C ~ 400 DEG C, the second Semiconductor substrate is applied to the pressure of 5,000 Ns ~ 100,000 Ns simultaneously.
13. pressure transducer formation methods as claimed in claim 12, it is characterized in that, described metal is diffusion interlinked to be completed under vacuum conditions, is vacuum in described cavity.
14. pressure transducer formation methods as claimed in claim 1, is characterized in that, the technique of described removal first Semiconductor substrate is chemically mechanical polishing, wet etching or dry etching.
15. pressure transducer formation methods as claimed in claim 1, it is characterized in that, described first Semiconductor substrate is silicon substrate or germanium substrate, and the first Semiconductor substrate is not adulterated, and is suitable for insulation course, substrate layer, device layer provide physical support.
16. pressure transducer formation methods as claimed in claim 1, is characterized in that, the material of described dielectric layer is the low k-value material of specific inductive capacity 2.0 ~ 4.0 or the ultra low k material of specific inductive capacity <2.0.
17. pressure transducer formation methods as claimed in claim 5, is characterized in that, the material of described interconnection structure is copper, aluminium, nickel or tungsten, and formation process is physical vapour deposition (PVD) or electrochemical deposition.
18. pressure transducer formation methods as claimed in claim 17, it is characterized in that, the top dimension of described interconnection structure section is greater than bottom size.
19. pressure transducer formation methods as claimed in claim 1, it is characterized in that, the top dimension of described first trench profile is greater than, is equal to or less than bottom size.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107764459A (en) * | 2016-08-17 | 2018-03-06 | 苏州明皜传感科技有限公司 | Pressure sensor and its manufacture method |
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| CN105571749B (en) | 2018-09-07 |
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