CN105552063A - System in a package (SIP) structure - Google Patents
System in a package (SIP) structure Download PDFInfo
- Publication number
- CN105552063A CN105552063A CN201610076112.4A CN201610076112A CN105552063A CN 105552063 A CN105552063 A CN 105552063A CN 201610076112 A CN201610076112 A CN 201610076112A CN 105552063 A CN105552063 A CN 105552063A
- Authority
- CN
- China
- Prior art keywords
- chip
- metal
- metal leads
- sip
- package structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 85
- 239000002184 metal Substances 0.000 claims abstract description 85
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 238000004806 packaging method and process Methods 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000001154 acute effect Effects 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 9
- 238000004021 metal welding Methods 0.000 description 8
- 238000009713 electroplating Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 229910001252 Pd alloy Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005288 electromagnetic effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention discloses a system in a package (SIP) structure. The SIP structure comprises a circuit substrate, a chip and a plurality of metal leads, wherein the chip is arranged on the substrate, a plurality of metal bonding pads are arranged on the circuit substrate at the periphery of the chip, and the two ends of each metal lead are respectively connected with different metal bonding pads and arranged above the chip. In the SIP structure disclosed by the invention, a shielding cover comprises the plurality of metal leads, the metal bonding pads used for connecting the metal leads are arranged at the periphery of the chip, the two ends of each metal lead are respectively connected with different metal bonding pads, thus, the above shielding cover is formed above and on the two sides of the chip, and the shielding cover partially or completely covers the chip so as to achieve the purpose of shielding interference among different chips.
Description
Technical Field
The invention relates to the technical field of IC packaging, in particular to an SIP packaging structure.
Background
SIP (systemlinapackage system in package) is a package in which a plurality of functional chips, including a processor, a memory, and the like, are integrated, thereby implementing a substantially complete function. The SIP package can be flexibly integrated by adopting the existing package, and even 3D stacking can be carried out. Thus, the design cycle can be greatly shortened, and the functional device can have a choice. SIP packaging is increasingly applied in medical electronics, automotive electronics, power modules, image sensors, mobile phones, global positioning systems, Bluetooth and the like.
As electronic systems become smaller and the density of electronic components within SIP packages increases, electromagnetic interference (EMI) within the systems tends to be generated. Especially, some high frequency chip packaging structures, such as radio frequency chips, GPS chips, Bluetooth chips and other high frequency chips, are packaged into an integrated structure through SIP, and the mutual electromagnetic interference influence is large. Therefore, it is necessary to design an SIP package structure capable of reducing the influence of electromagnetic interference, so as to avoid the mutual electromagnetic interference effect of the chips in the package and avoid the performance degradation or the occurrence of errors of the system.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide an SIP package structure, which can shield the electromagnetic effect generated by the chip inside the SIP package body, so as to solve the problem of shielding electromagnetic interference.
In order to solve the technical problems, the invention adopts the technical scheme that: the utility model provides a SIP packaging structure, includes circuit substrate, sets up chip and many metal lead on the base plate, be provided with a plurality of metal bonding pads on the peripheral circuit substrate of chip, every metal lead both ends are connected different metal bonding pads respectively and are set up the chip top.
The invention has the beneficial effects that: the SIP packaging structure adopts a shielding structure with a plurality of metal leads, the periphery of a chip is provided with metal welding pads for connecting the metal leads, two ends of the metal leads are respectively connected with different metal welding pads, so that shielding covers are formed above and at two sides of the chip, the plurality of metal leads respectively cross the chip, and the chip is partially or completely covered on the chip, so that the purpose of mutual shielding interference among different chips is achieved.
Drawings
Fig. 1 is a schematic structural diagram of an SIP package structure according to an embodiment of the present invention;
fig. 2 is a structural sectional view of an SIP package structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an SIP package structure in which metal leads and side edges have an included angle according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an SIP package structure with two-layer metal leads according to an embodiment of the present invention.
Description of reference numerals:
1. a circuit substrate; 2. a metal pad; 3. a metal lead; 4. a chip; 5. and packaging the filling body.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
The most key concept of the invention is that a plurality of metal leads 3 are arranged on a chip 4, and two ends of each metal lead 3 are respectively fixed on different metal welding pads 2, so that the chips 4 can be partially or completely covered by the plurality of metal leads 3 to achieve the shielding effect.
Referring to fig. 1 to 4, the SIP package structure of the present invention includes a circuit substrate 1, a chip 4 disposed on the circuit substrate 1, and a plurality of metal leads 3, wherein the circuit substrate 1 at the periphery of the chip 4 is disposed with a plurality of metal pads 2, and two ends of each metal lead 3 are respectively connected to different metal pads 2 and disposed above the chip 4 to partially or completely cover the chip 4. Wherein,
from the above description, the beneficial effects of the present invention are: the SIP packaging structure adopts a shielding structure of a plurality of metal leads 3, the periphery of a chip 4 is provided with metal welding pads 2 used for connecting the metal leads 3, two ends of the metal leads 3 are respectively connected with different metal welding pads 2, so that the shielding covers are formed above and at two sides of the chip 4, the plurality of metal leads 3 respectively cross over the chip 4, and the chip 4 partially or completely covers the chip 4 to achieve the purpose of mutual shielding interference among different chips 4.
The circuit board 1 of the present invention is a printed circuit board, which may be an FR4 copper clad circuit board, a BT resin-based circuit board, or a printed circuit board of another type.
The metal bonding pad 2 is formed simultaneously with the metal circuit of the printed circuit board, and the surface is processed by electroplating gold or electroplating alloy, wherein the electroplating alloy can adopt common electroplating metals such as nickel-palladium alloy and the like in the market. The metal welding pads 2 are distributed around the high-frequency chip, and aim at connecting the metal silver wires with the metal silver wires to play a role of electromagnetic shielding. The metal bonding pad 2 should be designed as an integrated body, that is, all the metal leads 3 are connected into a whole to be electrically connected to achieve electrical conduction, the metal leads 3 are respectively connected with the metal bonding pad 2 by a lead bonding mode, and the path of each metal lead 3 passes through the upper part of the high-frequency chip to form the shielding case.
Furthermore, the area of the metal lead 3 covering the chip 4 is over 60%, and a large amount of data research shows that the effect of shielding electromagnetic interference can be achieved when the area of the wire covering the chip 4 is over 60%.
Further, the chip 4 is a high frequency chip.
In this embodiment, the chip 4 is a high frequency chip, which may be an RF chip, a GPS positioning chip, a DRAM memory chip, a bluetooth chip, or the like, and may be connected to the circuit substrate 1 through SMT or metal wire bonding, or the like.
Further, the metal leads 3 are disposed along one side of the chip 4 or in a vertical direction of the side.
In other embodiments, the metal leads 3 form an acute angle with one side of the chip 4.
In other embodiments, the shielding can has two layers, and the metal leads 3 in the two layers of shielding can have an included angle therebetween.
In other embodiments, all of the metal leads are arranged in parallel, or all of the metal leads form a grid.
Further, the diameter of the metal lead 3 is 10-250 μm, and the thickness of the metal lead 3 can be selected according to the size of the chip 4 and the specific electromagnetic interference shielding effect.
Further, the metal lead 3 may be made of copper wire, silver wire, aluminum wire or alloy wire, and the specific material may be selected according to the effect of shielding electromagnetic interference.
Further, the semiconductor device further includes a package filler 5, and the package filler 5 packages the chip 4 and the shield case on the circuit board 1 and covers the chip 4, the electronic component metal leads 3, and the like.
Referring to fig. 1 and fig. 2, a first embodiment of the present invention is: the SIP package structure of the present embodiment includes a circuit substrate 1, a metal pad 2, a metal lead 3, a chip 4 and a package filler 5. The circuit substrate can be a printed circuit board, and can be an FR4 copper-clad circuit board, or a BT resin-based circuit board, or other forms of printed circuit boards. The chip 4 is an RF (radio frequency) chip, a GPS (global positioning system) positioning chip, a DRAM (dynamic random access memory) storage chip, a Bluetooth chip and the like, and the chip 4 is arranged on the circuit substrate 1 and connected with the circuit substrate in an SMT (surface mount technology) or metal lead bonding mode and the like. The circuit substrate 1 at the periphery of the chip 4 is provided with a plurality of metal welding pads 2, a plurality of metal leads 3 are provided, and two ends of each metal lead 3 are respectively connected with one metal welding pad 2 and cross over the chip 4. The metal bonding pad 2 and the metal circuit of the printed circuit board are formed at the same time, and the surface is processed by electroplating gold or electroplating alloy (such as nickel palladium alloy). All metal weld pads connected with the metal leads are designed in an integrated mode, namely all the metal leads are electrically connected into a whole, so that electrical conduction is achieved, the electromagnetic shielding effect is achieved, and the chip 4 is protected. The package filling body 5 completely covers the chip, the metal lead, and other electronic components on the substrate.
The metal leads 3 may be arranged in various ways, as shown in fig. 1, and all the metal leads 3 are arranged in parallel along one of the side edges of the chip 4.
As shown in fig. 3, all the metal leads 3 are arranged in parallel along a direction forming an angle with the side of the chip 4.
As shown in fig. 4, the metal leads 3 are arranged in parallel in two directions, forming a grid, which may be perpendicular or at other angles. In order to achieve the shielding effect, the coverage area of the metal lead to the chip should preferably exceed 60% of the upper surface of the chip.
In summary, the SIP package structure provided by the present invention enables the plurality of metal leads 3 to form the shielding cover to cover the chip 4 partially or completely, thereby achieving the effect of shielding electromagnetic interference.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (10)
1. The utility model provides a SIP packaging structure, includes circuit substrate, sets up chip and many metal lead on the base plate, its characterized in that, be provided with a plurality of metal bonding pads on the peripheral circuit substrate of chip, every metal lead both ends are connected different metal bonding pads respectively and are set up the chip top.
2. The SIP package structure of claim 1, wherein the plurality of metal pads are electrically connected.
3. The SIP package structure of claim 1, wherein the metal leads cover more than 60% of the area of the chip.
4. The SIP package structure of claim 1, wherein the chip is a high frequency chip.
5. The SIP package structure of claim 1, wherein each of the metal leads is disposed along a side of the chip or in a vertical direction of the side.
6. The SIP package structure of claim 1, wherein each of the metal leads forms an acute angle with a side of the chip.
7. The SIP package structure of claim 1, wherein all the metal leads are arranged in parallel, or all the metal leads form a grid, or the metal leads form an upper and lower layer structure, wherein the metal leads of the upper layer have a different direction from the metal leads of the lower layer.
8. The SIP package structure of any of claims 1-7, wherein the metal leads have a diameter of 10-250 microns.
9. The SIP package structure of any one of claims 1-7, wherein the metal leads are made of copper wires, silver wires, aluminum wires or alloy wires.
10. The SIP package structure of any of claims 1-7, further comprising a package filler that encapsulates the chip and the shield on the circuit substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610076112.4A CN105552063A (en) | 2016-02-03 | 2016-02-03 | System in a package (SIP) structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610076112.4A CN105552063A (en) | 2016-02-03 | 2016-02-03 | System in a package (SIP) structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105552063A true CN105552063A (en) | 2016-05-04 |
Family
ID=55831156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610076112.4A Pending CN105552063A (en) | 2016-02-03 | 2016-02-03 | System in a package (SIP) structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105552063A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111653552A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | A quadrilateral flat chip package structure with high resistance to electromagnetic pulse interference |
| CN112992881A (en) * | 2019-12-17 | 2021-06-18 | 江苏长电科技股份有限公司 | Electromagnetic shielding packaging structure |
| US12009314B2 (en) | 2020-01-17 | 2024-06-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of compartment shielding using bond wires |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1119903A (en) * | 1993-02-02 | 1996-04-03 | Ast研究公司 | A circuit board device containing shielding net and its structure |
| US20020096749A1 (en) * | 2001-01-22 | 2002-07-25 | International Rectifier Corporation | Clip-type lead frame for source mounted die |
| CN101023560A (en) * | 2004-08-06 | 2007-08-22 | 国际商业机器公司 | Apparatus and methods for constructing antennas using wire bonds as radiating elements |
| JP2008010636A (en) * | 2006-06-29 | 2008-01-17 | Rohm Co Ltd | Light receiving module |
| CN102160175A (en) * | 2008-08-22 | 2011-08-17 | 台湾积体电路制造股份有限公司 | Impedance controlled electrical interconnects using metamaterials |
| CN102969303A (en) * | 2012-10-26 | 2013-03-13 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| US20150048490A1 (en) * | 2013-08-13 | 2015-02-19 | Kabushiki Kaisha Toshiba | Memory module |
| US20150223322A1 (en) * | 2014-01-31 | 2015-08-06 | Stmicroelectronics S.R.L. | Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof |
| US9240372B1 (en) * | 2002-01-16 | 2016-01-19 | Marvell International Ltd. | Semiconductor die having lead wires formed over a circuit in a shielded area |
| CN205542768U (en) * | 2016-02-03 | 2016-08-31 | 深圳佰维存储科技有限公司 | SIP packaging structure |
-
2016
- 2016-02-03 CN CN201610076112.4A patent/CN105552063A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1119903A (en) * | 1993-02-02 | 1996-04-03 | Ast研究公司 | A circuit board device containing shielding net and its structure |
| US20020096749A1 (en) * | 2001-01-22 | 2002-07-25 | International Rectifier Corporation | Clip-type lead frame for source mounted die |
| US9240372B1 (en) * | 2002-01-16 | 2016-01-19 | Marvell International Ltd. | Semiconductor die having lead wires formed over a circuit in a shielded area |
| CN101023560A (en) * | 2004-08-06 | 2007-08-22 | 国际商业机器公司 | Apparatus and methods for constructing antennas using wire bonds as radiating elements |
| JP2008010636A (en) * | 2006-06-29 | 2008-01-17 | Rohm Co Ltd | Light receiving module |
| CN102160175A (en) * | 2008-08-22 | 2011-08-17 | 台湾积体电路制造股份有限公司 | Impedance controlled electrical interconnects using metamaterials |
| CN102969303A (en) * | 2012-10-26 | 2013-03-13 | 日月光半导体制造股份有限公司 | Semiconductor package structure and manufacturing method thereof |
| US20150048490A1 (en) * | 2013-08-13 | 2015-02-19 | Kabushiki Kaisha Toshiba | Memory module |
| US20150223322A1 (en) * | 2014-01-31 | 2015-08-06 | Stmicroelectronics S.R.L. | Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof |
| CN205542768U (en) * | 2016-02-03 | 2016-08-31 | 深圳佰维存储科技有限公司 | SIP packaging structure |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112992881A (en) * | 2019-12-17 | 2021-06-18 | 江苏长电科技股份有限公司 | Electromagnetic shielding packaging structure |
| US12009314B2 (en) | 2020-01-17 | 2024-06-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of compartment shielding using bond wires |
| CN111653552A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | A quadrilateral flat chip package structure with high resistance to electromagnetic pulse interference |
| CN111653552B (en) * | 2020-06-16 | 2022-06-10 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
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| C06 | Publication | ||
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| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 518055, Guangdong, Nanshan District, Taoyuan Shenzhen street, with the rich industrial city, No. 4 factory building, 1 floor, 2 floor, 4 floor, 5 floor Applicant after: Shenzhen Bai dimensional storage Polytron Technologies Inc Address before: 518000, Guangdong, Nanshan District, Taoyuan Shenzhen street, with the rich industrial city, No. 4 factory building, 1 floor, 2 floor, 4 floor, 5 floor Applicant before: Biwin Storage Technology Limited |
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| COR | Change of bibliographic data | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160504 |
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| RJ01 | Rejection of invention patent application after publication |