CN105530213A - A Hybrid Baseband System for High Speed Communication - Google Patents

Abstract

The invention discloses a mixed baseband system for high speed communication, comprising a modulus carrier recovering module which comprises a phase rotator, is connected to the output of a high speed communication system and is used for receiving signals demodulated by the high speed communication system and removing the influence of carrier deviation on the signals through recovering the phase of a sender; a data feedback equalizing module which is connected to the modulus carrier recovering module and is used for equalizing the signals output by the modulus carrier recovering module so as to reduce the influence of intersymbol interference and further increase the Signal to Noise Ratio; a clock and data covering module which is connected to the data feedback equalizing module and is used for recovering a clock and demodulating the signals output by the data feedback equalizing module so as to obtain and output finally demodulated signals. Compared with the prior art, the system of the invention simplifies the baseband design of a receiver and saves power consumption on the premise of ensuring signal transmission processing precision and accuracy.

Description

A Hybrid Baseband System for High Speed Communication

technical field

The invention relates to the communication field, in particular to a hybrid baseband system for high-speed communication.

Background technique

With the continuous development of communication technology, a 60 GHz millimeter wave high-speed communication system is proposed in the prior art.

The standard of the 60GHz millimeter wave high-speed communication system is as high as 7GHz or more than the channel bandwidth occupied by traditional communication (for example, the frequency range of the license-free frequency in the United States is 57GHz to 64GHz), thus providing the possibility for ultra-high-speed communication rates. The current 60GHz millimeter wave communication rate can reach Gbps, while the 802.11n standard and carrierless communication technology (UltraWideband, UWB) can only achieve 600Mbps and 480Mbps.

Compared with traditional communication system standards, the communication system in the 60GHz frequency band has many advantages. First of all, due to the strong directivity of wireless signals in the 60GHz frequency band, the communication signals of 60GHz communication systems in different directions interfere with each other very little; The inter-communication system interference of the communication system is therefore very small and almost negligible. Secondly, the loss of the signal on 60GHz in free space is very large, reaching 15dB/km, and obstacles also greatly attenuate the millimeter wave of 60GHz. Therefore, short-distance wireless communication on 60GHz has a natural high security. Advantage. Thirdly, the 60 GHz communication system designed by integrated circuit monolithic requires smaller components than traditional communication standards, thereby reducing costs.

At present, the 60GHz millimeter wave communication system is under intense research, and the existing standards are not uniform, including 802.11ad launched by the IEEE standardization organization, WirelessHD1.1 launched by the WirelessHD working group established by LG and Panasonic, and WirelessHD1.1 by Intel and Nokia. WiGig1.0 formulated by the WiGig Alliance composed of such as. A variety of non-uniform standards make it difficult to achieve compatibility and matching between different system architectures.

In addition, the architecture adopted by many 60GHz millimeter wave communication system designs is still the traditional transceiver mode. This mode usually separates the design of the RF front-end, analog baseband and digital baseband, thus resulting in the need for analog and digital baseband circuits. An analog-to-digital converter ADC. Since the communication data rate of 60GHz millimeter wave communication is very high, the ADC performance corresponding to the requirements is very high, which makes ADC design difficult and consumes a lot of power. In addition, due to the communication with a data rate of up to Gbps, the switching speed of the digital baseband circuit will be very fast, resulting in a large power consumption of the digital baseband circuit.

Therefore, in view of the problems existing in the 60 GHz millimeter wave communication system in the prior art, a new hybrid baseband system for high-speed communication is needed.

Contents of the invention

Aiming at the problems existing in the 60GHz millimeter wave communication system in the prior art, the present invention provides a hybrid baseband system for high-speed communication, the system includes an analog-to-digital carrier recovery module, a data feedback equalization module, and a clock and data recovery module, in:

The analog-to-digital carrier recovery module includes a phase rotator, which is connected to the output of the high-speed communication system, the phase rotator is used to rotate the phase of the input signal, and the analog-to-digital carrier recovery module is used to receive demodulated signals from the high-speed communication system signal and cancel the effect of carrier deviation on said signal by restoring the phase of the transmitter;

The data feedback equalization module is connected to the analog-to-digital carrier recovery module, and is used to equalize the signal output by the analog-to-digital carrier recovery module to reduce the influence of intersymbol interference, thereby increasing the signal-to-noise ratio;

The clock and data recovery module is connected to the data feedback equalization module, and is used for recovering the clock and demodulating the signal output by the data feedback equalization module to obtain and output the final demodulated signal.

In one embodiment, the analog-to-digital carrier recovery module further includes a first error detector and a first loop filter, wherein:

The first error detector is connected to the output of the clock and data recovery module for detecting the final demodulated signal to obtain a first error signal;

The first loop filter is connected to the first error detector, and the first loop filter outputs a first control word for controlling the phase rotator based on the error signal;

The phase rotator is connected to the first loop filter, and under the control of the first control word, the phase rotator rotates the input signal by a corresponding phase and outputs it.

In an embodiment, the data feedback equalization module includes a first amplifier for amplifying signals and a first signal path for transmitting signals, wherein:

The input of the first amplifier is connected to the output of the analog-to-digital carrier recovery module;

The input of the first signal path is connected to the output of the first amplifier, and the output of the first signal path is the output of the data feedback equalization module.

In an embodiment, the data feedback equalization module further includes a data feedback equalizer, and the data feedback equalizer includes:

a second error detector connected to the output of the clock and data recovery module for detecting the final demodulated signal to obtain a second error signal;

a data sampler, connected to the first signal path, for collecting the analog signal transmitted on the first signal path and converting the collected analog signal into a digital sampling signal;

A second loop filter, connected to the second error detector and the data sampler, for outputting a second control word based on the second error signal and the digital sampling signal;

a first balanced current source branch connected to said second loop filter and connected to a location on said first signal path between said data sampler access point and said first amplifier output, for Outputting a first branch current with a specific magnitude and direction to the first signal path based on the second control word to equalize signal data transmitted on the first signal path.

In one embodiment, the data feedback equalization module further includes a tail equalizer, and the tail equalizer includes:

A third error detector, which is connected to a position after the access point of the first equalizing current source branch on the first signal path, and is used to detect the signal transmitted on the first signal path to obtain the second error detector. Three error signals;

a third loop filter connected to the third error detector and configured to output a third control word based on the third error signal;

A shift register array, which is connected to the clock and data recovery module, and is used to delay and shift the demodulated data;

A second balancing current source branch connected to the third loop filter and the shift register array and connected to the third error detector and the first balancing current on the first signal path A position between source branch access points, for outputting a second branch current of a specific magnitude and direction to the first signal path based on the third control word and the output of the shift register array to balance all Signal data transmitted on the first signal path.

In one embodiment, the clock and data recovery module includes:

A lead-lag phase detector connected to the output of the clock and data recovery module for analyzing the final demodulated signal to obtain a lead/lag signal;

a fourth loop filter, which is connected to the lead-lag phase detector, and is used to output a fourth control word based on the lead/lag signal;

a phase interpolator, which is connected to the fourth loop filter and connected to the high-speed communication system, and is used to acquire the frequency-divided signal of the high-speed communication system and perform the frequency-division signal according to the fourth control word Make phase adjustments;

A clock shaping buffer, which is connected to the phase interpolator, is used to acquire and output a corresponding square wave clock according to the phase-adjusted frequency-divided signal;

a duty ratio adjuster, which is connected to the clock shaping buffer and is used to output a corresponding sampling clock according to the square wave clock;

A sampling output unit, which includes a signal input terminal, a signal output terminal and a control terminal, wherein the control terminal is connected to the duty ratio regulator, and the signal input terminal and the signal output terminal are respectively the clock and the The input and output of the data recovery module, the sampling output unit is used to sample the input signal based on the sampling clock to obtain the final demodulated signal.

In an embodiment, the system further includes an analog-to-digital direct current cancellation feedback module, and the analog-to-digital direct current cancellation feedback module is installed between the data feedback equalization module and the clock and data recovery module for eliminating the The DC offset of the signal output by the data feedback equalization module.

In one embodiment, the analog-to-digital DC cancellation feedback module includes:

a second amplifier, the input of which is connected to the output of the data feedback equalization module;

a second signal path, the input of which is connected to the output of the second amplifier, the output of which is connected to the input of the clock and data recovery module;

a fourth error detector connected to the output of the second signal path for obtaining a fourth error signal based on the output signal of the second signal path;

a fourth loop filter connected to the fourth error detector and configured to output a fifth control word based on the fourth error signal;

a reference voltage generator, connected to the fourth loop filter and connected to the second signal path, for outputting a reference voltage to the second signal path based on the fifth control word to eliminate the first The DC offset of the signal transmitted on the second signal path.

In one embodiment, the analog-to-digital DC cancellation feedback module further includes a third amplifier connected between the reference voltage generator and the second signal path, and used to amplify and adjust the output of the reference voltage generator The reference voltage is amplified and adjusted to output the reference voltage to the second signal path so as to eliminate the DC offset.

In an embodiment, the analog-to-digital DC cancellation feedback module further includes a DC offset detector, and the DC offset detector is used to detect whether there is a DC offset in the final demodulated signal, so as to control the modulus based on the detection result. On/off of the DC cancellation feedback module.

Compared with the prior art, the system of the present invention simplifies the baseband design of the receiver and saves power consumption under the premise of ensuring signal transmission processing precision and accuracy.

Additional features or advantages of the invention will be set forth in the ensuing description. And, some features or advantages of the present invention will be apparent from the description, or be understood by practicing the present invention. The objects and some of the advantages of the invention will be realized or obtained by the steps particularly pointed out in the written description, claims as well as the appended drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the description, and are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the attached picture:

Fig. 1 is a schematic diagram of a system structure according to an embodiment of the present invention.

detailed description

The implementation of the present invention will be described in detail below in conjunction with the accompanying drawings and examples, so that implementers of the present invention can fully understand how the present invention uses technical means to solve technical problems, and achieve the realization process of technical effects and according to the above-mentioned realization process The present invention is implemented concretely. It should be noted that, as long as there is no conflict, each embodiment and each feature in each embodiment of the present invention can be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.

At present, the 60GHz millimeter-wave communication system is under intense research, and the existing standards are not uniform. Various non-uniform standards make it difficult to achieve compatibility and matching among different system architectures. In addition, the architecture adopted by many 60GHz millimeter wave communication system designs is still the traditional transceiver mode. This mode usually separates the design of the RF front-end, analog baseband and digital baseband, thus resulting in the need for analog and digital baseband circuits. An analog-to-digital converter ADC. Since the communication data rate of 60GHz millimeter wave communication is very high, the ADC performance corresponding to the requirements is very high, which makes ADC design difficult and consumes a lot of power. In addition, due to the communication with a data rate of up to Gbps, the switching speed of the digital baseband circuit will be very fast, resulting in a large power consumption of the digital baseband circuit.

Aiming at the problems existing in the 60GHz millimeter wave communication system in the prior art, the present invention proposes a hybrid baseband system for high-speed communication. As shown in FIG. 1 , in an embodiment of the present invention, the system includes an analog-to-digital carrier recovery module 110 , a data feedback equalization module 120 and a clock and data recovery module 150 .

The analog-to-digital carrier recovery module 110 includes a phase rotator 111 . The analog-to-digital carrier recovery module 110 is connected to the output of the high-speed communication system, and the phase rotator 111 is used to rotate the phase of the input signal. The analog-to-digital carrier recovery module 110 is used to receive the demodulated signal of the high-speed communication system and eliminate the influence of the carrier deviation on the signal by recovering the phase of the transmitter.

The data feedback equalization module 120 is connected to the analog-to-digital carrier recovery module 110 and is used for equalizing the signal output by the analog-to-digital carrier recovery module so as to reduce the influence of intersymbol interference and increase the signal-to-noise ratio.

The clock and data recovery module 150 is connected to the data feedback equalization module 120 for recovering the clock and demodulating the signal output by the data feedback equalization module 120 to obtain and output the final demodulated signal.

Further, in this embodiment, the data feedback equalization module 120, the analog-to-digital carrier recovery module 110, and the clock and data recovery module 150 are all configurable adaptive modules. The RF signal is input to the phase rotator 111 in the configurable analog-to-digital carrier recovery module 110 after passing through the quadrature phase shift keying (QuadraturePhaseShiftKeyin, QPSK) demodulator of the high-speed communication system, and the phase rotator 111 rotates the incoming signal, so that Its output signal is no longer degraded by carrier phase and frequency inconsistency. The output signal of the phase rotator 111 is sent to the data feedback equalization module 120, which reduces the deterioration of the signal-to-noise ratio caused by intersymbol interference caused by channels or encoding. The data feedback equalization module 120 outputs a signal to the sampling output part of the clock and data recovery module 150 .

In this embodiment, the data feedback equalization module 120 is adopted because of the time-varying and unpredictability of the channel. The adaptive equalization process of the data feedback equalization module 120 is to adjust the loop filter coefficients so that the mean square error of the error between the equalized output signal and the ideal output reaches the minimum, and the way to adjust the filter coefficients is to move towards the mean square error sphere Iterate step by step in the direction of the steepest descent, and finally reach the minimum mean square error. The adjusted step size, that is, the gain of the loop filter, has a lot to do with the convergence speed, system stability, input signal-to-noise ratio, and final convergence error, so the invention can flexibly select the convergence step size through configuration. , so as to choose the optimal result among the above trade-offs.

In order to reduce the output error, in this embodiment, the analog-to-digital carrier recovery module 110 also includes a first error detector 112 and a first loop filter 113, wherein: the first error detector 112 is connected to the clock and data recovery module 150 (the final output of the system), used to detect the final demodulated signal so as to obtain the first error signal; the first loop filter 113 is connected with the first error detector 112, and the first loop filter 113 is based on the first error detector 112 An error signal output by an error detector 112 is used to control the first control word of the phase rotator 111; the phase rotator 111 is connected with the first loop filter 113, and the phase rotator 111 will be under the control of the first control word The input signal is output after rotating the corresponding phase.

The analog-to-digital carrier recovery module 110 mainly solves the signal distortion caused by frequency drift and phase inconsistency between the local oscillators of the transmitter and receiver. In this embodiment, it is aimed at the quadrature phase shift keying (Quadrature Phase Shift Keyin, QPSK) modulation mode on 60 GHz. The signal received by the configurable analog-to-digital carrier recovery module 110 can be represented by the following formula:

In Formula 1:

t is a time variable;

x is the instantaneous phase of the signal input to the phase rotator 111 after being disturbed;

Δf and represent the frequency difference and initial phase difference between the receiver and the transmitter, respectively;

I and Q are input quadrature signals before interference;

I(in) and Q(in) are signals input to the phase rotator 111 after being disturbed;

amp represents the instantaneous amplitude of the signal input to the phase rotator 111 after being disturbed.

It can be seen from formula 1 that when the input I/Q is subjected to Δf and After interference, the input signals I(in) and Q(in) entering the phase rotator 111 will be distorted in amplitude. After the signal is rotated by the phase rotator 111, it can be expressed by the following formula:

$\left\{\begin{array}{c}\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; cos</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\sqrt{{\mathrm{<span\; class="notranslate">\; I</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; )</span>}\\ \mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; sin</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\sqrt{{\mathrm{<span\; class="notranslate">\; I</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; )</span>}\mathrm{<span\; class="notranslate">\; cos</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; )</span>\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

In formula 2:

I(out) and Q(out) are signals output by the phase rotator 111;

y is the rotation angle of the phase rotator.

It can be seen from formula 2 that the phase of the quadrature signal after rotation is compensated compared with the original signal. When the compensation amount is inconsistent with the input phase difference, the output signal is also distorted in amplitude. This distorted signal will make the first error The error detected by the detector 112 is used by the first loop filter 113. When the amount of compensation is the same as the deviation caused by the local oscillator, the loop will enter a locked state. Since the phase rotator 111 changes the phase amount, and the deviation of the local oscillator includes frequency deviation, to track the phase difference caused by the frequency difference, the first loop filter 113 is designed to be at least second-order. When the loop enters the tracking locked state, the initial phase difference is corrected, and the existing frequency difference is also tracked in the second-order digital first loop filter 113, and the control word is output every clock cycle to rotate the phase of the phase rotator 111 Coincident with the phase caused by the frequency, thus recovering the carrier.

In addition, because the locking speed and stability of the loop have a great relationship with the gain of the frequency integration path, and the frequency integration path also has a direct relationship with the frequency deviation that can be corrected, so the system of the present invention can pass the actual frequency deviation range Configure the gain of the frequency path to make the best choice in terms of locking speed and stability and function.

The data feedback equalization module 120 solves the intersymbol interference caused by the channel, and the sampling of the impulse response of the band-limited channel can be simply expressed by the following formula.

h(t)=H ₁ (t)+H(t-nT)(n=1,2...)(3)

In Equation 3: h(t) represents the total impulse response of the band-limited channel at time t. Among them, H ₁ (t) represents the response to the signal at the current time t; H(t-nT) represents the response (interference) to the signal after n sampling clocks, where n is an integer, and T is the period of the sampling clock .

It can be seen from Equation 3 that the signal at time t will interfere with the signal sampled by the next clock T. The data feedback equalization module 120 of this embodiment reduces or even eliminates this interference.

In this embodiment, the data feedback equalization module 120 includes a first amplifier 121 for amplifying the signal and a first signal path for transmitting the signal, wherein: the input of the first amplifier 121 and the output of the analog-to-digital carrier recovery module 110 ( The output of the phase rotator 111) is connected; the input of the first signal path is connected with the output of the first amplifier 121, and the output of the first signal path is the output of the data feedback equalization module.

Further, in this embodiment, the data feedback equalization module 120 also includes a data feedback equalizer 122, and the data feedback equalizer 122 compensates the loss introduced by the current data, which includes:

The second error detector 125, which is connected to the output of the clock and data recovery module 150, is used to detect the final demodulated signal so as to obtain the second error signal;

A data sampler 126, which is connected to the first signal path, for collecting the analog signal transmitted on the first signal path and converting the collected analog signal into a digital sampling signal;

The second loop filter 124, which is connected to the second error detector 125 and the data sampler 126, is used to output the second control word based on the second error signal and the digital sampling signal;

A first balanced current source branch 123, which is connected to the second loop filter 124 and connected to the first signal path for outputting a first branch current with a specific magnitude and direction to the first signal path based on the second control word to Signal data transmitted on the first signal path is equalized. The access position of the first balanced current source branch 123 in the first signal path is the position between the access point of the data sampler 126 and the output of the first amplifier 121, so that the sampled by the data sampler 126 is the first balanced current source The equalized result signal of branch 123.

Further, in this embodiment, the data feedback equalization module 120 further includes a tail equalizer 130 . ; The tail equalizer is to compensate and eliminate the crosstalk introduced by the previously received data, which includes:

The third error detector 133, which is connected to the position after the access point of the first balanced current source branch 123 on the first signal path, is used to detect the signal transmitted on the first signal path so as to obtain the third error signal ( What is detected is the result signal after the equalization of the first equalization current source branch 123);

The third loop filter 132, which is connected to the third error detector 133, is used to output the third control word based on the third error signal;

A shift register array 134, which is connected to the clock and data recovery module 150, and is used for delay shifting the demodulated data;

The second balanced current source branch 131 is connected to the third loop filter 132 and the shift register array 134 and connected to the first signal path. The third error detector 133 is connected to the first balanced current source branch 123. The position between the points is used to output a specific size to the first signal path based on the third control word and the output of the shift register array (the signal output by the shift register array is the signal obtained after the demodulated data is delayed). and the second branch current in the direction to equalize the signal data transmitted on the first signal path.

Specifically, the third control word output by the third loop filter 132 and the output of the shift register array 134 jointly control the equalization current branch at the corresponding position, and control the number and direction of opening thereof, so as to equalize the current data.

In this embodiment, the function of the clock and data recovery module 150 is to recover the clock from the input data and complete the final digital signal output. The clock and data recovery module 150 mainly adjusts the output signal phase of the main PLL frequency divider Finally, the duty cycle is adjusted through the clock shaping buffer to realize the clock recovery. The realization of the phase adjustment of the output signal of the frequency divider is realized by the quadrature phase interpolator, and its principle can be explained by the following formula.

$\left\{\begin{array}{c}\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; +</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; Q</span>}\\ \mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; I</span>}\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; I</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; Q</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; L</span>}\mathrm{<span\; class="notranslate">\; K</span>}\mathrm{<span\; class="notranslate">\; I</span>}\end{array}\right.<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

In formula 4:

OUTI and OUTQ represent the adjusted output;

CLKI and CLKQ represent the quadrature frequency divider output of the main phase-locked loop;

IA, IB, IC, ID generation loop filter output control word;

α1=IA-IB, α2=IC-ID represent the relative amplification factors of CLKI and CLKQ signals, respectively.

The phase of the output clock can be changed by adjusting the output control word. The input signal is sampled by the rising edge and falling edge clock of CLKI and the rising edge of CLKQ and sent to the lead-lag phase detector to identify the lead-lag information, and then send this information to the loop filter to control the digital loop filter to update the output control font size and orientation.

Same as the carrier recovery, since the recovery of the clock not only needs to recover the moderate phase but also recovers the frequency difference between the clock and the data, this embodiment adopts a second-order digital loop filter to track the drift of the frequency. In addition, because there is a great relationship between the frequency integration loop gain of the secondary loop filter and the locking speed, locking deviation range and loop stability, the present invention can perform optimal manual configuration according to needs. The signal output by the phase interpolator is turned into a full-scale output signal through a clock shaping buffer, and finally becomes a sampling clock with a 50% duty cycle after adjusting the duty cycle.

The principle of the duty ratio adjustment circuit is briefly described as follows: the DC level of the signal with a duty ratio of less than 50% is less than half of the full rail level, and the other end of the difference must be greater than half of the full rail level, and the difference is taken out through a first-order RC filter For the DC term of the clock, a comparator compares the difference between the two, and then adjusts the common-mode level of the duty cycle regulator-inverter, so that the duty cycle of the output clock is 50%.

Specifically, the clock and data recovery module 150 includes a lead-lag phase detector 152 , a fourth loop filter 153 , a phase interpolator 154 , a clock shaping buffer 155 , a duty cycle adjuster 156 and a sampling output unit 151 .

A lead-lag phase detector 152 (lead-lag phase discriminator (BangBangPD)) is connected to the output of the clock and data recovery module 150 for analyzing the final demodulated signal to obtain the lead/lag signal.

The fourth loop filter 153 is connected with the lead-lag phase detector 152, and is used for outputting a fourth control word based on the lead/lag signal.

The phase interpolator 154 is connected to the fourth loop filter 153 and connected to the high-speed communication system, and is used to obtain the frequency-divided signal of the high-speed communication system and adjust the phase of the frequency-divided signal according to the fourth control word.

Clock shaping buffer 155 (current mode latch type clock to complementary bipolar transistor type (CMOS) clock shaping buffer (buffer)) is connected with phase interpolator 154, is used for obtaining and Output the corresponding square wave clock;

The duty cycle adjuster 156 is connected to the clock shaping buffer 155 and is used for outputting a corresponding sampling clock according to the square wave clock output by the clock shaping buffer 155 .

The sampling output unit 151 includes a signal input terminal, a signal output terminal and a control terminal, wherein the control terminal of the sampling output unit 151 is connected to the duty ratio adjuster 156, and the signal input terminal and the signal output terminal are clock and data recovery modules 150 respectively. For input and output, the sampling output unit 151 is used for sampling the input signal based on the sampling clock so as to obtain the final demodulated signal.

Specifically, the duty ratio regulator 156 itself is composed of two identical inverters, a DC blocking capacitor, a DC bias resistor, a differential first-order RC filter, an error comparator, a bias voltage generator, and a digital control module. The differential output of the clock shaping buffer 155 is sent to the input ends of two identical inverters respectively through the DC blocking capacitor, and the output of an inverter of the duty cycle regulator 156 is sent to the sampling output unit 151 as mentioned above on the one hand, On the other hand, they are respectively sent to the differential first-order RC filter. The differential first-order RC filter retains the respective DC components of the differential after filtering out high-frequency components. The two DC component signals are respectively connected to the two ends of the comparator, the output signal of the comparator is sent to the control module, and the control module outputs the control word to control the bias voltage generator to generate the corresponding differential bias voltage, and the differential bias voltage passes through the Bias resistors are added to the input terminals of the two directional devices to adjust their respective DC operating points.

Further, in this embodiment, the system further includes an analog-to-digital direct current cancellation feedback module 140 . The analog-to-digital DC cancellation feedback module 140 is installed between the data feedback equalization module 120 and the clock and data recovery module 150, and is used for eliminating the DC offset of the signal output by the data feedback equalization module.

In this embodiment, the data feedback equalization module 120 outputs a signal to the analog-to-digital DC cancellation feedback module 140 . The analog-to-digital DC elimination feedback module 140 eliminates the DC offset caused by the previous stage and the current stage, and then outputs the regulated signal to the clock and data recovery module 150 . The clock and data recovery module 150 uses the recovered clock sampling data to recover data.

The way for the analog-to-digital DC cancellation feedback module 140 to solve the DC offset is to add an auxiliary amplifier unit, and connect the output of the auxiliary amplifier unit to the output of the main amplifier unit. Both the accumulation of the previous stage and the DC error introduced by this stage can be equivalent to the DC offset of the output of the main amplifier. When there is no input signal at the original input terminal of the baseband, the output of the main amplifier is sampled by the sampler, and the input differential of the auxiliary amplifier is continuously adjusted. The bias voltage makes the output of the main amplifier close to zero, thereby finally eliminating the accumulation of the previous stage and the DC offset caused by this stage.

Specifically, in this embodiment, the analog-to-digital DC cancellation feedback module 140 includes:

The second amplifier 141, whose input end is connected to the output of the data feedback equalization module 150 (the output end of the first signal path);

A second signal path, the input of which is connected to the output of the second amplifier 141, the output of which is connected to the input of the clock and data recovery module 150;

a fourth error detector 144, connected to the output of the second signal path, for obtaining a fourth error signal based on the output signal of the second signal path;

A fourth loop filter 145, which is connected to the fourth error detector 144, and is used to output the fifth control word based on the fourth error signal;

A reference voltage generator 143, which is connected to the fourth loop filter and connected to the second signal path, for outputting a reference voltage to the second signal path based on the fifth control word to eliminate the direct current of the signal transmitted on the second signal path out of tune.

The specific position where the reference voltage generator 143 is connected to the second signal path is between the connection position of the fourth error detector 144 and the output of the second amplifier 141 .

Further, the analog-to-digital DC elimination feedback module 140 also includes a third amplifier 142, which is connected between the reference voltage generator 143 and the second signal path, and is used to amplify and adjust the reference voltage output by the reference voltage generator and amplify the adjusted The reference voltage output to the second signal path to achieve the elimination of DC offset.

Further, in another embodiment of the present invention, the analog-to-digital DC cancellation feedback module further includes a DC offset detector, and the DC offset detector is used to detect whether there is a DC offset in the final demodulated signal, so as to control the analog-to-digital DC cancellation based on the detection result On/off of the feedback module.

In order to control the system of the present invention, in an embodiment of the present invention, the system further includes a digital configuration module. The digital configuration module is connected with all other controllable components in the system, and is used to control the control variables of all other controllable components in the processing system. Including: the frequency path gain of the loop filter in the configurable analog-digital hybrid carrier restorer, the rotation control word of the configuration phase rotator in manual mode, the gain of the loop filter of the configurable adaptive data feedback equalizer, Configuration of the equalizer in manual mode, configurable hybrid analog-digital DC offset cancellation feedback module in manual mode, configurable frequency and phase gain configuration of digital loop filtering in the clock and data recovery module, configurable in manual mode Configure the configuration of the interpolator in the clock and data recovery module, and configure the configuration of the duty cycle regulator in the clock and data recovery module in manual mode.

Further, the digital configuration module includes a serial data interface (represented by SPI), a register file and a bias generation module. The DC biasing and SPI configuration principles included in the auxiliary section remain the same as in the basic receiver.

The serial data interface is used to communicate with the external digital processing part, and the control signal is written into the internal register file. The input terminals of the serial data interface are the external clock CLK, the external state reversal clock SCLK, the external chip select signal SCS and the external The serial input data SDI, the first output terminal of the serial data interface is the serial data output terminal SDO. The second output terminal of the serial data interface is connected to the input of the register file, and is used for controlling the value stored in the register in the register file.

Register file, analog-digital hybrid baseband for 60GHz mmWave high-speed communication system provides control of all configurable variables, including: configurable analog-digital hybrid carrier recoverer, frequency path gain of the loop filter, configuration phase in manual mode The rotation control word of the rotator, the gain of the loop filter of the configurable adaptive data feedback equalizer, the configuration of the equalizer in manual mode, the configuration under the configurable mixed modulus DC offset cancellation feedback module in manual mode, configurable Configure Frequency and Phase Gain Configuration of Digital Loop Filtering in Clock and Data Recovery Block, Configuration of Interpolator in Configurable Clock and Data Recovery Block in Manual Mode, Duty Duty in Configurable Clock and Data Recovery Block in Manual Mode ratio regulator configuration. The input of the register file is connected with the output end of the serial data interface, and the output end of the register file is connected with the control end of the configurable variable.

The bias generation module provides the required bias voltage and bias current for the analog-digital hybrid baseband applied to the 60GHz millimeter wave high-speed communication system.

In order to reduce the volume of the system, in an embodiment of the present invention, the system adopts a single-chip integrated circuit structure.

The invention adopts single-chip integrated circuit technology to realize the analog-digital mixed baseband applied to the 60GHz millimeter wave communication system. Compared with the prior art, due to the use of single-chip integrated circuit technology, the size of the system of the present invention is small and the cost is low; in addition, the system of the present invention can configure many system indicators wherein, the gain of the frequency integration path of carrier recovery , Manual Mode Download Wave Recovery Configuration, Loop Gain for Data Feedback Equalizer, Data Feedback Equalizer in Manual Mode, DC Offset Configuration in Manual Mode, and Frequency Integration Path Gain in Clock and Data Recovery and Clock Data in Manual Mode Restoring the configuration; at the same time, the system according to the invention simplifies the baseband design of the receiver and saves power consumption due to the adoption of a hybrid baseband design method.

Although the embodiments disclosed in the present invention are as above, the described content is only an embodiment adopted for the convenience of understanding the present invention, and is not intended to limit the present invention. The method described in the present invention can also have other various embodiments. Without departing from the essence of the present invention, those skilled in the art can make various corresponding changes or modifications according to the present invention, but these corresponding changes or modifications should all belong to the protection scope of the claims of the present invention.

Claims (10)

1. A hybrid baseband system for high-speed communications, characterized in that the system includes an analog-to-digital carrier recovery module, a data feedback equalization module and a clock and data recovery module, wherein: The analog-to-digital carrier recovery module includes a phase rotator, which is connected to the output of the high-speed communication system, the phase rotator is used to rotate the phase of the input signal, and the analog-to-digital carrier recovery module is used to receive demodulated signals from the high-speed communication system signal and cancel the effect of carrier deviation on said signal by restoring the phase of the transmitter; The data feedback equalization module is connected to the analog-to-digital carrier recovery module, and is used to equalize the signal output by the analog-to-digital carrier recovery module to reduce the influence of intersymbol interference, thereby increasing the signal-to-noise ratio; The clock and data recovery module is connected to the data feedback equalization module, and is used for recovering the clock and demodulating the signal output by the data feedback equalization module to obtain and output the final demodulated signal. 2. The system of claim 1, wherein the analog-to-digital carrier recovery module further comprises a first error detector and a first loop filter, wherein: The first error detector is connected to the output of the clock and data recovery module for detecting the final demodulated signal to obtain a first error signal; The first loop filter is connected to the first error detector, and the first loop filter outputs a first control word for controlling the phase rotator based on the error signal; The phase rotator is connected to the first loop filter, and under the control of the first control word, the phase rotator rotates the input signal by a corresponding phase and outputs it. 3. The system according to claim 1 or 2, wherein the data feedback equalization module comprises a first amplifier for amplifying signals and a first signal path for transmitting signals, wherein: The input of the first amplifier is connected to the output of the analog-to-digital carrier recovery module; The input of the first signal path is connected to the output of the first amplifier, and the output of the first signal path is the output of the data feedback equalization module. 4. The system according to claim 3, wherein the data feedback equalization module further comprises a data feedback equalizer, and the data feedback equalizer comprises: a second error detector connected to the output of the clock and data recovery module for detecting the final demodulated signal to obtain a second error signal; a data sampler, connected to the first signal path, for collecting the analog signal transmitted on the first signal path and converting the collected analog signal into a digital sampling signal; A second loop filter, connected to the second error detector and the data sampler, for outputting a second control word based on the second error signal and the digital sampling signal; a first balanced current source branch connected to said second loop filter and connected to a location on said first signal path between said data sampler access point and said first amplifier output, for Outputting a first branch current with a specific magnitude and direction to the first signal path based on the second control word to equalize signal data transmitted on the first signal path. 5. system as claimed in claim 4, is characterized in that, described data feedback equalization module also comprises tail equalizer, and described tail equalizer comprises: A third error detector, which is connected to a position after the access point of the first equalizing current source branch on the first signal path, and is used to detect the signal transmitted on the first signal path to obtain the second error detector. Three error signals; a third loop filter connected to the third error detector and configured to output a third control word based on the third error signal; A shift register array, which is connected to the clock and data recovery module, and is used to delay and shift the demodulated data; A second balancing current source branch connected to the third loop filter and the shift register array and connected to the third error detector and the first balancing current on the first signal path A position between source branch access points, for outputting a second branch current of a specific magnitude and direction to the first signal path based on the third control word and the output of the shift register array to balance all Signal data transmitted on the first signal path. 6. The system according to any one of claims 1-5, wherein the clock and data recovery module comprises: A lead-lag phase detector connected to the output of the clock and data recovery module for analyzing the final demodulated signal to obtain a lead/lag signal; a fourth loop filter, which is connected to the lead-lag phase detector, and is used to output a fourth control word based on the lead/lag signal; a phase interpolator, which is connected to the fourth loop filter and connected to the high-speed communication system, and is used to acquire the frequency-divided signal of the high-speed communication system and perform the frequency-division signal according to the fourth control word Make phase adjustments; A clock shaping buffer, which is connected to the phase interpolator, is used to acquire and output a corresponding square wave clock according to the phase-adjusted frequency-divided signal; a duty ratio adjuster, which is connected to the clock shaping buffer and is used to output a corresponding sampling clock according to the square wave clock; A sampling output unit, which includes a signal input terminal, a signal output terminal and a control terminal, wherein the control terminal is connected to the duty ratio regulator, and the signal input terminal and the signal output terminal are respectively the clock and the The input and output of the data recovery module, the sampling output unit is used to sample the input signal based on the sampling clock to obtain the final demodulated signal. 7. The system according to any one of claims 1-6, wherein the system also includes an analog-to-digital direct current elimination feedback module, and the analog-to-digital direct current elimination feedback module is installed on the data feedback equalization module and Between the clock and the data recovery module, it is used to eliminate the DC offset of the signal output by the data feedback equalization module. 8. The system according to claim 7, wherein the modulus direct current cancellation feedback module comprises: a second amplifier, the input of which is connected to the output of the data feedback equalization module; a second signal path, the input of which is connected to the output of the second amplifier, the output of which is connected to the input of the clock and data recovery module; a fourth error detector connected to the output of the second signal path for obtaining a fourth error signal based on the output signal of the second signal path; a fourth loop filter connected to the fourth error detector and configured to output a fifth control word based on the fourth error signal; a reference voltage generator, connected to the fourth loop filter and connected to the second signal path, for outputting a reference voltage to the second signal path based on the fifth control word to eliminate the first The DC offset of the signal transmitted on the second signal path. 9. The system according to claim 8, wherein the analog-to-digital DC cancellation feedback module further comprises a third amplifier connected between the reference voltage generator and the second signal path for amplifying and adjusting the reference voltage output by the reference voltage generator and outputting the amplified and adjusted reference voltage to the second signal path to eliminate DC offset. 10. The system according to any one of claims 7-9, wherein the analog-to-digital DC cancellation feedback module further comprises a DC offset detector, and the DC offset detector is used to detect the final demodulated signal Whether there is a DC offset in the system, so as to control the opening/closing of the analog-to-digital DC cancellation feedback module based on the detection result.