CN105529370A - A kind of MOS trigger negative resistance diode and its manufacturing method - Google Patents

Abstract

The invention relates to a semiconductor technology, in particular to an MOS-triggered dynistor (MOS-triggered Dynistor, MTD for short) and a manufacturing method thereof. The invention provides a normally closed MOS-triggered dynistor applied to the field of pulse power. Compared with a conventional MCT, the MTD provided by the invention comprises a P-type base region bump structure, which passes through an N-type source region and is connected with a cathode metal; and the cathode metal is connected with the N-type source region and the P-type base region bump structure to form a cathode short circuit, so that the device has normally closed characteristics; a drive circuit can be simplified; and the system reliability is improved. The MTD working mode is a PNPN dynistor mode; and the MOS-triggered dynistor has high peak current and current rise rate, and is very suitable for the field of the pulse power.

Description

A kind of MOS trigger negative resistance diode and its manufacturing method

technical field

The present invention relates to semiconductor technology, in particular to a MOS-Triggered Dynistor (MTD for short).

Background technique

Power semiconductor devices, as switching devices, can be used in the fields of power electronics and power pulses. The traditional thyristor (Thyristor) has the advantages of low conduction voltage drop, large voltage capacity, and high current density, which are very suitable for application in the field of power pulses. Since the advent of the thyristor, its related products have been widely used in power pulse and other fields. However, the thyristor is driven by current control, which increases the complexity of the system, reduces the reliability, and is not conducive to the miniaturization of the pulse power system.

An insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, referred to as: IGBT) is a device widely used in the field of power electronics. It is a voltage-controlled device with a simple structure and a mature and reliable manufacturing process. However, IGBT has current saturation capability, which limits its application in high power density. MOS Controlled Thyristor (MOS Controlled Thyristor, referred to as MCT) is a semiconductor device that combines the advantages of IGBT and thyristor. It has the advantages of voltage control drive, no current saturation characteristics and high power density, and is very suitable for high power applications. However, MCT is a normally-on device, which requires a negative voltage on the gate to maintain its off state. This not only increases the complexity of the system, but also brings potential danger to the system to a certain extent and reduces the reliability of the system.

Contents of the invention

The invention proposes a normally-off type MOS trigger negative resistance diode which is applied in the field of high voltage and high power and has the characteristic of simple driving.

The technical solution of the present invention: a MOS trigger negative resistance diode, including PNPN negative resistance diode parts and MOS parts arranged in parallel alternately, is characterized in that, the PNPN negative resistance diode part includes an N-type drift region 4, located in the N-type drift The P-type base region 3 on the upper surface of the region 4, the P-type anode region 5 located on the lower surface of the N-type drift region 4, and the N-type source region 1 located on the upper surface of the P-type base region 3, the lower surface of the P-type anode region 5 An anode 6 is connected, and the upper surface of the N-type source region 1 is connected to a cathode metal 7; the MOS part includes an N-type drift region 4, a P-type anode region 5 located on the lower surface of the N-type drift region 4, a gate structure and A P-type source region 10, the lower surface of the P-type anode region 5 is connected to an anode 6; the P-type source region 10 is located on the upper layer of the N-type source region 1 and is in contact with the gate structure; it is characterized in that the P-type The base region 3 penetrates the N-type source region 1 through the raised structure on its upper surface and then short-circuits with the cathode metal 7 .

Further, the P-type base region 3 is integrated with the raised structure on its upper surface.

Further, the P-type base region 3 is independent from the protruding structure on its upper surface, and the protruding structure is the P-type semiconductor region 2 .

Further, there are multiple protrusion structures.

Further, the gate structure of the MOS part is a trench gate structure or a planar gate structure.

A kind of manufacturing method of MOS triggered negative resistance diode, is characterized in that, comprises the following steps:

The first step: use the substrate silicon wafer to fabricate the junction terminal to form an N-type semiconductor drift region 4;

Step 2: using an ion implantation process to form a P-type base region 3 on the upper side of the N-type semiconductor drift region 4;

Step 3: making a gate structure on the other side of the upper layer of the N-type semiconductor drift region 4;

Step 4: Using an ion implantation process, fabricate an N-type source region 1 and a P-type source region 10 on the upper layer of the P-type base region 3; the P-type source region 10 is in contact with the gate structure; Fabricate a raised structure passing through the N-type source region 1 on the surface;

Step 5: Deposit a BPSG insulating dielectric layer on the upper surface of the device, and etch the ohmic contact hole;

Step 6: Deposit metal on the surface of N-type semiconductor source region 1 to form cathode metal 7;

The seventh step: depositing a passivation layer;

Step 8: Thinning and polishing the lower surface of the N-type semiconductor drift region 4, injecting P-type impurities and performing ion activation to form the anode region 5;

Step 9: Gold backing, forming an anode 6 at the bottom of the anode region 5 .

Further, in the fourth step, the specific method for making a raised structure passing through the N-type source region 1 on the upper surface of the P-type base region 3 is as follows:

The mask plate used when making the N-type source region 1 and the P-type source region 10 on the upper layer of the P-type base region 3 has a shielding area, and the part of the P-type semiconductor base region 3 covered by the shielding region is not implanted with N-type impurities, so that A raised structure of the P-type base region 3 connected to the cathode metal 7 through the N-type source region 1 is formed.

Further, in the fourth step, the specific method for making a raised structure passing through the N-type source region 1 on the upper surface of the P-type base region 3 is as follows:

After making N-type source region 1 and P-type source region 10 on the upper layer of P-type base region 3, continue to implant P-type impurities on N-type source region 1 to form P Type semiconductor region 2.

The invention has the beneficial effects of proposing a normally-off MOS trigger negative resistance diode and a manufacturing method thereof which are applied in the field of high voltage and high power and are simple to drive.

Description of drawings

Fig. 1 is a schematic diagram of a conventional MCT cell structure;

Fig. 2 is a schematic diagram of the structure of a MOS trigger negative resistance diode trench gate cell in the present invention;

Fig. 3 is a schematic diagram of the planar grid cell structure of the MOS trigger negative resistance diode of the present invention;

Fig. 4 is a schematic diagram of another trench gate cell structure of the MOS trigger negative resistance diode of the present invention;

Fig. 5 is a schematic diagram of another planar grid cell structure of the MOS trigger negative resistance diode of the present invention;

Fig. 6 is a schematic diagram of the raised structure of the P-type base region produced by the planar gate cell of the MOS trigger negative resistance diode of the present invention;

Fig. 7 is a schematic diagram of another planar gate type cell of the MOS trigger negative resistance diode of the present invention to make a P-type raised area;

8 is a schematic diagram of an equivalent circuit of a MOS trigger negative resistance diode of the present invention;

Fig. 9 is a schematic diagram of a forward blocking characteristic curve of a MOS trigger negative resistance diode of the present invention and a conventional MCT;

10 is a schematic diagram of the conduction characteristic curves of MOS trigger negative resistance diodes (different N-type source region lengths) and conventional MCTs of the present invention;

Fig. 11 is a schematic diagram of a strip-shaped cell layout of a MOS trigger negative resistance diode of the present invention;

Fig. 12 is a schematic diagram of a square cell layout of a MOS trigger negative resistance diode of the present invention;

Fig. 13 is a schematic diagram of a hexagonal cell layout of the MOS trigger negative resistance diode of the present invention;

Fig. 14 is a schematic sectional view along the section line AA' of Fig. 11/12/13;

Fig. 15 is a schematic cross-sectional view along the section line BB' in Fig. 11 .

detailed description

The present invention is described in detail below in conjunction with accompanying drawing

The MOS trigger negative resistance diode planar gate cell structure provided by the present invention is as shown in Figure 2, comprises MOS part and PNPNDynistor (negative resistance diode), and its MOS part provides driving current for PNPN negative resistance diode part, within tens of nanoseconds The entire device is quickly triggered to turn on, so that the device obtains high current capability. The PNPN negative resistance diode part has a cathode short-circuit structure composed of N-type source region 1, P-type base region 3 protrusion structure and cathode metal 7, so that the device has a normally-off characteristic. The raised structure of the P-type base region 3 and the P-type base region 3 can be set independently of each other, as shown in FIG. 4 and FIG. 5 .

In the MOS trigger negative resistance diode provided by the present invention, its MOS part can be set as a trench gate and a planar gate. The cell structure of the trench gate MTD is shown in Figure 2 and Figure 4, and the structure of the planar gate MTD cell is as follows: As shown in Figure 3 and Figure 5; its anode structure is similar to that of various existing MCT anode structures.

The MOS trigger negative resistance transistor provided by the present invention has the following working principle:

In the cellular structure shown in Figure 2, when the positive voltage is applied to the anode, and the cathode and the gate are connected to zero potential, the P-N junction between the drift region 4 and the P-type base region 3 is reversely biased, and the resulting PN junction is reversed. The leakage current flows through the P-type base region 3 and is extracted by the raised structure of the P-type base region 3, and a lateral voltage drop is generated on the P-type base region 3. The reverse leakage current of the PN junction is very small, and in the P-type base region 3 The lateral voltage drop generated above is much smaller than the PN junction barrier voltage formed by the N-type source region 1 and the P-type base region 3, which is not enough to turn on the PNPN negative resistance diode part. At this time, the device exhibits a normally-off characteristic, and its withstand voltage effect is equivalent to that when a negative potential is applied to the gate.

Add positive potential to the gate in Figure 1 to make the channel under the gate conduct, add zero potential to the cathode, and add positive voltage to the anode. At this time, the electrons generated in the MOS part flow into the drift region 4 through the channel under the gate to provide base drive current for the PNP transistor composed of the P-type base region 3 , the drift region 4 and the anode 5 . The driven current is extracted by the raised structure through the P-type base region 3 . Due to the large current, the lateral voltage drop generated in the P-type base region 3 quickly exceeds the PN junction barrier voltage, triggering the partial opening of the PNPN negative resistance diode close to the MOS region, and the opened part rapidly diffuses to the The entire PNPN negative resistance diode makes the device have high current capability and high current rise rate. The equivalent circuit of the MTD is shown in Figure 8.

The MOS trigger negative resistance diode provided by the present invention takes the planar grid cell structure shown in Figure 1 as an example, and its manufacturing steps are as follows:

The first step: use the substrate silicon wafer to fabricate the junction terminal to form an N-type semiconductor drift region 4;

Step 2: injecting P-type impurities, push junction diffusion to form P-type base region 3;

Step 3: Thermally grow a gate oxide layer 9 on the surface of the substrate and deposit polycrystalline to form gate polycrystalline 8;

Step 4: Etch the gate oxide layer and polycrystalline layer on the surface of the substrate, and use self-alignment process to form N-type source region 1 and P-type source region 10 respectively; on P-type base region 3, fabricate through N-type source region 1 raised structure;

Step 5: Deposit a BPSG insulating dielectric layer on the upper surface of the device, and etch the ohmic contact hole;

Step 6: Deposit metal on the surface of N-type semiconductor source region 1 to form cathode metal 7;

The seventh step: depositing a passivation layer;

Step 8: Thinning and polishing the lower surface of the N-type semiconductor drift region 4, injecting P-type impurities and performing ion activation to form the anode region 5;

Step 9: Gold backing, forming an anode 6 at the bottom of the anode region 5 .

The simulation comparison between the MCT with a withstand voltage of 1400V and the MTD of this example shows that the performance of the present invention is improved compared with the MCT, a voltage-controlled device widely used in the field of pulse power. As shown in Figure 9, when the gate voltage is equal to 0V, the MTD in this example has a withstand voltage of more than 1400V, while the MCT cannot maintain its blocking state, and its withstand voltage is 0V. When the gate voltage is equal to -10V, the conventional MCT has a withstand voltage of 1400V, which is equivalent to the MTD of the present invention. The MTD of the present invention has a normally-off characteristic, making its drive simpler than that of a normally-on MCT.

When the device is turned on, as shown in Figure 10, the MOS trigger negative resistance transistor in this example has a negative resistance region in the process of gradually increasing the anode voltage, which is due to the PN junction formed by the P-type base region 3 and the N-type source region 1 caused by gradual opening. After passing through this negative resistance region, its current characteristics are similar to those of conventional MCTs, with a large current density. It can be seen that the introduction of the raised structure in the P-type base region 3 will not affect the current capability of the MTD.

The schematic diagrams of the cell layout of the MOS trigger negative resistance diode of the present invention are shown in Figure 11, Figure 12 and Figure 13, wherein Figure 11 is a strip cell layout, Figure 12 is a square cell layout, and Figure 13 is a hexagonal cell layout . Fig. 14 is a schematic cross-sectional view according to the section line AA' of Fig. 11/12/13, and Fig. 15 is a schematic cross-sectional view according to the section line BB' of Fig. 11. Wherein, the P-Well boundary refers to the actual boundary of the P-type base region 3 after considering the lateral diffusion. The N-source boundary is the actual boundary of the N-type source region 1 after considering lateral diffusion, and the window of the N-type source region 1 is the same as the window of the P-type source region 10 .

Claims (8)

1. a kind of MOS triggers negative-resistance diode, comprises the PNPN negative-resistance diode part and the MOS part that are arranged side by side alternately, it is characterized in that, described PNPN negative-resistance diode part comprises N-type drift region (4), is positioned at N-type drift region ( 4) P-type base region (3) on the upper surface, P-type anode region (5) on the lower surface of the N-type drift region (4), and N-type source region (1) on the upper surface of the P-type base region (3) , the lower surface of the P-type anode region (5) is connected with an anode (6), and the upper surface of the N-type source region (1) is connected with a cathode metal (7); the MOS part includes an N-type drift region (4) , a P-type anode region (5) located on the lower surface of the N-type drift region (4), a gate structure and a P-type source region (10), and the lower surface of the P-type anode region (5) is connected to an anode (6); The P-type source region (10) is located on the upper layer of the N-type source region (1) and is in contact with the gate structure; it is characterized in that the P-type base region (3) penetrates the N-type base region (3) through a raised structure on its upper surface. The type source region (1) is short-circuited with the cathode metal (7). 2. A MOS trigger negative resistance diode according to claim 1, characterized in that the P-type base region (3) is integrated with the raised structure on its upper surface. 3. A kind of MOS triggered negative-resistance diode according to claim 1, characterized in that, the P-type base region (3) is independent from the protruding structure on its upper surface, and the protruding structure is P-type semiconductor region (2). 4. A MOS trigger negative resistance diode according to claim 2 or 3, characterized in that there are a plurality of said raised structures. 5 . The MOS trigger negative resistance diode according to claim 4 , wherein the gate structure of the MOS part is a trench gate structure or a planar gate structure. 6. A manufacturing method of MOS trigger negative resistance diode, is characterized in that, comprises the following steps: The first step: using the substrate silicon wafer to make a junction terminal to form an N-type semiconductor drift region (4); Step 2: using an ion implantation process to form a P-type base region (3) on the upper side of the N-type semiconductor drift region (4); Step 3: making a gate structure on the other side of the upper layer of the N-type semiconductor drift region (4); Step 4: using an ion implantation process to fabricate an N-type source region (1) and a P-type source region (10) on the upper layer of the P-type base region (3); the P-type source region (10) is in contact with the gate structure; At the same time, a raised structure passing through the N-type source region (1) is formed on the upper surface of the P-type base region (3); Step 5: Deposit a BPSG insulating dielectric layer on the upper surface of the device, and etch the ohmic contact hole; Step 6: Depositing metal on the surface of the N-type semiconductor source region (1) to form a cathode metal (7); The seventh step: depositing a passivation layer; Step 8: Thinning and polishing the lower surface of the N-type semiconductor drift region (4), injecting P-type impurities and performing ion activation to form the anode region (5); Step 9: gold backing, forming an anode (6) at the bottom of the anode region (5). 7. A method for manufacturing a MOS trigger negative resistance diode according to claim 6, characterized in that in the fourth step, the upper surface of the P-type base region (3) is made to pass through the N-type source region (1) The specific method of the convex structure is: The mask plate used when making the N-type source region (1) and the P-type source region (10) on the upper layer of the P-type base region (3) has a shielding area, and the part of the P-type semiconductor base region (3) covered by the shielding region Not implanted with N-type impurities, thereby forming a raised structure of the P-type base region (3) passing through the N-type source region (1) and connected to the cathode metal (7). 8. The manufacturing method of a kind of MOS triggered negative resistance diode according to claim 6, characterized in that, in the fourth step, the upper surface of the P-type base region (3) is made to pass through the N-type source region (1 ) The specific method of the raised structure is: After fabricating the N-type source region (1) and the P-type source region (10) on the upper layer of the P-type base region (3), continue to implant P-type impurities on the N-type source region (1) to form a penetrating N-type source region (1) and a P-type semiconductor region (2) connected to the P-type base region (3).