CN105518892A - Nonvolatile Memory Devices Using Thin Film Transistors and Schottky Diodes - Google Patents

Abstract

An improved cross-point memory array device is introduced that includes a plurality of memory cells. Each memory cell is disposed at an intersection region of conductive lines, wherein one of the first conductive lines is electrically coupled at a first terminal and one of the second conductive lines is electrically coupled at a second terminal. Each conductive line is electrically coupled to at least two Thin Film Transistors (TFTs) that provide access to the memory cells. Each memory cell includes a resistance that is controllable using a back-to-back schottky diode positioned between each memory cell and one of the conductive lines. The device is essentially manufactured in a BEOL facility without the need for front-end semiconductor production facilities, but can still be made with ultra-high density and low cost.

Description

Nonvolatile Memory Devices Using Thin Film Transistors and Schottky Diodes

Cross references to related applications:

This application claims priority from Provisional Patent Application Serial No. 61/699,211 having a filing date of September 10, 2012 and Provisional Patent Application Serial No. 61/702,485 having a subsequent filing date.

Federally funded research: None.

Sequence Listing: None.

prior art literature

US Patent Application Publication 2012/0281465, filed November 8, 2012 by Agan et al.

US Patent Application Publication 2012/0257449 filed October 11, 2012 by Agan et al.

Kim's US Patent No. 6,750,540, filed June 15, 2004.

US Patent No. 5,640,343, filed June 17, 1997 by Gallagher et al.

US Patent No. 7,224,601 filed May 29, 2007 by Panchula.

US Patent No. 7,529,121 filed May 5, 2009 by Kitagawa et al.

US Patent No. 6,838,721, filed January 4, 2005 by Garni et al.

U.S. Patent No. 7,668,005 filed February 23, 2010 by Ueda.

US Patent Application Publication 2010/0213458 filed Aug. 26, 2010 by Prall.

US Patent No. 8,411,494 filed April 2, 2013 by Shukh.

US Patent No. 8,227,788, filed July 24, 2012 by Mikawa et al.

US Patent No. 7,608,514, filed October 27, 2009 by Hsu et al.

US Patent No. 7,968,419 filed June 28, 2011 by Li et al.

US Patent No. 8,289,746 filed October 16, 2012 by Chen et al.

US Patent Application Publication 2012/0224417 filed September 6, 2012 by Wang et al.

US Patent Application Publication 2013/0044532, filed February 21, 2013 by Bethune et al.

US Patent Application Publication 2013/0223125 filed August 29, 2013 by DeBrosse et al.

technical field

The present disclosure relates to non-volatile memory arrays and devices; more particularly, to cross-point memory arrays employing back-to-back Schottky diodes at memory cells and thin-film transistors as selection elements, enabling low-cost three-dimensional memory arrays for A separate memory device or embedded memory on a chip.

Explanation of reference signs, text and abbreviations

12 pinned (or reference) magnetic layer

14 tunnel barrier layer

16 free (or storage) magnetic layers

18 Amorphous semiconductor layer

Array of 22 memory cells

24-bit line driver

26 word line drivers

28 source line drivers

30 Magnetic Random Access Memory (MRAM) Arrays

60 silicon substrate

61CMOS circuit layer

62 interconnect layers

63 MTJ layers including MTJ elements, back-to-back Schottky diodes and wires

64 thin film transistor (TFT) layers

65 interconnect

66 word wires – shared by both MTJ layers

70 glass substrate

80 wires, representing bit lines or word lines

81 for the area of thin film transistors

82 interconnects between wires and thin film transistors

BBSD - Back to Back Schottky Diodes

BL, BL1, BL2, BL3...BLN bit lines

C, C11-C33...CNM memory cells

Fm is the minimum feature size of the technology node for the MTJ layer (including MTJ, wire, and BBSD)

Ft Minimum feature size of the technology node for the TFT layer

Fc is the minimum feature size of the technology node for the CMOS circuit layer

J, J11-J33 magnetic tunnel junction

K, K11-K33....KNM (Memory Element) Magnetic Tunnel Junction and Semiconducting Layer Including Part of Back-to-Back Schottky Diodes

M - the number of word lines in the memory array

N - the number of bit lines in the memory array

MTJ - Magnetic Tunnel Junction

SA1-SA3...SAM sense amplifiers

TFT-Thin Film Transistor

Tb1–Tb6...Tb(Nx2) bit line transistors

Ts1–Ts3...TsM read transistors

Tw1-Tw6, ...Tw(Mx2) word line transistors

WL, WL1, WL2, WL3...WLM word lines

Background technique

Nonvolatile cross-point memory technologies such as resistive random access memory (ReRAM) and magnetic random access memory (MRAM) using magnetic tunnel junctions (MTJs) are used to provide dense and fast nonvolatile promising candidates for volatile storage schemes.

A conventional MTJ comprises at least one pinned ferromagnetic layer and one free ferromagnetic layer separated from each other by a thin tunnel barrier layer. The free layer has a reversible magnetization direction that can have two stable directions parallel or antiparallel to the fixed magnetization direction of the pinned layer. The resistance of an MTJ depends on the mutual orientation of the magnetizations in the free and pinned layers and can be effectively controlled.

A typical MRAM device includes an array of memory cells, a plurality of parallel word lines extending along the columns (or rows) of memory cells, and a plurality of parallel bit lines extending along the rows (or columns) of memory cells. The word lines and bit lines overlap each other but are spaced apart from each other in the vertical direction. Each memory cell is located at the intersection of a word line and a bit line, and typically includes a single MTJ connected in series with a select metal-oxide-semiconductor (MOS) transistor. The series connected MTJ and transistor are electrically coupled at one terminal to a word line and at an opposite terminal to a bit line.

Figure 1 shows a circuit diagram for a Magnetic Random Access Memory (MRAM) array according to the prior art disclosed in US Patent Application Publication US2012/0281465. US Patent Application Publication US2012/0281465 discloses in detail various methods of writing bits ("0" and "1") to memory cells, and reading and erasing bits. The disclosure of US2012/0281465 is incorporated herein by reference in its entirety.

Figure 2 shows a cross-sectional view of a magnetic memory cell made with perpendicular magnetic material according to the prior art.

The circuit described by US2012/0281465 presents a challenge for controlling the addressing of a memory array for writing, reading or erasing due to the fact that alternative current paths are possible compared to those described in the publication . This problem is also described in patent numbers US7,968,419 and US8,227,788, which teach the use of back-to-back Schottky diodes in a resistive memory array to solve the crosstalk problem associated with reading from the array. FIG. 3 is a circuit diagram of a cross-point resistive nonvolatile memory array including resistance change elements 105 having back-to-back Schottky diodes (referred to as current steering elements) 112 according to US Pat. No. 8,227,788. Word and bit conduction lines are indicated at 101 and 119 .

US2012/0281465 describes the location of select transistors positioned along the perimeter of the array which still requires a considerable die area. Transistors The use of MOSs as selection elements limits the arrangement of existing MRAMs into three-dimensional configurations due to the longer interconnects from the far layers of the MTJ to the selection transistors. Furthermore, MOS technology is relatively expensive.

There is a need for an improved method of addressing word select transistors and bit select transistors in MRAM memory arrays that maintains the advantages of small die size due to the memory array cross point design, and eliminates the need for MOS transistors, which together enable lower cost.

The present application solves the above-mentioned problems and provides a solution for a low-cost three-dimensional non-volatile cross-point memory array.

Contents of the invention

The improved memory device includes a substrate; a plurality of memory arrays arranged above the surface of the substrate, each memory array is arranged in a matrix, and includes a plurality of parallel first conductive lines, overlapping with the first conductive lines at a plurality of intersection regions a plurality of parallel second conductive lines; a plurality of memory cells, each memory cell arranged at an intersection region of said conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the first conductive lines at a second terminal a second wire; and including a controllable resistance; wherein back-to-back Schottky diodes are located between each memory cell and one of the wires, and wherein each wire is electrically coupled to at least two thin film transistors (TFTs). The device is basically fabricated in BEOL facilities without the need for front-end semiconductor production facilities, and can also be fabricated in an ultra-high-density and low-cost manner. Furthermore, the device can be fabricated as an embedded memory on a layer directly above a semiconductor circuit (such as in an ASIC, FPGA, or microprocessor chip), which provides even lower cost and easy, fast access to non-volatile memory without leaving the chip. TFTs can be fabricated in single-layer or multi-layer arrays, which gives designers flexibility for optimizing cost, performance, or other design goals.

A magnetic tunnel junction (MTJ) element referred to herein within the scope of the present specification and claims is a generic term for tunnel magnetoresistive elements using an insulator or a semiconductor as a tunnel barrier layer. Although the above figures illustrate the main components of an MTJ element, another layer (or layers) may also be included, such as a seed layer, a pinning layer, a capping layer, and others.

The use of back-to-back Schottky diodes in nonvolatile memory arrays for Resistive Random Access Memory (ReRAM) was disclosed by Mikawa (US Patent 8,227,788) and Li (US Patent 7,968,419), and by Agan through inventor (Agan ) used back-to-back Schottky diodes in a non-volatile memory array for Magnetic Random Access Memory (MRAM) in co-pending patent application Ser. No. 61/702,485. The disclosures of US Patents 8,227,788 and 7,968,419 and US Patent Application 61/702,485 are hereby incorporated by reference in their entirety. Back-to-back Schottky diodes are metal/semiconductor/metal (MSM) structures, usually made of silicon (Si) semiconductor material, but other semiconductor materials such as zinc oxide (ZnO) or indium gallium zinc oxide (IGZO) can be used. Back-to-back Schottky diodes have a threshold voltage, a breakdown voltage, and an on/off current ratio.

FIG. 6 shows a circuit diagram of a portion of a cross-point MRAM array 30 according to an embodiment of the disclosure. The memory comprises an array 22 of memory cells C11-CNM, a plurality of parallel bitlines BL1-BLN connected at their ends to a bitline driver 24, and a plurality of parallel bitlines BL1-BLN connected at their ends to a wordline driver 26. Word lines WL1-WLM.

Each memory cell includes MTJ elements and back-to-back Schottky diodes (BBSDs) without select transistors. The MTJ elements and the semiconductor layers of the BBSD (together labeled K) are connected at their ends to appropriate bit and word lines and are arranged at line intersection regions in the vertical space between them. Representative schematic diagrams of memory cells of MRAM 30 are shown in FIGS. 4A and 4B . The MTJ element J has a columnar structure and includes at least one pinned magnetic layer 12 with a fixed magnetization direction (shown by solid arrows), a free A magnetic layer 16, and a tunnel barrier layer 14 disposed between the pinned magnetic layer and the free magnetic layer. A semiconductor material 18 such as silicon (Si) is disposed between the word line WL and the free magnetic layer 16; the metal-semiconductor-metal (MSM) structure is a back-to-back Schottky diode, BBSD.

The free magnetic layer 16 may be made of a magnetic material with substantial spin polarity, and in its equilibrium state has a magnetization directed generally perpendicular to the layer surface. For example, the free magnetic layer 16 may be made of a (Co ₃₀ Fe ₇₀ ) ₈₅ B ₁₅ (atomic %) alloy having a thickness of about 1.5 nm. The pinned magnetic layer 12 may be made of a magnetic material with substantial spin polarity, and with a magnetization directed generally perpendicular to the layer surface. For example, the pinned magnetic layer may be made of a (Co ₃₀ Fe ₇₀ ) ₈₅ B ₁₅ (atomic %) alloy having a thickness of about 2.5 nm. The tunnel barrier layer 14 may be made of MgO having a thickness of about 1.1 nm. The free layer, the tunnel barrier layer and the pinned layer form a substantially coherent texture having a BCC (Body Centered Cubic) structure with a (001) plane orientation. MTJ elements with this crystal structure provide considerable tunneling magnetoresistance (TMR>100% at room temperature) and spin-polarized write current densities of about 1·10 ⁶ A/cm ² or less. These parameters are essential for MRAM.

In the MRAM 30 shown in FIG. 6, a plurality of conductive bit and word lines intersect each other but are spaced apart from each other in a direction perpendicular to the plane of the substrate (not shown). Each of the memory cells C11-CNM includes a suitable MTJ element and semiconductor layer (K11-KNM) with bit and word lines arranged in the vertical space between them at the intersection area. The memory element K is electrically connected at its opposite ends to intersecting bit lines and word lines. For example, the memory cell C22 includes the memory element K22 arranged at the intersection area of the bit line BL2 and the word line WL2. Memory element 22 is connected at its first end to word line WL2 and at its second end to bit line BL2.

The bit lines BL1-BLN extend in the X direction. They are electrically connected to a bit line driver 24, which includes transistors Tb1-Tb(Nx2), which may be CMOS transistors or thin film transistors (TFTs). Each bit line is connected to two transistors that control the magnitude and direction of the current flow. Although FIG. 6 schematically shows the bitline driver 24 transistors connected at the ends of the bitlines BL1-BLN, this is not required, and in particular, it is preferable to provide bitline drivers at various points along the bitlines. Physical interconnections between BL1-BLN and bit line driver transistors Tb1-Tb(Nx2) in order to minimize the interconnection complexity of the device. This is an important aspect of the invention, enabling the interconnection of small technology node bit lines to larger technology node transistors disposed above or below the entire area of the memory array. Shorter interconnects are preferred as they enable higher speed operation.

The bit drivers 24 operate as row select switches. The bit drivers 24 and associated transistors are connected by signal lines (not shown) to the bandgap and decoder logic, which includes additional transistors that may or may not be on the same layer as the bitline transistors. Preferably, the decoder logic and bandgap transistors are on the same layer as the associated bit driver transistors in order to provide shorter interconnects and thus higher speed operation and lower cost due to simpler construction.

The word lines WL1-WLM extend in the Y direction crossing the X direction. Each wordline WL1 - WL3 is connected to a wordline driver 26 . Although FIG. 6 schematically shows wordline driver 26 transistors connected at the ends of wordlines WL1-WLM, this is not required, and in particular, it is preferred to provide The physical interconnection between wires WL1-WLM and wordline driver transistors Tw1-Tw(Mx2) in order to minimize the interconnection complexity of the device. This is an important aspect of the invention, enabling the interconnection of small technology node word lines to larger technology node transistors disposed above or below the entire area of the memory array. Shorter interconnects are preferred as they enable higher speed operation.

The driver 26 includes a plurality of read/write circuits. Each of the read/write circuits includes at least one pair of transistors Tw1-Tw(Mx2) connected in series to each other, and one of the sense amplifiers SA1-SAM. Each word line WL1-WLM is connected to two transistors that control the magnitude and direction of the current. The word line is also connected to the common drain terminal of the pair of transistors and to one input of the sense amplifier SA through the read transistor T _S . For example, the word line WL2 is connected to the common drain terminal formed on the transistor pair Tw3 and Tw4 through the read transistor Ts2 and to the first input terminal of the sense amplifier SA2. A second input terminal of the sense amplifier SA2 is connected to a reference element (not shown). The gates of the transistors Tw1 - Tw ( Mx2 ) are connected to a word line driver 26 . The word driver 26 operates as a column selection switch. The word driver 26 and associated transistors are connected by signal lines (not shown) to the bandgap and decoder logic, which includes additional transistors that may or may not be on the same layer. Preferably, the decoder logic and bandgap transistors are on the same layer as the associated word driver transistors to provide shorter interconnects and thus higher speed operation and lower cost due to simpler construction.

Each of the sense amplifiers SA1-SAM includes at least two inputs. One input of the amplifier is connected to the word lines WL1-WLM and the common drain terminal of the pair of transistors through read transistors Ts1-TsM. The other input of the sense amplifier is connected to a reference element (not shown). The sense amplifier judges the data value of the MTJ element inside the selected memory cell based on the reference signal.

The memory 30 shown in FIG. 6 comprises an array 22 of memory elements K11-KNM arranged over the substrate (not shown). Select transistors Tb1-Tb(Nx2) and Tw1-Tw(Mx2) may be located along the perimeter of array 22, but are preferably fabricated on another layer above or below the memory array, and are located across the entire area of the array to minimize complexity of interconnecting devices. This enables multiplexing of very large size MxN memory arrays. This approach, which involves layering several memory arrays and thin-film transistor (TFT) arrays in three dimensions, optimizes chip area and provides maximum storage density in terms of bits per area.

Larger size TFTs made with larger technology node Ft relative to MTJ layer technology node Fm provide cost savings as such process equipment is significantly lower in cost than would be required for CMOS transistors . Even within the field of TFT transistor production, processing of larger technology nodes is less costly than processing of smaller technology nodes. Larger transistors can also provide the significant write current necessary for high speed writing.

The MRAM 30 shown in FIG. 6 employs a spin-induced switching mechanism of the memory element K. As shown in FIG. According to spin-induced switching, the magnetization orientation in the free layer 16 can be reversed by means of a spin-polarized current _Is (not shown) flowing through the memory element. The electrons writing the current have a considerable degree of spin polarization predetermined by the magnetic properties of the pinned layer 12 . The transfer of spin-polarized electrons flowing through the free layer 16 causes its spin-torque of the magnetization in the free layer to change the direction of the spin-polarized electrons. The direction of magnetization in the free layer 16 can be controlled by means of the direction of the spin-polarized current Is flowing through the memory element. The direction of the spin-polarized current in the memory element corresponds to writing a logic "0" or to a parallel orientation of the magnetization directions in the free magnetic layer 16 and the pinned magnetic layer 12 .

To write a logic "0" to a memory element (e.g. K22 of memory cell C22), a switching current Is is generated in the memory element by applying an appropriate input signal to the gate of transistor Tb4 and to the gate of transistor Tw3 (not shown). Both transistors are turned on. The spin polarized current Is flows from a power supply (not shown) through transistor Tb4, bit line BL2, memory element K22, word line WL2, and transistor Tw3 to ground. For the memory element having the configuration shown in FIG. 4A , the current Is flows through the tunnel barrier layer 14 in the direction from the free layer 16 to the pinned layer 12 . The spin-polarized conduction electrons move in the opposite direction from the pinned layer 12 to the free layer 16 . For a given direction of current Is, the magnetization in the free layer 16 will point parallel to the magnetization direction of the pinned layer 12 . This mutual orientation of the magnetizations corresponds to the low resistance state of the memory element or to a logic "0". In order for this operation to occur, a minimum threshold voltage is required due to the back-to-back Schottky diode (BBSD) structure.

To write a logic "1" to a memory element (such as K22 of memory cell C22), a write current Is (not shown) is supplied to the memory element by applying an appropriate input signal to the gates of transistors Tb3 and Tw4 K22. The transistor is turned on, and current Is flows from transistor Tw4 through word line WL2, memory element K22, and bit line BL2 to transistor Tb3. In the memory element K22 having the configuration shown in FIG. 4A , the spin-polarized current Is flows in the direction from the pinned layer 12 to the free layer 16 . This orientation of the spin-polarized current directs the magnetization in the free layer 16 antiparallel to the magnetization direction of the pinned layer 12 . This mutual orientation of the magnetizations corresponds to a high resistance state or to a logic "1". In order for this operation to occur, a minimum threshold voltage is required due to the back-to-back Schottky diode (BBSD) structure.

A major advantage of using TFTs is that multilayer memory arrays can be fabricated with TFT layers between such memory layers to provide very high density memory devices.

With respect to digital integrated circuits, process technology refers to the specific method used to make a silicon chip. The driving force behind the manufacture of integrated circuits is miniaturization, and process technology boils down to the size of finished transistors and other components. A specific feature size of a process technology is also called a "technology node" or "process node". High-density memory arrays can use cross-point architectures and can be fabricated at smaller sized technology nodes. The state of the state of the art process technology nodes has also evolved from 1,000nm in 1985 to 180nm in 1999, 45nm in 2008, 22nm in 2012, and hopefully 2014 as technology improves in semiconductor processing. 14nm on the line. By 2020, the 7nm process technology node is expected to be available.

A major advantage of the present invention is that the technology nodes used to fabricate the memory array (MTJ layer) and the TFT array (TFT layer) are decoupled. In other words, depending on the desired function of the TFT layer, one can fabricate the TFT using the same technology node (e.g. 45nm) used to fabricate the MTJ layer, or preferably, in order to reduce costs and given the fact that compared to The number of memory elements (M×N), the number of TFTs required ((2×N)+(3×M)) is significantly smaller, and larger technology nodes (e.g., 65nm , 90 nm, 130 nm or even larger). In addition, there is no need to place TFTs along the perimeter of the memory array as disclosed in US2012/0281465; instead, TFTs are fabricated directly above or below the memory array to be addressed. The interconnection of the TFTs to their corresponding wires is done vertically without the need for complex lateral interconnections. TFT does not require the front-end process equipment required in MOS foundry. Therefore, the cost of TFTs is significantly lower compared to MOS-based transistors. Eliminating the need for MOS-based transistors allows the use of low-cost glass substrates.

The selection thin film transistor may be disposed above or below the magnetic tunnel junction (or junction). The gate width of the select transistor can be significantly larger than the width (or diameter) of the magnetic tunnel junction. The memory cell has a transistor-several magnetic tunnel junction (IT-nMTJ) arrangement. The magnetic tunnel junctions are commonly electrically connected at their first ends to the select transistors and are individually electrically coupled at their second ends to a suitable conductor (bit line or word line). Data can be recorded to the magnetic tunnel junction by a spin-induced switching mechanism or by a hybrid switching mechanism involving the simultaneous action of a spin-polarized current and a bias magnetic field applied to the magnetic tunnel junction.

Figure 10 is a top view showing wires (or bit lines or word lines) interconnected at various intermediate points to allow easy connection to a large array of transistors formed across a larger area. The figure is to convey the fact that although the area required to fabricate a TFT is much larger than that of a memory cell, the TFT can be placed across the area above or below the MTJ layer such that at the Fm technology node Interconnects between fabricated wires are connected to TFT terminals fabricated at the Ft technology node without complex lateral interconnect routing. TFT terminations only need to be connected at a portion of the wires and the TFTs are arranged in such a way as to minimize disconnections due to alignment challenges due to the process technology nodes used to fabricate the TFTs compared to the MTJ layer. Layers are much larger process technology nodes creating alignment challenges.

11A and 11B further illustrate the advantages of the present invention with regard to process technology node (Fm and Ft) decoupling during fabrication of memory array layers including BBSD and wires, (MTJ layer) and TFT array (TFT layer). As described in the examples below, there are many configurations in which the designer may choose to place transistors on the various TFT layers disclosed herein. 11A and 11B are only for one configuration, that of the third embodiment, in which a single-layer TFT array may have at least 2N transistors to provide bit driver circuits for the MTJ layer.

A typical size (area) for a TFT is 12 Ft ² (T). The size (area) of the cross-point memory cell is 4Fm ² . For a given matrix or memory block comprising MxN cells (bits), the required area is ^MxNx4Fm2 . In order to take into account the required area on the TFT layer interconnected to the bit wires, 2*N TFTs (select transistors) are required. The area required for the TFTs (assuming each TFT is a typical area of 12Ft ² ) is equal to 24Ft ² ×N. Calculating the equivalent area for the MTJ layer and the TFT layer provides the maximum value Ft for a given matrix of M word lines at a given Fm technology node for the memory cell. therefore,

Since M×N×4Fm ² (MTJ layer area)=24Ft ² ×N (TFT layer area),

This yields the square root of Ft(max)=(M×Fm ² /6).

For example, if Fm=45 nanometers and a matrix of 100 word lines, then the maximum value Ft=184 nanometers. Assuming M=N, a 100 x 100 (10 megabits) memory block would occupy a square area of approximately 9 microns x 9 microns. As noted, it is preferred to also include transistors for decoder logic and bandgap logic close to the select transistors. Therefore, a designer may choose Ft = 130 nm (approximately 288% x Fm), which provides twice the number of transistors in the same space as Ft = 184 nm. It should be noted that in practice 184 nm is not a usable process technology node; however, 180 nm is a usable process technology node. The intent of Figures 11A and 11B is to show how by decoupling the technology nodes required for the MTJ layer from the TFT layer, the designer is given a wide range of flexibility to choose the technology node that is optimal for the product design. Important parameter - be it cost, speed, density or power. Holding Fm = 45 nm, if M = 1,000 (assuming M = N 1 Mbit memory blocks), then the maximum value is Ft = 581 nm (>1000% x Fm).

The 45nm process technology node was introduced in 2008. If one observes Fm = 7nm (a technology node expected to be available by 2020) and M = 10,000, then Ftmax = 286nm (assuming ^12Ft2 of TFT area remains typical size). If it is assumed that M=N, the memory block will have 100 megabits, occupying an area of 140 microns by 140 microns. That equates to about 400 gigabytes per square inch. With five (5) MTJ layers, substantially 2 terabytes per square inch devices can be fabricated in a BEOL facility, where word and bit driver select transistors, read transistors, and encoder logic transistors are included, and Made at low-cost technology nodes of 180nm or 130nm.

It should be noted herein that the term "TFT layer" and TFT-L1, TFT-L2, TFT-L3...TFT-Ln used herein in the figures and examples may refer to a single-layer TFT array or several layers TFT array. The calculations of Figures 11A and 11B assume a single-layer TFT array. However, more than one layer of TFTs can be designed and fabricated, which would allow the use of larger technology nodes compared to single layer TFT arrays. Alternatively, the same technology node but a multi-layer TFT provides a greater number of transistors that can be placed within a given area. This allows for flexibility in design. For example, FIG. 11B shows that even at a relatively small-sized memory array (M=10), the maximum value, Ft, is greater than Fm, indicating that for even small-sized memory arrays, the TFT drive circuit can reside in the same area of the memory array. above or below. This can be done with the same technology node for Fm as used for Ft or with a technology node slightly larger than that for Fm, or one can add one or more additional layers of TFT, which will The technology node requirements will be relaxed and enable the fabrication of larger and lower cost technology node TFTs. This may be advantageous for some embedded memory designs. The metal layer interconnect design between the TFT layers and the connections between the TFT terminations and the wires of the MTJ layer are known techniques, therefore the drawings and descriptions herein are intended to be illustrative only and do not require such interconnections. Even the detailed drawings.

Description of drawings

FIG. 1 is a circuit diagram of a memory array according to the prior art.

2 is a cross-sectional view of a magnetic memory cell made using perpendicular magnetic material according to the prior art.

3 is a circuit diagram of a cross-point resistive non-volatile memory array with back-to-back Schottky diodes at each memory cell, according to the prior art.

4A and 4B are cross-sectional views of a magnetic memory cell fabricated with a perpendicular magnetic material including back-to-back Schottky diodes built into the structure.

Figure 5 is a cross-sectional view of a stacked magnetic memory cell made with perpendicular magnetic material including back-to-back Schottky diodes built into the structure whereby two stacked memory cells share a common word line.

6 is a circuit diagram of a cross-point array of magnetic random access memory (MRAM) with back-to-back Schottky diodes at each memory cell.

7 is a cross-sectional view of a three-dimensional memory array made according to the first embodiment of the present invention.

8 is a cross-sectional view of a three-dimensional memory array made according to a second embodiment of the present invention.

9 is a cross-sectional view of a three-dimensional memory array made according to a third embodiment of the present invention.

Figure 10 is a top view illustration showing wire (or bitline or wordline) interconnections at various intermediate points to allow easy connection to a large transistor array formed across a larger area.

Figures 11A and 11B are graphs showing the range of maximum technology nodes for TFTs as a function of M and Fm, assuming a TFT cell area of ^12Ft2 for only one configuration.

detailed description

The best mode for carrying out the invention is presented in terms of the disclosed first, second and third embodiments.

Embodiments of the present disclosure will be explained below with reference to the drawings. It should be noted that in the following explanation, the same reference numerals designate constituent elements having substantially the same function and arrangement, and description will be repeated only when necessary.

It should also be pointed out that the various embodiments presented below only disclose devices or methods for implementing the technical concept of the present invention. Therefore, the technical idea of the present invention does not limit the material, structure, arrangement, etc. of the constituent parts to those described below. The technical idea of the present invention can be variously changed within the scope of the appended claims.

first embodiment

7 is a cross-sectional view of a three-dimensional memory array made according to the first embodiment of the present invention. The memory array (63) is a cross-point MRAM array made according to Figure 6 whereby a BBSD is incorporated into each memory element. A silicon wafer substrate (60) is provided with CMOS circuits (61) fabricated on the substrate. Such circuits are fabricated at a technology node (Fc), which may be the same size or smaller or larger than the technology node (Fm) used for the MTJ layer, depending on the nature of the CMOS circuit. For example, a microprocessor or a high-end FPGA can be fabricated at a smaller technology node Fc compared to an embedded memory array (Fm), which resides above the circuit. This embedded memory costs less than a separate chip and offers higher speeds because there is no delay to leave the chip. Lower power consumption is also achieved due to the reduction in circuitry. On the other hand, a standalone memory device may have a larger technology node Fc compared to the memory array technology node (Fm). In a dedicated memory device, high density is critical for low cost; therefore, the technology node (Fm) of the memory array will be as small as possible, and the CMOS circuitry will be relatively less complex compared to a microprocessor , therefore, to reduce cost, it can be fabricated at a technology node (Fc) larger than the memory array technology node (Fm). This circuit includes bandgap and decoder logic for the memory array (63), and select transistors for the first memory array (MTJ-L1). Additional circuitry for the memory arrays (MTJ-L1-MTJ-Ln) is provided in different layers (64) of thin film transistors (TFT-L1-TFT-Ln) arranged between the memory arrays. TFT circuits are fabricated at technology nodes (Ft) significantly larger than Fm, such as 40% to 1000% larger than Fm. An interconnection layer (62) is fabricated at technology node Fm to provide interconnection of wordlines and bitlines to corresponding word driver and bit driver circuits. As shown in FIG. 10, relatively large thin film transistors are placed across a large area so that the interconnections to the bitlines and wordlines are not at the ends of these lines, but at various intermediate points along the lines, thereby Interconnect complexity is minimized. Additional interconnections (65) are made from one or more TFT layers to associated bandgap and decoder logic (not shown), which may or may not reside on the CMOS circuit layer. Preferably, the bandgap and decoder logic transistors are located on the same layer or in close proximity to corresponding bit select or word select transistors to provide shorter interconnects, which provide higher speed operation due to lower complexity of construction and Lower cost, in this case such transistors would be on the TFT layer. The TFT layer preferably includes a word driver circuit for the MTJ layer above or below it or a bit driver circuit for the MTJ layer above or below it. For example, TFT-L1 may include a bit driver transistor for MTJ-L1 and a word driver transistor for MTJ-L2; TFT-L2 may include a bit driver transistor for MTJ-L2 and a word driver for MTJ-L3 transistors; and so on. The word driver transistors for MTJ-L1 will reside on the CMOS circuit layer. In this case, each TFT layer, except the top layer TFT-Ln, will include at least (M×3)+(N×2) transistors, if the decoder and bandgap logic reside on the TFT layer , plus an additional transistor.

second embodiment

8 is a cross-sectional view of a three-dimensional memory array made according to a second embodiment of the present invention. The memory array (63) is a cross-point MRAM array made according to Figure 6 whereby a BBSD is incorporated into each memory element. A low cost glass substrate (70) is provided with a first thin film transistor layer (TFT-L1) circuit fabricated on the substrate. Such circuits are fabricated at a technology node (Ft) which may be the same size as the technology node (Fm) used for the MTJ layer, but preferably larger than Fm for cost savings. Such circuitry may include bandgap and decoder logic for the memory array (63), and select transistors for the first memory array (MTJ-L1). Additional circuitry for the memory arrays (MTJ-L1-MTJ-Ln) is provided in different additional layers (64) of thin film transistors (TFT-L1-TFT-Ln+1) arranged between the memory arrays. TFT circuits are fabricated at technology nodes (Ft) significantly larger than Fm, such as 40% to 1,000% larger than Fm. An interconnection layer (62) is fabricated at technology node Fm to provide interconnection of wordlines and bitlines to corresponding word driver and bit driver circuits. As shown in FIG. 10, relatively large thin film transistors are placed across a large area so that the interconnections to the bitlines and wordlines are not at the ends of these lines, but at various intermediate points along the lines, thereby Interconnect complexity is minimized. Additional interconnections (65) are made from one or more TFT layers to associated bandgap and decoder logic (not shown), which may or may not reside at the TFT-L1 circuit layer superior. Preferably, the bandgap and decoder logic transistors are located on the same layer or in close proximity to corresponding bit or word select transistors to provide shorter interconnects, which provide higher speed operation and lower cost, in this case such a transistor would be on the TFT layer. The TFT layer preferably includes a word driver circuit for the MTJ layer above or below it or a bit driver circuit for the MTJ layer above or below it. For example, TFT-L1 may include a word driver transistor for MTJ-L1; TFT-L2 may include a bit driver circuit for MTJ-L1 and a word driver transistor for MTJ-L2; TFT-L3 may include a -bit driver transistors for L2 and word driver transistors for MTJ-L3; and so on. In this case, each intermediate TFT layer (except the top and bottom layers) will consist of at least (M×3)+(N×2) transistors, if the decoder and bandgap logic reside on the TFT layer , plus an additional transistor.

third embodiment

9 is a cross-sectional view of a three-dimensional memory array made according to a third embodiment of the present invention. The memory array (63) is a cross-point MRAM array made according to Figure 6 whereby a BBSD is incorporated into each memory element. A low cost glass substrate (70) is provided with a first thin film transistor layer (TFT-L1) circuit fabricated on the substrate. Such circuits are fabricated at a technology node (Ft) which may be the same size as the technology node (Fm) used for the MTJ layer, but preferably larger than Fm for cost savings. Such circuitry may include bandgap and decoder logic for the memory array (63), and select transistors for the first memory array (MTJ-L1). Additional circuits for memory arrays (MTJ-L1-MTJ-Ln) are provided in different layers of thin film transistors (TFT-L2-TFT-L(n/2+1)) arranged between every two memory arrays ( 64) Inside. TFT circuits are fabricated at technology nodes (Ft) significantly larger than Fm, such as 40% to 1,000% larger than Fm. An interconnect layer (62) is fabricated at technology node Fm to provide interconnection of the bit lines to corresponding bit driver circuits. Alternating pairs of memory arrays share a common word line (66), which is interconnected to a TFT layer (eg, TFT-1) by an interconnect (65). Figure 5 shows a cross-sectional view of corresponding memory cells on different memory arrays that share a common word line at the interface (66) of the two memory arrays.

As shown in FIG. 10, relatively large thin film transistors are arranged across a large area so that the interconnections to the bitlines and wordlines are not at the ends of these lines, but at various intermediate points along the lines, thereby Interconnect complexity is minimized. Additional interconnections (65) are made from one or more TFT layers to associated bandgap and decoder logic (not shown), which may or may not reside on the TFT-L1 circuit layer. Preferably, the bandgap and decoder logic transistors are located on the same layer or in close proximity to corresponding bit select or word select transistors to provide shorter interconnects, which provide higher speed operation due to lower complexity of construction and Lower cost, in which case such circuitry would be located on each TFT layer. In this embodiment, the intermediate TFT layer includes bit drivers for the MTJ layer residing directly above and below the TFT layer. Therefore, the number of transistors on such an intermediate TFT layer will be at least 2*(N*2)=4N. Alternatively, the TFT layer may be fabricated in two layers, a first layer providing bit driver transistors for the MTJ layer below the TFT layer, and a second layer providing bit driver transistors for the MTJ layer above the TFT layer.

It should be noted that the sequence of layers (MTJ and TFT) indicated in the above embodiments may be modified without departing from the scope of the present invention. A key aspect of the present invention is that high-density non-volatile cross-point memory devices can be fabricated in back-end process (BEQL) facilities without the need for costly front-end processing of silicon semiconductor production lines.

Within an embodiment of the invention, there is great freedom in the choice of materials and their thicknesses.

The pinned layer 12 may have a thickness of about 1-100 nanometers, more specifically about 3-50 nanometers, and an easy magnetization axis along it of about 1000 Oersteds or higher, and more specifically about 2000-5000 Oersteds. obtained coercivity. Layer 12 may be made of a magnetic material with perpendicular anisotropy, such as Co, Fe or Ni-based alloys (Fe or Ni-based alloys such as FePt, FePd, CoFeB, FeB, CoFeCrB, CoFeVB, etc.) and/or multilayers based on them or/and laminates (such as CoFe/CoFeTb, CoFeB/CoGd, Fe/TbFe, CoFe/Ta, CoFeB/W, CoFeB/Cr, Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/ Pt, Fe/Pd, Ni/Cu, etc.).

Free layer 16 may have a thickness of about 1-5 nanometers, more specifically about 1.5-2.5 nanometers, and a coercivity of less than 1000 Oersteds, and more specifically about 200-500 Oersteds. The free layer 16 may be made of a soft magnetic material with perpendicular anisotropy, such as Co, Fe, or Ni-based alloys (such as CoFeB, FeB, CoFeCrB, CoFeVB, FeCrB, FeVB, etc.) and/or multilayers and/or laminates (such as CoFeB/(CoFe/Pt), CoFeB/(Co/Pd), CoFe/W, CoFeB/Ta, CoFeB/Cr, Co/Pt, Co/Pd, Co/Au, CoFe/Pt, Fe/Pt, Fe/Pd, Ni/Cu, etc.).

Tunnel barrier layer 14 may have a thickness of about 0.5-2.5 nanometers, more specifically about 0.8-1.3 nanometers. The tunnel barrier layer can be made of MgO, Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , Mg—MgO, ZrOx and similar materials and/or multilayers based on them.

TFTs are widely used in the flat panel display industry; therefore, it is known in the art how to make such transistors. A range of materials for such transistors will be described without intending to limit the invention to such materials.

The TFT insulator layer can be made of SiO ₂ , Al ₂ O ₃ , SiN and other similar materials and/or laminates based on them, or polymer films (such as backed photoresist), polyimide Amines and other similar materials. The thickness of the insulator layer 31 may range from 100 nanometers to 5 micrometers.

The TFT semiconductor layer may be made of polysilicon, cadmium selenide, and others, or more preferably, of numerous amorphous oxide semiconductor materials including, but not limited to, SnO ₂ , In ₂ O ₃ , CdO, Cu ₂ O, InGaZnO, ZnSnO, ZnO, InZnO, AgSbO ₃ , 2CdO·GeO ₂ , 2CdO·PbO, CdS·In2Sx, InGaO ₃ (ZnO) _m (m<=4) and others. The incorporation of thin film oxide semiconductor transistors into electronic devices is disclosed in the following three references, which are incorporated herein by reference in their entirety. (1) PresentstatusofamorphousIn-Ga-Zn-Othin-filmtransistors, ToshioKamiya, KenjiNomuraandHideoHosono, 2010Sci.Technol.Adv.Mater. Advanced Materials Science and Technology 11044305); (2) Short channel device performance of amorphous InGaZnOthinfilm Transistor, SanghunJeon, AnassBenayad, Seung-EonAhn, SunghoPark, IhunSong, ChangjungKim, and U-InChung, APPLIEDPHYSICSLETTERS 99, 082104 (2011) , AnassBenayad, Seung-EonAhn, SunghoPark, IhunSong, ChangjungKim, and U-inChung, Applied Physics Letters 99, 082104 (2011)); and (3) Nanometer-scaleOxideThinFilmTransistorwithpotentialforHigh-DensityImageSensorApplications, SanghunJeon, SunghoPark, IhunSong, Jiur JaechulPark, HojungKim, SunilKim, SangwookKim, HuaxiangYin, U-InChung, EunhaLee, and ChangjungKim, Applied Materials & Interfaces, Vol.3, No.1, 1-6, 2011 (Nanoscale Oxide Thin Film Transistor with Potential for High Density Image Sensor Application , SanghunJeon, SunghoPark, IhunSong, Ji-HyunHur, JaechulPark, HojungKim, SunilKim, SangwookKim, HuaxiangYin, U-InChung, EunhaLee, and ChangjungKim, Applied Materials and Interfaces, Vol. 1, No. 3, pp. 1-6, 2011). The thickness of semiconductor layer 32 may range from 10 nanometers to 5000 nanometers, and more specifically from 50 nanometers to 200 nanometers.

The TFT gate insulating layer can be made of SiO ₂ , SiON, SiNx, aluminum oxide, or other suitable dielectric materials. The thickness of the gate insulator layer may range from 10 nanometers to 1000 nanometers, and more specifically, from 50 nanometers to 200 nanometers.

The bit BL and word WL wires may be made of Cu, Al, Au, Ag, AlCu, Ta/Au/Ta, Cr/Cu/Cr, polysilicon and/or similar materials and/or laminates based on them.

The amorphous semiconductor layer 18 may be made of silicon (Si), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or many other semiconductors when coupled to a wire and one of the metal layers of the MTJ comprises a back-to-back Schottky diode. material.

It should be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art in view of the above description. The scope of the invention should therefore be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims (22)

1. a storage arrangement, it comprises:

Substrate;

Be arranged in the memory array above substrate surface, memory array is with matrix arrangements, and comprise many parallel the first wires, at the second wire that multiple intersecting area place is parallel with many of the first wire overlap, multiple memory cell, each memory cell arrangement is at the intersecting area place of described wire, and each memory cell is electrically coupled to wherein first wire and be electrically coupled to wherein second wire in the second end at first terminal place, and comprises controllable resistor;

Wherein back-to-back Schottky diode at each memory cell with wherein between a described wire; And

Wherein every bar wire is electrically coupled at least two thin-film transistors.

2. device according to claim 1, is characterized in that thin-film transistor utilizes than the technology node manufacture for the manufacture of the technology node large 40% or larger of memory cell.

3. device according to claim 1, is characterized in that thin-film transistor is positioned at above or below memory cell array.

4. device according to claim 1, it is characterized in that memory cell is MTJ, this MTJ comprises at least one pinned ferromagnetic layer with fixed magnetisation direction and the free ferromagnetic layer with reversible magnetizing direction, and pinning layer and free layer are by thin tunnel barrier layer and separated from one another.

5. device according to claim 1, is characterized in that memory array is resistive ram array.

6. device according to claim 1, is characterized in that substrate is glass substrate.

7. device according to claim 1, is characterized in that it is in-line memory, and in-line memory resides on the chip above the circuit or other integrated circuit of microprocessor, FPGA, ASIC.

8. device according to claim 2, is characterized in that thin-film transistor utilizes than the technology node manufacture for the manufacture of the technology node large 280% or larger of memory cell.

9. device according to claim 2, is characterized in that thin-film transistor utilizes than the technology node manufacture for the manufacture of the technology node large 1000% or larger of memory cell.

10. device according to claim 1, is characterized in that the thin-film transistor relevant to decoder logic is closely selected transistor near driver and manufacture.

11. 1 kinds of storage arrangements, it comprises:

Substrate;

Be arranged in the multiple memory arrays above substrate surface, each memory array is with matrix arrangements and comprise many parallel the first wires, at the second wire that multiple intersecting area place is parallel with many of the first wire overlap, multiple memory cell, each memory cell arrangement is at the intersecting area place of described wire, each memory cell is electrically coupled to wherein first wire and be electrically coupled to wherein second wire in the second end at first terminal place, and comprises controllable resistor;

Wherein back-to-back Schottky diode at each memory cell with wherein between a described wire; And

Wherein every bar wire is electrically coupled at least two thin-film transistors.

12. device according to claim 11, it is characterized in that thin-film transistor utilizes and make than the technology node for the manufacture of the technology node large 40% or larger of memory cell.

13. devices according to claim 11, it is characterized in that thin-film transistor above or below memory array or between layer place location.

14. devices according to claim 11, it is characterized in that memory cell is MTJ, MTJ comprises at least one fixing pinning ferromagnetic layer with fixed magnetisation direction and the free ferromagnetic layer with reversible magnetizing direction, and pinning layer and free layer are by thin tunnel barrier layer and separated from one another.

15. devices according to claim 11, is characterized in that memory array is resistive ram array.

16. devices according to claim 11, is characterized in that substrate is glass substrate.

17. device according to claim 11, it is characterized in that it is in-line memory, in-line memory resides on the chip above the circuit or other integrated circuit of microprocessor, FPGA, ASIC.

18. device according to claim 12, it is characterized in that thin-film transistor utilizes and make than the technology node for the manufacture of the technology node large 280% or larger of memory cell.

19. device according to claim 12, it is characterized in that thin-film transistor utilizes and make than the technology node for the manufacture of the technology node large 1000% or larger of memory cell.

20. devices according to claim 11, is characterized in that the thin-film transistor relevant to decoder logic is closely selected transistor near driver and manufacture.

21. 1 kinds of storage arrangements, it comprises:

Substrate;

Be arranged in the memory array above substrate surface, memory array is with matrix arrangements and comprise many parallel the first wires, at the second wire that multiple intersecting area place is parallel with many of the first wire overlap, multiple memory cell, each memory cell arrangement is at the intersecting area place of described wire, and each memory cell is electrically coupled to wherein first wire and be electrically coupled to wherein second wire in the second end at first terminal place;

Each wire wherein in the first wire or the second wire or the first wire and the second wire is electrically coupled at least two transistors;

Wherein said transistor is located substantially on above or below memory array.

22. 1 kinds of storage arrangements, it comprises:

Substrate;

Be arranged in the multiple memory arrays above substrate surface, each memory array is with matrix arrangements and comprise many parallel the first wires, at the second wire that multiple intersecting area place is parallel with many of the first wire overlap, multiple memory cell, each memory cell arrangement is at the intersecting area place of described wire, and each memory cell is electrically coupled to wherein first wire and be electrically coupled to wherein second wire in the second end at first terminal place;

Each wire wherein in the first wire or the second wire or the first wire and the second wire is electrically coupled at least two transistors;

Wherein said transistor to be located substantially on above or below memory array or between.