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CN105514118A - Thin film transistor array substrate, preparation method thereof, display panel and display device - Google Patents

Thin film transistor array substrate, preparation method thereof, display panel and display device Download PDF

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Publication number
CN105514118A
CN105514118A CN201510990042.9A CN201510990042A CN105514118A CN 105514118 A CN105514118 A CN 105514118A CN 201510990042 A CN201510990042 A CN 201510990042A CN 105514118 A CN105514118 A CN 105514118A
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film transistor
thin film
thin
switching
insulating layer
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刘青刚
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Kunshan Govisionox Optoelectronics Co Ltd
Kunshan Guoxian Photoelectric Co Ltd
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Kunshan Guoxian Photoelectric Co Ltd
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01Manufacture or treatment
    • H10D86/021Manufacture or treatment of multiple TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/431Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/1201Manufacture or treatment

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本发明提供一种薄膜晶体管阵列基板及其制备方法、显示面板及显示装置,所述制备方法包括:在基板上同时形成开关薄膜晶体管和驱动薄膜晶体管的有源区;在有源区上形成开关薄膜晶体管的栅极绝缘层及栅极,以及驱动薄膜晶体管的第一栅极绝缘层;在第一栅极绝缘层上形成第二栅极绝缘层;形成驱动薄膜晶体管的栅极;驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。

The invention provides a thin film transistor array substrate and a preparation method thereof, a display panel and a display device. The preparation method includes: simultaneously forming an active region of a switching thin film transistor and a driving thin film transistor on the substrate; forming a switch on the active region The gate insulating layer and gate of the thin film transistor, and the first gate insulating layer of the driving thin film transistor; forming the second gate insulating layer on the first gate insulating layer; forming the gate of driving the thin film transistor; driving the thin film transistor The thickness of the gate insulating layer is greater than the thickness of the gate insulating layer of the switching thin film transistor, so that the subthreshold swing of the driving thin film transistor is greater than the subthreshold swing of the switching thin film transistor. Since the subthreshold swing of the driving thin film transistor is relatively large, it can The display of the gray scale is better controlled, and at the same time, because the sub-threshold swing of the switching thin film transistor is small, the switching performance of the switching thin film transistor is guaranteed, and finally the quality of the display device is improved.

Description

薄膜晶体管阵列基板及其制备方法、显示面板及显示装置Thin film transistor array substrate and its preparation method, display panel and display device

技术领域technical field

本发明涉及平面显示技术领域,具体涉及一种薄膜晶体管阵列基板及其制备方法、显示面板及显示装置。The invention relates to the technical field of plane display, in particular to a thin film transistor array substrate and a preparation method thereof, a display panel and a display device.

背景技术Background technique

有机发光显示器(OrganicLight-EmittingDiode,OLED)相比现在的主流显示技术薄膜晶体管液晶显示器(ThinFilmTransistorLiquidCrystalDisplay,TFT-LCD),具有广视角、高亮度、高对比度、低能耗、体积更轻薄等优点,是目前平板显示技术关注的焦点。Compared with the current mainstream display technology Thin Film Transistor Liquid Crystal Display (TFT-LCD), organic light-emitting display (Organic Light-Emitting Diode, OLED) has the advantages of wide viewing angle, high brightness, high contrast, low energy consumption, and thinner volume. The focus of flat panel display technology.

有机发光显示器的驱动方法分为被动矩阵式(PM,PassiveMatrix)和主动矩阵式(AM,ActiveMatrix)两种。而相比被动矩阵式驱动,主动矩阵式驱动具有显示信息量大、功耗低、器件寿命长、画面对比度高等优点。There are two driving methods of organic light emitting displays: passive matrix (PM, PassiveMatrix) and active matrix (AM, ActiveMatrix). Compared with the passive matrix drive, the active matrix drive has the advantages of large display information, low power consumption, long device life, and high screen contrast.

目前,主动矩阵式有机发光显示器(AMOLED)主要使用低温多晶硅薄膜晶体管(LTPS-TFT)驱动OLED发光。如图1所示,一般而言主动矩阵式有机发光显示器包括:开关薄膜晶体管2、驱动薄膜晶体管1和有机发光器件(OLED)3。开关薄膜晶体管2的栅极连接扫描线4,其漏极(或源极)连接数据线5,其源极(或漏极)连接驱动薄膜晶体管1的栅极。驱动薄膜晶体管1的源极(或漏极)连接电源线6,其漏极(或源极)连接OLED的阳极,OLED的阴极接地。在驱动薄膜晶体管1的源极(或漏极)与栅极之间连接有存储电容7。Currently, active matrix organic light emitting displays (AMOLEDs) mainly use low temperature polysilicon thin film transistors (LTPS-TFTs) to drive OLEDs to emit light. As shown in FIG. 1 , generally speaking, an active matrix organic light emitting display includes: a switching thin film transistor 2 , a driving thin film transistor 1 and an organic light emitting device (OLED) 3 . The gate of the switching thin film transistor 2 is connected to the scan line 4 , the drain (or source) thereof is connected to the data line 5 , and the source (or drain) is connected to the gate of the driving thin film transistor 1 . The source (or drain) of the driving thin film transistor 1 is connected to the power line 6, the drain (or source) is connected to the anode of the OLED, and the cathode of the OLED is grounded. A storage capacitor 7 is connected between the source (or drain) and the gate of the driving thin film transistor 1 .

通常要求开关薄膜晶体管2具有低的亚阈值摆幅(sub-thresholdswing,S.S),使得电流随电压变化更大,而要求驱动薄膜晶体管1具有较高的亚阈值摆幅,使得电流随电压变化更小,这样可以保证开关薄膜晶体管2的开关性能更好,有利于灰阶的控制。而薄膜晶体管的亚阈值摆幅取决于栅极电容大小,栅极电容大小取决于栅极绝缘层的厚度,因此驱动薄膜晶体管2的栅极绝缘层厚度应大于开关薄膜晶体管1的栅极绝缘层的厚度。Generally, the switching thin film transistor 2 is required to have a low sub-threshold swing (sub-threshold swing, S.S), so that the current varies more with the voltage, and the driving thin film transistor 1 is required to have a higher sub-threshold swing, so that the current varies more with the voltage. Small, this can ensure better switching performance of the switching thin film transistor 2, which is beneficial to gray scale control. The sub-threshold swing of the TFT depends on the gate capacitance, and the gate capacitance depends on the thickness of the gate insulating layer. Therefore, the thickness of the gate insulating layer of the driving TFT 2 should be greater than that of the switching TFT 1. thickness of.

但是,在现有工艺中,开关薄膜晶体管2和驱动薄膜晶体管1的制程相同,其栅极绝缘层的厚度也相同,导致两种薄膜晶体管的亚阈值摆幅的大小相等,因此不利于有效的开启和闭合开关薄膜晶体管及灰阶的控制。However, in the existing technology, the manufacturing process of the switching thin film transistor 2 and the driving thin film transistor 1 are the same, and the thickness of the gate insulating layer is also the same, which results in equal sub-threshold swings of the two thin film transistors, which is not conducive to effective Turn on and off the switching thin film transistor and the control of the gray scale.

发明内容Contents of the invention

本发明的目的在于提供一种薄膜晶体管阵列基板及其制备方法、显示面板及显示装置,在保持开关薄膜晶体管亚阈值摆幅较小的前提下有效提高驱动薄膜晶体管的亚阈值摆幅,进而保证开关薄膜晶体管的开关能力,可以更好的控制灰阶的显示,提升显示器件的品质。The purpose of the present invention is to provide a thin-film transistor array substrate and its preparation method, display panel and display device, which can effectively improve the sub-threshold swing of the driving thin-film transistor under the premise of keeping the sub-threshold swing of the switching thin-film transistor small, thereby ensuring The switching capability of the switching thin film transistor can better control the gray scale display and improve the quality of the display device.

为实现上述目的,本发明提供一种薄膜晶体管阵列基板的制备方法,包括:In order to achieve the above object, the present invention provides a method for preparing a thin film transistor array substrate, comprising:

在基板上同时形成开关薄膜晶体管的有源区和驱动薄膜晶体管的有源区;Simultaneously forming the active area of the switching thin film transistor and the active area of the driving thin film transistor on the substrate;

在所述基板上同时形成开关薄膜晶体管的栅极绝缘层和驱动薄膜晶体管的第一栅极绝缘层;Simultaneously forming a gate insulating layer of a switching thin film transistor and a first gate insulating layer of a driving thin film transistor on the substrate;

在所述开关薄膜晶体管的栅极绝缘层上形成开关薄膜晶体管的栅极;forming the gate of the switch thin film transistor on the gate insulating layer of the switch thin film transistor;

在所述驱动薄膜晶体管的第一栅极绝缘层上形成第二栅极绝缘层;forming a second gate insulating layer on the first gate insulating layer of the driving thin film transistor;

在所述第二栅极绝缘层上形成驱动薄膜晶体管的栅极。A gate of a driving thin film transistor is formed on the second gate insulating layer.

可选的,所述栅极绝缘层包括氧化硅层、氮化硅层之一或其组合。Optionally, the gate insulating layer includes one of a silicon oxide layer, a silicon nitride layer or a combination thereof.

可选的,在所述第二栅极绝缘层上形成驱动薄膜晶体管的栅极之后,还包括:依次形成保护层、开关薄膜晶体管与驱动薄膜晶体管的源极/漏极、有机平坦层、有机电致发光电极和像素定义层。Optionally, after forming the gate of the driving thin film transistor on the second gate insulating layer, it further includes: sequentially forming a protective layer, the source/drain of the switching thin film transistor and the driving thin film transistor, an organic planar layer, organic Electromechanical Luminescent Electrodes and Pixel Definition Layers.

本发明还提供一种薄膜晶体管阵列基板的制备方法,包括:The present invention also provides a method for preparing a thin film transistor array substrate, comprising:

在基板上同时形成开关薄膜晶体管的栅极和驱动薄膜晶体管的栅极;Simultaneously forming the gate of the switching thin film transistor and the gate of the driving thin film transistor on the substrate;

在所述基板上同时形成开关薄膜晶体管的栅极绝缘层和驱动薄膜晶体管的第一栅极绝缘层;Simultaneously forming a gate insulating layer of a switching thin film transistor and a first gate insulating layer of a driving thin film transistor on the substrate;

在所述开关薄膜晶体管的栅极绝缘层上形成开关薄膜晶体管的有源区;forming an active region of the switching thin film transistor on the gate insulating layer of the switching thin film transistor;

在所述驱动薄膜晶体管的第一栅极绝缘层上形成第二栅极绝缘层;forming a second gate insulating layer on the first gate insulating layer of the driving thin film transistor;

在所述第二栅极绝缘层上形成驱动薄膜晶体管的有源区。An active region for driving a thin film transistor is formed on the second gate insulating layer.

可选的,所述栅极绝缘层包括氧化硅层、氮化硅层之一或其组合。Optionally, the gate insulating layer includes one of a silicon oxide layer, a silicon nitride layer or a combination thereof.

可选的,在所述第二栅极绝缘层上形成驱动薄膜晶体管的有源区之后,还包括:依次形成保护层、开关薄膜晶体管与驱动薄膜晶体管的源极/漏极、有机平坦层、有机电致发光电极和像素定义层。Optionally, after forming the active region of the driving thin film transistor on the second gate insulating layer, it further includes: sequentially forming a protective layer, the source/drain of the switching thin film transistor and the driving thin film transistor, an organic planar layer, Organic electroluminescent electrodes and pixel definition layers.

相应的,本发明还提供一种薄膜晶体管阵列基板,采用上述薄膜晶体管阵列基板的制备方法制备。Correspondingly, the present invention also provides a thin film transistor array substrate, which is prepared by the above method for preparing the thin film transistor array substrate.

优选的,所述开关薄膜晶体管为顶栅型薄膜晶体管或底栅型薄膜晶体管;所述驱动薄膜晶体管为顶栅型薄膜晶体管或底栅型薄膜晶体管。Preferably, the switch thin film transistor is a top gate thin film transistor or a bottom gate thin film transistor; the driving thin film transistor is a top gate thin film transistor or a bottom gate thin film transistor.

相应的,本发明还提供一种显示面板,包括上述的薄膜晶体管阵列基板。Correspondingly, the present invention also provides a display panel, including the above thin film transistor array substrate.

相应的,本发明还提供一种显示装置,包括上述的显示面板。Correspondingly, the present invention also provides a display device, including the above-mentioned display panel.

与现有技术相比,本发明提供的薄膜晶体管阵列基板及其制备方法、显示面板及显示装置,通过在形成开关薄膜晶体管的栅极图形之后,在驱动薄膜晶体管的第一栅极绝缘层上形成第二栅极绝缘层,使得驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,进而使得驱动薄膜晶体管的栅极电容值小于开关薄膜晶体管的栅极电容值,进而使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。Compared with the prior art, the thin film transistor array substrate and its preparation method, display panel and display device provided by the present invention, after forming the gate pattern of the switching thin film transistor, on the first gate insulating layer of the driving thin film transistor forming a second gate insulating layer, so that the thickness of the gate insulating layer of the driving thin film transistor is greater than the thickness of the gate insulating layer of the switching thin film transistor, so that the gate capacitance of the driving thin film transistor is smaller than the gate capacitance of the switching thin film transistor, Furthermore, the subthreshold swing of the driving thin film transistor is larger than that of the switching thin film transistor. Since the subthreshold swing of the driving thin film transistor is relatively large, the gray scale display can be better controlled. At the same time, due to the subthreshold swing of the switching thin film transistor The swing amplitude is small, which ensures the switching performance of the switching thin film transistor, and finally improves the quality of the display device.

附图说明Description of drawings

图1为现有的主动矩阵式有机发光显示器(AMOLED)的基本原理图;FIG. 1 is a basic schematic diagram of an existing active matrix organic light emitting display (AMOLED);

图2为本发明实施例一所提供的薄膜晶体管阵列基板的制备方法的流程图;FIG. 2 is a flow chart of a method for manufacturing a thin film transistor array substrate provided in Embodiment 1 of the present invention;

图3~7为本发明实施例一所提供的薄膜晶体管阵列基板的制备方法各步骤的结构示意图。3 to 7 are structural schematic diagrams of each step of the manufacturing method of the thin film transistor array substrate provided by Embodiment 1 of the present invention.

具体实施方式detailed description

为使本发明的内容更加清楚易懂,以下结合说明书附图,对本发明的内容做进一步说明。当然本发明并不局限于该具体实施例,本领域的技术人员所熟知的一般替换也涵盖在本发明的保护范围内。In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

其次,本发明利用示意图进行了详细的表述,在详述本发明实例时,为了便于说明,示意图不依照一般比例局部放大,不应对此作为本发明的限定。Secondly, the present invention is described in detail by means of schematic diagrams. When describing the examples of the present invention in detail, for the convenience of illustration, the schematic diagrams are not partially enlarged according to the general scale, which should not be used as a limitation of the present invention.

本发明的核心思想在于,通过在形成开关薄膜晶体管的栅极图形之后,在驱动薄膜晶体管的第一栅极绝缘层上形成第二栅极绝缘层,使得驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,进而使得驱动薄膜晶体管的栅极电容值小于开关薄膜晶体管的栅极电容值,进而使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。The core idea of the present invention is that by forming the second gate insulating layer on the first gate insulating layer of the driving thin film transistor after forming the gate pattern of the switching thin film transistor, the thickness of the gate insulating layer of the driving thin film transistor greater than the thickness of the gate insulating layer of the switching thin film transistor, thereby making the gate capacitance value of the driving thin film transistor smaller than the gate capacitance value of the switching thin film transistor, thereby making the subthreshold swing of the driving thin film transistor larger than that of the switching thin film transistor , due to the large sub-threshold swing of the driving thin film transistor, the display of gray scale can be better controlled, and at the same time, because the sub-threshold swing of the switching thin film transistor is small, the switching performance of the switching thin film transistor is guaranteed, and finally the quality of the display device is improved .

【实施例一】[Example 1]

图2为本发明实施例一所提供的薄膜晶体管阵列基板的制备方法的流程图,如图2所示,本发明提出一种薄膜晶体管阵列基板的制备方法,包括以下步骤:FIG. 2 is a flow chart of a method for preparing a thin film transistor array substrate provided in Embodiment 1 of the present invention. As shown in FIG. 2 , the present invention proposes a method for preparing a thin film transistor array substrate, which includes the following steps:

步骤S01:在基板上同时形成开关薄膜晶体管的有源区和驱动薄膜晶体管的有源区;Step S01: simultaneously forming an active region of a switching thin film transistor and an active region of a driving thin film transistor on a substrate;

步骤S02:在所述基板上同时形成开关薄膜晶体管的栅极绝缘层和驱动薄膜晶体管的第一栅极绝缘层;Step S02: simultaneously forming a gate insulating layer of a switching thin film transistor and a first gate insulating layer of a driving thin film transistor on the substrate;

步骤S03:在所述开关薄膜晶体管的栅极绝缘层上形成开关薄膜晶体管的栅极;Step S03: forming the gate of the switching thin film transistor on the gate insulating layer of the switching thin film transistor;

步骤S04:在所述驱动薄膜晶体管的第一栅极绝缘层上形成第二栅极绝缘层;Step S04: forming a second gate insulating layer on the first gate insulating layer of the driving thin film transistor;

步骤S05:在所述第二栅极绝缘层上形成驱动薄膜晶体管的栅极。Step S05: forming a gate of a driving thin film transistor on the second gate insulating layer.

图3~7为本发明实施例一所提供的薄膜晶体管阵列基板的制备方法各步骤形成的结构示意图。下面结合图2~图7详细说明本发明提出的薄膜晶体管阵列基板的制备方法。3 to 7 are schematic diagrams of structures formed in each step of the manufacturing method of the thin film transistor array substrate provided by Embodiment 1 of the present invention. The preparation method of the thin film transistor array substrate proposed by the present invention will be described in detail below with reference to FIGS. 2 to 7 .

在步骤S01中,在基板10上同时形成开关薄膜晶体管的有源区11和驱动薄膜晶体管的有源区11,如图3所示。所述基板10为透明基板,优选的,所述基板20为玻璃基板。在所述基板10上通过溅射、曝光、显影、刻蚀、剥离等工艺形成薄膜晶体管和驱动薄膜晶体管的有源区11。其中,所述有源区11的材料为多晶硅,或者本领域技术人员已知的其他材料。In step S01 , the active region 11 of the switching thin film transistor and the active region 11 of the driving thin film transistor are simultaneously formed on the substrate 10 , as shown in FIG. 3 . The substrate 10 is a transparent substrate, preferably, the substrate 20 is a glass substrate. The thin film transistor and the active region 11 for driving the thin film transistor are formed on the substrate 10 through processes such as sputtering, exposure, development, etching, and stripping. Wherein, the material of the active region 11 is polysilicon, or other materials known to those skilled in the art.

在步骤S02中,在完成上述步骤的基板上,同时形成开关薄膜晶体管的栅极绝缘层12和驱动薄膜晶体管的第一栅极绝缘层12,如图4所示。本实施例中,采用化学气相沉积法、曝光、显影、刻蚀、剥离等工艺在所述基板10上形成一层栅极绝缘层12,形成于所述开关晶体管的有源区11上的为开关薄膜晶体管的栅极绝缘层,形成于所述驱动薄膜晶体管的有源区11上的为驱动薄膜晶体管的第一栅极绝缘层,。优选的,采用等离子体增强化学气相沉积法(PECVD,PlasmaEnhancedChemicalVaporDeposition)形成栅极绝缘层12,可以理解的是,亦可采用其他方法形成栅极绝缘层12。其中,栅极绝缘层12为单层或多层结构,其包括氧化硅层、氮化硅层之一或其组合。In step S02 , the gate insulating layer 12 of the switching thin film transistor and the first gate insulating layer 12 of the driving thin film transistor are simultaneously formed on the substrate after the above steps, as shown in FIG. 4 . In this embodiment, a gate insulating layer 12 is formed on the substrate 10 by chemical vapor deposition, exposure, development, etching, stripping and other processes, and the gate insulating layer 12 formed on the active region 11 of the switching transistor is The gate insulating layer of the switching thin film transistor is the first gate insulating layer of the driving thin film transistor formed on the active region 11 of the driving thin film transistor. Preferably, the gate insulating layer 12 is formed by plasma enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition). It is understood that the gate insulating layer 12 may also be formed by other methods. Wherein, the gate insulating layer 12 is a single-layer or multi-layer structure, which includes one of a silicon oxide layer, a silicon nitride layer or a combination thereof.

在步骤S03中,在所述开关薄膜晶体管的栅极绝缘层12上形成开关薄膜晶体管的栅极13,如图5所示。具体而言,在完成上述步骤的基板10上,通过溅射、曝光、显影、刻蚀、剥离等工艺形成开关薄膜晶体管的栅极13。其中,所述栅极13的材料可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钨(W)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层。In step S03 , the gate 13 of the switch thin film transistor is formed on the gate insulating layer 12 of the switch thin film transistor, as shown in FIG. 5 . Specifically, on the substrate 10 after the above steps are completed, the gate 13 of the switching thin film transistor is formed by processes such as sputtering, exposure, development, etching, and stripping. Wherein, the material of the gate 13 can be molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminum (Al), aluminum neodymium alloy (AlNd), tungsten (W), titanium (Ti) and copper (Cu) A single-layer or multi-layer composite laminate formed of one or more of them.

在步骤S04中,在所述驱动薄膜晶体管的第一栅极绝缘层12上形成第二栅极绝缘层14,如图6所示。本实施例中,采用化学气相沉积法、曝光、显影、刻蚀、剥离等工艺形成第二栅极绝缘层14,优选的,采用等离子体增强化学气相沉积法(PECVD,PlasmaEnhancedChemicalVaporDeposition)形成第二栅极绝缘层14,可以理解的是,亦可采用其他方法形成第二栅极绝缘层12。其中,第二栅极绝缘层14为单层或多层结构,其包括氧化硅层、氮化硅层之一或其组合。In step S04 , a second gate insulating layer 14 is formed on the first gate insulating layer 12 of the driving thin film transistor, as shown in FIG. 6 . In this embodiment, the second gate insulating layer 14 is formed by chemical vapor deposition, exposure, development, etching, stripping, etc. It can be understood that other methods can also be used to form the second gate insulating layer 14 . Wherein, the second gate insulating layer 14 is a single-layer or multi-layer structure, which includes one of a silicon oxide layer, a silicon nitride layer or a combination thereof.

也就是说,驱动薄膜晶体管的栅极绝缘层为第一栅极绝缘层加第二栅极绝缘层,即驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,根据电容公式C=εAd(其中C为薄膜晶体管的电容,d为薄膜晶体管栅极绝缘层的厚度,A为薄膜晶体管栅极绝缘层的面积,ε为介电常数)可以得出薄膜晶体管的电容与其栅极绝缘层的厚度成反比,从而使得驱动薄膜晶体管的栅极电容值小于开关薄膜晶体管的栅极电容值,进而使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。That is to say, the gate insulating layer of the driving thin film transistor is the first gate insulating layer plus the second gate insulating layer, that is, the thickness of the gate insulating layer of the driving thin film transistor is greater than the thickness of the gate insulating layer of the switching thin film transistor, according to The capacitance formula C=εAd (wherein C is the capacitance of the thin film transistor, d is the thickness of the gate insulating layer of the thin film transistor, A is the area of the gate insulating layer of the thin film transistor, and ε is the dielectric constant) can draw the capacitance of the thin film transistor and its The thickness of the gate insulating layer is inversely proportional, so that the gate capacitance of the driving thin film transistor is smaller than the gate capacitance of the switching thin film transistor, so that the subthreshold swing of the driving thin film transistor is greater than the subthreshold swing of the switching thin film transistor, because The sub-threshold swing of the driving thin film transistor is relatively large, which can better control the display of the gray scale. At the same time, the switching performance of the switching thin film transistor is guaranteed due to the small sub-threshold swing of the switching thin film transistor, and finally the quality of the display device is improved.

在步骤S05中,在所述第二栅极绝缘层14上形成驱动薄膜晶体管的栅极15,如图7所示。具体而言,在完成上述步骤的基板10上,通过溅射、曝光、显影、刻蚀、剥离等工艺形成驱动薄膜晶体管的栅极15。其中,所述栅极15的材料可以为钼(Mo)、钼铌合金(MoNb)、铝(Al)、铝钕合金(AlNd)、钨(W)、钛(Ti)和铜(Cu)中的一种或它们中多种材料形成的单层或多层复合叠层。In step S05 , the gate 15 for driving the thin film transistor is formed on the second gate insulating layer 14 , as shown in FIG. 7 . Specifically, on the substrate 10 after the above steps are completed, the gate 15 for driving the thin film transistor is formed by processes such as sputtering, exposure, development, etching, and stripping. Wherein, the material of the gate 15 can be molybdenum (Mo), molybdenum niobium alloy (MoNb), aluminum (Al), aluminum neodymium alloy (AlNd), tungsten (W), titanium (Ti) and copper (Cu) A single-layer or multi-layer composite laminate formed of one or more of them.

在所述第二栅极绝缘层14上形成驱动薄膜晶体管的栅极15之后,还包括:依次形成保护层、开关薄膜晶体管与驱动薄膜晶体管的源极/漏极、有机平坦层、有机电致发光电极、像素定义层等。以上步骤为本领域技术人员所熟知,在此不再赘述。After forming the gate 15 of the driving thin film transistor on the second gate insulating layer 14, it also includes: sequentially forming a protective layer, the source/drain of the switching thin film transistor and the driving thin film transistor, an organic planar layer, an organic electro- Light-emitting electrodes, pixel definition layers, etc. The above steps are well known to those skilled in the art and will not be repeated here.

上述方法描述的是当开关薄膜晶体管和驱动薄膜晶体管均为顶栅型薄膜晶体管时,该薄膜晶体管阵列基板的具体制备方法。若当开关薄膜晶体管和驱动薄膜晶体管均为底栅型薄膜晶体管时,该薄膜晶体管阵列基板的制备方法与上述方法相似,区别在于:The above method describes the specific preparation method of the thin film transistor array substrate when both the switching thin film transistor and the driving thin film transistor are top-gate thin film transistors. If both the switching thin film transistor and the driving thin film transistor are bottom-gate thin film transistors, the preparation method of the thin film transistor array substrate is similar to the above method, the difference is that:

步骤S01:在基板10上同时形成开关薄膜晶体管的栅极11和驱动薄膜晶体管的栅极11;步骤S02:在所述基板10上同时形成开关薄膜晶体管的栅极绝缘层12和驱动薄膜晶体管的第一栅极绝缘层12;步骤S03:在所述开关薄膜晶体管的栅极绝缘层12上形成开关薄膜晶体管的有源区13;步骤S04:在所述驱动薄膜晶体管的第一栅极绝缘层12上形成第二栅极绝缘层14;步骤S05:在所述第二栅极绝缘层14上形成驱动薄膜晶体管的有源区15。Step S01: Form the gate 11 of the switching thin film transistor and the gate 11 of the driving thin film transistor on the substrate 10 at the same time; Step S02: Form the gate insulating layer 12 of the switching thin film transistor and the gate insulating layer 12 of the driving thin film transistor on the substrate 10 at the same time. The first gate insulating layer 12; step S03: forming the active region 13 of the switching thin film transistor on the gate insulating layer 12 of the switching thin film transistor; step S04: forming the first gate insulating layer of the driving thin film transistor Forming a second gate insulating layer 14 on 12 ; Step S05 : forming an active region 15 for driving a thin film transistor on the second gate insulating layer 14 .

其中,所述栅极绝缘层包括氧化硅层、氮化硅层之一或其组合;并且,在所述第二栅极绝缘层14上形成驱动薄膜晶体管的栅极15之后,还包括:依次形成保护层、开关薄膜晶体管与驱动薄膜晶体管的源极/漏极、有机平坦层、有机电致发光电极、像素定义层等。以上步骤为本领域技术人员所熟知,在此不再赘述。Wherein, the gate insulating layer includes one of a silicon oxide layer, a silicon nitride layer or a combination thereof; and, after forming the gate 15 of the driving thin film transistor on the second gate insulating layer 14, it further includes: Form the protection layer, the source/drain of the switching thin film transistor and the driving thin film transistor, the organic planar layer, the organic electroluminescence electrode, the pixel definition layer and so on. The above steps are well known to those skilled in the art and will not be repeated here.

当然,开关薄膜晶体管和驱动薄膜晶体管的类型也可以是不同的,也就是开关薄膜晶体管为顶栅型薄膜晶体管,驱动薄膜晶体管为底栅型薄膜晶体管,或者开关薄膜晶体管为底栅型薄膜晶体管,驱动薄膜晶体管为顶栅型薄膜晶体管,此时制备薄膜晶体管阵列基板是可以将开关薄膜晶体管和驱动薄膜晶体管分别制备,只要保证在形成开关薄膜晶体管的栅极或有源区图形之后,在驱动薄膜晶体管的第一栅极绝缘层上形成第二栅极绝缘层,使得驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管的栅极绝缘层的厚度即可,每个薄膜晶体管的制备方法与上述方法类似,在此不重复赘述。Of course, the types of the switching thin film transistor and the driving thin film transistor may also be different, that is, the switching thin film transistor is a top gate thin film transistor, the driving thin film transistor is a bottom gate thin film transistor, or the switching thin film transistor is a bottom gate thin film transistor, The driving thin film transistor is a top-gate thin film transistor. At this time, the thin film transistor array substrate can be prepared separately from the switching thin film transistor and the driving thin film transistor, as long as it is ensured that after the gate or active region pattern of the switching thin film transistor is formed, the driving thin film transistor The second gate insulating layer is formed on the first gate insulating layer of the transistor, so that the thickness of the gate insulating layer of the driving thin film transistor is greater than the thickness of the gate insulating layer of the switching thin film transistor. The preparation method of each thin film transistor is the same as The above methods are similar and will not be repeated here.

【实施例二】[Example 2]

本实施例提供一种薄膜晶体管阵列基板,采用实施例一所述的薄膜晶体管阵列基板的制备方法制备。This embodiment provides a thin film transistor array substrate, which is prepared by the manufacturing method of the thin film transistor array substrate described in the first embodiment.

请参照图7所示,所述薄膜晶体管阵列基板包括开关薄膜晶体管和驱动薄膜晶体管,所述开关薄膜晶体管的栅极绝缘层为栅极绝缘层12,所述驱动薄膜晶体管的栅极绝缘层为第一栅极绝缘层12与第二栅极绝缘层14,驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,使得驱动薄膜晶体管的栅极电容值小于开关薄膜晶体管的栅极电容值,进而使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。Please refer to FIG. 7, the thin film transistor array substrate includes a switching thin film transistor and a driving thin film transistor, the gate insulating layer of the switching thin film transistor is a gate insulating layer 12, and the gate insulating layer of the driving thin film transistor is The first gate insulating layer 12 and the second gate insulating layer 14, the thickness of the gate insulating layer of the driving thin film transistor is greater than the thickness of the switching thin film transistor gate insulating layer, so that the gate capacitance of the driving thin film transistor is smaller than the switching thin film transistor The gate capacitance value, so that the subthreshold swing of the driving thin film transistor is larger than the subthreshold swing of the switching thin film transistor. Because the subthreshold swing of the driving thin film transistor is larger, the gray scale display can be better controlled. At the same time, because The sub-threshold swing of the switching thin film transistor is small, which ensures the switching performance of the switching thin film transistor, and finally improves the quality of the display device.

优选的,所述开关薄膜晶体管为顶栅型薄膜晶体管或底栅型薄膜晶体管;所述驱动薄膜晶体管为顶栅型薄膜晶体管或底栅型薄膜晶体管。Preferably, the switch thin film transistor is a top gate thin film transistor or a bottom gate thin film transistor; the driving thin film transistor is a top gate thin film transistor or a bottom gate thin film transistor.

【实施例三】[Embodiment 3]

本实施例提供一种显示面板,其包括实施例二所述的薄膜晶体管阵列基板。This embodiment provides a display panel, which includes the TFT array substrate described in the second embodiment.

本实施例的显示面板中具有实施例二中的薄膜晶体管阵列基板,故其驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,使得驱动薄膜晶体管的栅极电容值小于开关薄膜晶体管的栅极电容值,进而使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。The display panel of this embodiment has the thin film transistor array substrate in the second embodiment, so the thickness of the gate insulating layer of the driving thin film transistor is greater than the thickness of the switching thin film transistor gate insulating layer, so that the gate capacitance of the driving thin film transistor smaller than the gate capacitance value of the switching thin film transistor, thereby making the subthreshold swing of the driving thin film transistor larger than the subthreshold swing of the switching thin film transistor, since the subthreshold swing of the driving thin film transistor is larger, the gray scale can be better controlled At the same time, due to the small sub-threshold swing of the switching thin film transistor, the switching performance of the switching thin film transistor is guaranteed, and the quality of the display device is finally improved.

【实施例四】[Embodiment 4]

本实施例提供一种显示装置,其包括实施例三所述的显示面板。This embodiment provides a display device, which includes the display panel described in the third embodiment.

本实施例中的显示装置具有实施例三中的显示面板,故其驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,使得驱动薄膜晶体管的栅极电容值小于开关薄膜晶体管的栅极电容值,进而使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。The display device in this embodiment has the display panel in Embodiment 3, so the thickness of the gate insulating layer of the driving thin film transistor is greater than the thickness of the gate insulating layer of the switching thin film transistor, so that the gate capacitance of the driving thin film transistor is smaller than that of the switching transistor. The gate capacitance value of the thin film transistor makes the subthreshold swing of the driving thin film transistor larger than the subthreshold swing of the switching thin film transistor. Since the subthreshold swing of the driving thin film transistor is larger, the gray scale display can be better controlled. At the same time, since the sub-threshold swing of the switching thin film transistor is small, the switching performance of the switching thin film transistor is guaranteed, and finally the quality of the display device is improved.

综上所述,本发明提供的薄膜晶体管阵列基板及其制备方法、显示面板及显示装置,通过在形成开关薄膜晶体管的栅极图形之后,在驱动薄膜晶体管的第一栅极绝缘层上形成第二栅极绝缘层,使得驱动薄膜晶体管的栅极绝缘层的厚度大于开关薄膜晶体管栅极绝缘层的厚度,从而使得驱动薄膜晶体管的栅极电容值小于开关薄膜晶体管的栅极电容值,进而使得驱动薄膜晶体管的亚阈值摆幅大于开关薄膜晶体管的亚阈值摆幅,由于驱动薄膜晶体管的亚阈值摆幅较大,可以更好的控制灰阶的显示,同时由于开关薄膜晶体管的亚阈值摆幅较小,保证开关薄膜晶体管的开关性能,最终提升显示器件的品质。To sum up, the thin film transistor array substrate and its preparation method, display panel and display device provided by the present invention are formed by forming the first gate insulating layer of the driving thin film transistor after forming the gate pattern of the switching thin film transistor. Two gate insulating layers, so that the thickness of the gate insulating layer of the driving thin film transistor is greater than the thickness of the switching thin film transistor gate insulating layer, so that the gate capacitance value of the driving thin film transistor is smaller than the gate capacitance value of the switching thin film transistor, and then makes the gate capacitance value of the switching thin film transistor The subthreshold swing of the driving thin film transistor is larger than that of the switching thin film transistor. Because the subthreshold swing of the driving thin film transistor is larger, the gray scale display can be better controlled. At the same time, due to the subthreshold swing of the switching thin film transistor Smaller, to ensure the switching performance of the switching thin film transistor, and finally improve the quality of the display device.

上述描述仅是对本发明较佳实施例的描述,并非对本发明范围的任何限定,本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰,均属于权利要求书的保护范围。The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosures shall fall within the protection scope of the claims.

Claims (10)

1. a preparation method for thin-film transistor array base-plate, is characterized in that, comprising:
Substrate is formed the active area of switching thin-film transistor simultaneously and drives the active area of thin-film transistor;
Form the gate insulator of switching thin-film transistor on the substrate simultaneously and drive the first grid insulating barrier of thin-film transistor;
The gate insulator of described switching thin-film transistor is formed the grid of switching thin-film transistor;
The first grid insulating barrier of described driving thin-film transistor forms second grid insulating barrier;
Described second grid insulating barrier is formed the grid driving thin-film transistor.
2. the preparation method of thin-film transistor array base-plate as claimed in claim 1, it is characterized in that, described gate insulator comprises silicon oxide layer, silicon nitride layer one or a combination set of.
3. the preparation method of thin-film transistor array base-plate as claimed in claim 1; it is characterized in that; after described second grid insulating barrier forms the grid driving thin-film transistor, also comprise: form the source/drain of protective layer, switching thin-film transistor and driving thin-film transistor, organic planarization layer, organic electroluminescent electrode and pixel defining layer successively.
4. a preparation method for thin-film transistor array base-plate, is characterized in that, comprising:
Substrate is formed the grid of switching thin-film transistor simultaneously and drives the grid of thin-film transistor;
Form the gate insulator of switching thin-film transistor on the substrate simultaneously and drive the first grid insulating barrier of thin-film transistor;
The gate insulator of described switching thin-film transistor is formed the active area of switching thin-film transistor;
The first grid insulating barrier of described driving thin-film transistor forms second grid insulating barrier;
Described second grid insulating barrier is formed the active area driving thin-film transistor.
5. the preparation method of thin-film transistor array base-plate as claimed in claim 4, it is characterized in that, described gate insulator comprises silicon oxide layer, silicon nitride layer one or a combination set of.
6. the preparation method of OLED array as claimed in claim 4; it is characterized in that; after described second grid insulating barrier forms the active area driving thin-film transistor, also comprise: form the source/drain of protective layer, switching thin-film transistor and driving thin-film transistor, organic planarization layer, organic electroluminescent electrode and pixel defining layer successively.
7. a thin-film transistor array base-plate, is characterized in that, adopts preparation method's preparation of the thin-film transistor array base-plate according to any one of claim 1 ~ 6.
8. thin-film transistor array base-plate as claimed in claim 7, it is characterized in that, described switching thin-film transistor is top gate type thin film transistor or bottom gate thin film transistor; Described driving thin-film transistor is top gate type thin film transistor or bottom gate thin film transistor.
9. a display floater, is characterized in that, comprises the thin-film transistor array base-plate described in claim 7 or 8.
10. a display unit, is characterized in that, comprises display floater according to claim 9.
CN201510990042.9A 2015-12-24 2015-12-24 Thin film transistor array substrate, preparation method thereof, display panel and display device Pending CN105514118A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106057825A (en) * 2016-08-03 2016-10-26 深圳市华星光电技术有限公司 Array substrate of OLED display device and manufacture method of array substrate
CN106298857A (en) * 2016-08-31 2017-01-04 深圳市华星光电技术有限公司 A kind of organic light-emitting display device and manufacture method thereof
CN106449706A (en) * 2016-10-17 2017-02-22 昆山国显光电有限公司 Display panel and manufacturing method thereof
CN107170784A (en) * 2017-05-25 2017-09-15 京东方科技集团股份有限公司 A kind of OLED array and preparation method thereof and OLED display
WO2019024259A1 (en) * 2017-07-31 2019-02-07 武汉华星光电技术有限公司 Display panel, array substrate and forming method therefor
CN109872998A (en) * 2017-12-04 2019-06-11 京东方科技集团股份有限公司 A kind of array substrate, preparation method, display panel and display device
CN112259553A (en) * 2020-09-30 2021-01-22 昆山国显光电有限公司 Array substrate and preparation method thereof, and display panel
CN117525090A (en) * 2024-01-05 2024-02-06 惠科股份有限公司 Array substrate preparation method, array substrate, display panel and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101834189A (en) * 2009-03-11 2010-09-15 统宝光电股份有限公司 image display system
CN102629621A (en) * 2012-01-09 2012-08-08 京东方科技集团股份有限公司 Circuit, array substrate and manufacturing method thereof, and display
CN103456765A (en) * 2013-09-10 2013-12-18 深圳市华星光电技术有限公司 Active type organic light-emitting device backboard and manufacturing method thereof
CN103715226A (en) * 2013-12-12 2014-04-09 京东方科技集团股份有限公司 OLED array substrate, preparation method thereof, display panel and display device
CN104078484A (en) * 2013-03-27 2014-10-01 三星显示有限公司 Organic light-emitting display apparatus and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101834189A (en) * 2009-03-11 2010-09-15 统宝光电股份有限公司 image display system
CN102629621A (en) * 2012-01-09 2012-08-08 京东方科技集团股份有限公司 Circuit, array substrate and manufacturing method thereof, and display
CN104078484A (en) * 2013-03-27 2014-10-01 三星显示有限公司 Organic light-emitting display apparatus and method of manufacturing the same
CN103456765A (en) * 2013-09-10 2013-12-18 深圳市华星光电技术有限公司 Active type organic light-emitting device backboard and manufacturing method thereof
CN103715226A (en) * 2013-12-12 2014-04-09 京东方科技集团股份有限公司 OLED array substrate, preparation method thereof, display panel and display device

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018023955A1 (en) * 2016-08-03 2018-02-08 深圳市华星光电技术有限公司 Array substrate of oled display device and manufacturing method therefor
US10644237B2 (en) 2016-08-03 2020-05-05 Shenzhen China Star Optoelectronics Technology Co., Ltd. Array substrate for OLED display device
CN106057825A (en) * 2016-08-03 2016-10-26 深圳市华星光电技术有限公司 Array substrate of OLED display device and manufacture method of array substrate
US10559639B2 (en) * 2016-08-31 2020-02-11 Shenzhen China Star Optoelectronics Technology Co., Ltd. Organic light-emitting display device and method for manufacturing the same
CN106298857B (en) * 2016-08-31 2019-03-15 深圳市华星光电技术有限公司 An organic light-emitting display device and a manufacturing method thereof
WO2018040379A1 (en) * 2016-08-31 2018-03-08 深圳市华星光电技术有限公司 Organic light-emitting display device and manufacturing method therefor
US20180190743A1 (en) * 2016-08-31 2018-07-05 Shenzhen China Star Optoelectronics Technology Co., Ltd. Organic light-emitting display device and method for manufacturing the same
CN106298857A (en) * 2016-08-31 2017-01-04 深圳市华星光电技术有限公司 A kind of organic light-emitting display device and manufacture method thereof
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CN107170784A (en) * 2017-05-25 2017-09-15 京东方科技集团股份有限公司 A kind of OLED array and preparation method thereof and OLED display
WO2018214771A1 (en) * 2017-05-25 2018-11-29 京东方科技集团股份有限公司 Oled array substrate, preparation method therefor, and oled display device
WO2019024259A1 (en) * 2017-07-31 2019-02-07 武汉华星光电技术有限公司 Display panel, array substrate and forming method therefor
US10700100B2 (en) 2017-07-31 2020-06-30 Wuhan China Star Optoelectronics Technology Co., Ltd. Display panel, array substrate and method of forming the same
CN109872998A (en) * 2017-12-04 2019-06-11 京东方科技集团股份有限公司 A kind of array substrate, preparation method, display panel and display device
CN112259553A (en) * 2020-09-30 2021-01-22 昆山国显光电有限公司 Array substrate and preparation method thereof, and display panel
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Application publication date: 20160420