CN105513515A - Display device - Google Patents

Abstract

The present invention relates to a display device, comprising: a timing controller; and a panel, connected to the timing controller and comprising a touch drive switch, a display drive switch, a series switch and a plurality of gate drive displacement register circuits; wherein at least one of the gate drive displacement register circuits is electrically connected to the touch drive switch, the display drive switch and the series switch.

Description

display screen

technical field

The present invention relates to a display device and its display panel, in particular to a display device with a touch function and its display panel.

Background technique

Current display devices, such as panels of smart phones, not only display images, but also have touch functions, so that users can operate more intuitively. However, besides the control circuit related to the display screen, the display device with the touch function must also increase the control circuit related to the touch control, thus increasing the manufacturing cost and complicating the wiring arrangement of the circuit.

Therefore, it is necessary to provide a new display device architecture, so that the circuit of the display device with touch function can be simplified and the manufacturing cost can be reduced.

Contents of the invention

An object of the present invention is to provide a display panel, including: a touch drive switch; a display drive switch; a series switch; a plurality of gate drive shift register circuits; The register circuit is electrically connected with the touch driving switch, the display driving switch and the serial switch. Therefore, both the touch driving circuit and the display driving circuit of the display device can be integrated into the gate driving shift register circuit on the panel.

Another object of the present invention is to provide a display device, including: a timing controller; Gate driving shift register circuit; wherein at least one gate driving shift register circuit is electrically connected to the touch driving switch, the display driving switch and the serial switch. Therefore, the touch driving circuit and the display driving circuit of the display device are integrated into the gate drive shift register circuit on the panel to reduce the cost of the overall display device; at the same time, the integration circuit provided by the present invention can achieve simplified Displays the efficacy of device circuit traces.

Description of drawings

In order to further illustrate the technical content of the present invention, the following detailed description is as follows in conjunction with the embodiments and accompanying drawings. in:

FIG. 1 is a schematic structural diagram of a display device of the present invention.

FIG. 2(A) is a main structural diagram of the first embodiment of the display device of the present invention.

FIG. 2(B) is a detailed structure diagram of the gate drive shift register circuit and its front-end circuit of the present invention.

Fig. 3 is a timing chart of signals in the first embodiment of the present invention.

Fig. 4 is a detailed flowchart of the first embodiment of the present invention.

FIG. 5 is a main structural diagram of the second embodiment of the display device of the present invention.

FIG. 6(A) is a signal timing diagram of the timing control signal and the switch control signal in the second embodiment of the present invention.

FIG. 6(B) is a timing diagram of signals related to the first touch and display segment in the second embodiment of the present invention.

FIG. 6(C) is a timing diagram of signals related to the second touch and display section in the second embodiment of the present invention.

detailed description

FIG. 1 is a schematic structural diagram of a display device of the present invention. The display device 10 mainly includes a timing controller 11 and a panel 12 . The panel 12 is connected to the timing controller 11, and includes a plurality of gate drive shift register circuits 13 and a touch and display area 14 with a plurality of gate lines and data lines, that is, the gate drive shift register The register circuit 13 is disposed on the panel 12, wherein the gate drive shift register circuit 13 is connected to the gate line through a first switch SW. In addition, the display device 10 transmits a control signal to the panel 12 through the timing controller 11 to drive touch control and screen display. The timing controller 11 sends at least one switch control signal SV to the first switch SW to control the opening and closing of the first switch SW, and the timing controller 11 can also send a touch driving signal STV(Tx) and A gate line drive signal STV (gate) is sent to the gate drive shift register circuit 13, and in conjunction with the switch control signal SV, when the touch drive is desired, the first switch SW makes the touch drive signal STV (Tx) passes to the touch and display area 14 of the panel. When displaying a picture, the first switch SW allows the gate line drive signal STV (gate) to pass to the touch and display area 14 of the panel. . It should be noted that the timing when the first switch SW passes the touch driving signal STV(Tx) is separated from the timing when the first switch SW passes the gate line driving signal STV(gate).

Please refer to FIG. 1 again, the touch and display area 14 is preferably divided into a plurality of touch and display segments (segment) 140, and each touch and display segment 140 has a touch driving block Tx and a plurality of gate lines GL.

The timing controller 11 has a touch and display integrated controller 15 to generate the control signal SV of the switch, which can output a timing control signal CKV to determine the timing of touch and screen display driving, and according to the control signal SV, sent to the first switch SW for controlling the first switch SW. In addition, the timing controller 11 also generates the touch driving signal STV(Tx) and the gate line driving signal STV(gate), and transmits the driving signal and the timing control signal CKV to the gate driving displacement The register circuit 13 forms an integrated enable signal MFP. In addition, the touch and display integrated controller 15 can also be connected to a switch control voltage level shifter 16, a gate line driving voltage level shifter 17 and a touch driving voltage level shifter 18, so as to The voltage level of the signal to be transmitted is increased.

Fig. 2 (A) is the main structural diagram of the first embodiment of the display device of the present invention, there are a plurality of gate driving shift register circuits 13 on the panel 12, and in order to make the description clearer, this embodiment is based on two The gate drive shift register circuit 13 corresponds to a touch and display section 140 as an example, and the total number of the gate drive shift register circuits 13 on the panel 12 is reduced to four. In fact, each touch The dual display section 140 may correspond to one or more than two gate driving shift register circuits 13 , and the total number of the gate driving shift register circuits 13 on the panel 12 is not limited to four. In addition, the first switch SW is preferably composed of a touch driving switch SW1 and a display driving switch SW2, so that the touch driving signal STV(Tx) and the gate line driving signal STV can be controlled at an appropriate time point respectively. (gate) pass. In addition, in addition to the touch driving switch SW1 and the display driving switch SW2, each touch and display section 140 on the panel 12 also includes a serial switch SW3, which is connected to the first Between the first gate drive shift register circuit 13-1 and the second gate drive shift register circuit 13-2, it is used to allow the potential of the gate line drive signal STV (gate) to pass through, that is, the first gate drive shift register circuit 13-2 The gate drive shift register circuit 13-1 transmits the potential of the gate line drive signal STV(gate) to the second gate drive shift register circuit 13-2 via the serial switch SW3. In fact, the second gate drive shift register circuit 13-2 is connected to the second gate line and a front-end circuit GTHZ2 of the third gate drive shift register circuit 13-3, thus the The potential of the gate line driving signal STV(gate) is transmitted to the second gate line and the front-end circuit GTHZ2.

It is worth noting that the display panel 12 has a scan time and an interval time when displaying images, the touch drive switch SW1 is turned on during the interval time when the panel 12 displays images, and the display drive switch SW2 is turned on during the scan time. enabled in .

In addition, in the first touch and display section 140-1, the touch driving switch SW1 and the display driving switch SW2 are preferably composed of a thin-film transistor (Thin-Film Transistor), but it is not limited. The first terminal of the thin film transistor is connected to the first gate driving shift register circuit 13 , and the other terminals are respectively connected to a data line DL1 or a gate line GL1 . Similarly, in the second touch and display section 140-2, one end of the switches SW1' and SW2' is connected to the third gate drive shift register circuit 13-2', and the other end is connected to Each is connected to another data line DL2 and another gate line GL3 .

Please refer to FIG. 2(A) again, the block in the upper left corner is the touch and display integrated controller 15, which has a first path connected to the gate terminals of all touch drive switches SW1 on the panel 12 and has a second The path connects the gate terminals of all the display driving switches SW2, and thereby transmits the switch control signal SV to control the switching on of the switches. In addition, the touch and display integrated controller 15 also has a third path and a fourth path connected to the first gate drive shift register circuit 13-1, the touch drive signal STV(Tx), the The gate line driving signal STV(gate) and the timing control signal CKV are sent to the first gate driving shift register circuit 13 - 1 to be integrated into the integrated enabling signal MFP1 .

FIG. 2(B) is a detailed structure diagram of the gate drive shift register circuits 13-1-13-4 and the front-end circuits GTHZ1-GTHZ2 of the present invention. As shown in FIG. 2(B), the touch drive signal STV(Tx) and the gate line drive signal STV(gate) are first integrated in the front-end circuit GTHZ1, and then integrated with the timing control circuit CKV in the first A gate-driven shift register circuit 13-1 to form the integrated enable signal MFP1, and then the first gate-driven shift register circuit 13-1 in the integrated enable signal MFP1 is related to the gate line drive signal STV( gate) is transmitted to the second gate drive shift register circuit 13-2, and integrated with the timing control signal CKV at an appropriate time point, and then output to another front-end circuit GTHZ2. The front-end circuit GTHZ2 integrates the part of the gate line driving signal STV(gate) with the external touch driving signal STV(Tx), and integrates the timing control signal CKV into the third gate driving shift register circuit 13-3, and then forms the integration enable signal MFP2.

FIG. 3 is a signal timing diagram in the first embodiment, please refer to FIG. 2(A). In this embodiment, the first touch and display section 140-1 includes two gate lines GL1 and GL2 respectively correspond to the first gate driving shift register circuit 13-1 and the second gate driving shift register circuit 13-2. Fig. 3 mainly shows the timing changes of signals of multiple nodes A, C, D, and E in Fig. 2(A), and the states of each node will be described later.

First is Node A (NodeA), which is located at the touch and display integrated controller 15. The gate line driving signal STV (gate) is boosted by the gate line driving voltage level shifter 17 and then input to the At the position before the front-end circuit GTHZ1, it can be known from FIG. 3 that the gate line driving signal STV(gate) has a gate line driving potential (Vgate(off) to Vgate(on)). Similarly, the touch driving signal STV(Tx) is boosted by the touch driving voltage level shifter 18 and input to the front-end circuit GTHZ1, and has a touch driving potential (Vtx(off) to Vtx(on) ). The front-end circuit GTHZ1 can form the start signal MFS with the touch drive potential and the gate line drive potential, and input the start signal and the timing control signal CKV to the first gate drive shift register circuit 13- 1. To obtain the operating timing to form the integration activation signal MFP1.

In addition, the node B (NodeB) in FIG. 2(A) is located between the serial switch SW3 and the second gate drive shift register circuit 13-2, and the timing of the timing control signal CKV proceeds to the When the first gate line driving timing pulse gate1 is passed, the gate line driving potential (Vgate(off) to Vgate(on)) in the integration enable signal MFP1 will pass through the node B.

Node C (NodeC) is located at the output end of the first gate drive shift register circuit 13-1, and is connected to the touch drive switch SW1, the display drive switch SW2 and the serial switch SW3, in other words, the node The signal timing diagram on C is the timing diagram of the integration start signal MFP1. From the signal timing diagram of node C, it can be seen that when the timing of the timing control signal CKV reaches the touch driving timing pulse Tx1, the touch driving switch SW1 receives the potential of the touch driving switch control signal SV1(TX) (Vsv1( off) to Vsv1(on)), so that the touch drive potential (Vtx(off) to Vtx(on)) in the integrated start signal MFP1 will pass through the touch drive switch SW1, so at the timing of node C It will have the touch driving potential (Vtx(off) to Vtx(on)); and when the timing control signal CKV is carried out to the first gate line driving timing pulse Gate1, the display driving switch SW2 receives the display driving switch The potential of the control signal SV2 (gate) (Vsv2 (off) to Vsv2 (on)) is turned on, and the serial switch SW3 receives the potential of the serial switch control signal VS3 (Vsv3 (off) to Vsv3 (on)), The gate line drive potential (Vgate(off) to Vgate(on)) in the integration enable signal MFP1 will pass through the display drive switch SW2 and the serial switch SW3, so the timing of the node C will have the Gate line driving potential (Vgate(off) to Vgate(on)).

Node D (NodeD) is located on a shared electrode line (VCOMline), which is connected to a data line DL1 connected to the touch drive switch SW1, and then receives the touch drive potential in the integrated activation signal MFP1, After that, the touch driving potential is coupled to at least one touch receiving terminal (not shown in the figure) through the shared electrode line. Therefore, when the timing of the timing control signal CKV reaches the touch driving timing pulse Tx1, the node D also has the touch driving potential (Vtx(off) to Vtx(on)).

The node E (NodeE) is located between the first gate line GL1 connected to the display driving switch SW2 and the first pixel unit 31, and the first pixel unit 31 receives the gate line in the integration start signal MFP1 driving potential to drive the first gate line for scanning. Therefore, when the timing of the timing control signal CKV reaches the first gate-line driving timing pulse gate1, the node E will have the gate-line driving potential (Vgate(off) to Vgate(on)).

In addition, on the node F in FIG. 2(A), the second gate drive shift register circuit 13-2 receives the gate line drive potential (Vgate(off) to Vgate( In addition to on)), the timing control signal CKV will be received from the outside, and when the timing of the timing control signal CKV proceeds to the second gate line driving timing pulse gate2, the gate line driving potential (Vgate( off) to Vgate(on)) to the first pixel unit 32 on the second gate line GL2, thereby driving the second gate line GL2 to scan.

Thus, the operation of the first touch and display section 140-1 can be completed. It should be noted that although the first touch and display section 140-1 has two gate lines in this embodiment, it can actually have more gate lines, and is not limited to one gate drive shift buffer A gate drive circuit controls one gate line, in fact, it can also be changed to a gate drive shift register circuit to control multiple gate lines.

Please refer to FIG. 3 again, the touch and display section 140-2 includes two gate lines, and one gate driving shift register circuit controls one gate line, and please also refer to FIG. 2(A). When the timing control signal CKV reaches the second gate line driving timing pulse gate2, the second gate driving shift register circuit 13-2 transmits the gate line driving potential (Vgate(off) to Vgate( on)) to the second gate line GL2, the gate line drive potential (Vgate(off) to Vgate(on)) will also be transmitted to the third gate drive shift register circuit 13-3 The front-end circuit GTHZ2, the front-end circuit GTHZ2 combines the gate line driving signal STV(gate) and the touch driving signal STV(Tx) from the touch and display integrated controller 15 into the start signal MFS, and combines the The timing control signal CKV is input to the third gate driving shift register circuit 13 - 3 together to form the second integration enable signal MFP2 .

Node G (NodeG) is located at the output end of the third gate drive shift register circuit 13-3, that is, the signal passing through node G is the integrated enable signal MFP2, and node G is connected to the touch drive switch SW1', The display driving switch SW2' and the serial switch SW3'. As shown in FIG. 3(C), when the timing of the timing control signal CKV reaches the touch driving timing pulse Tx1, the switch SW1' is turned on, so that the touch driving potential (Vtx(off) to Vtx(on) ) passes through the touch drive switch SW1', so the touch drive potential (Vtx(off) to Vtx(on)) will be present on the timing node G at this time; and when the timing control signal CKV is transmitted to the third gate When the pole line driving timing pulse Gate3, the switches SW2' and SW3' are turned on, so that the gate line driving potential (Vgate(off) to Vgate(on)) will pass through the display driving switch SW2' and the serial switch SW3 ', so that the node G will have the gate line driving potential (Vgate (off) to Vgate (on)) passing through. At this time, the first pixel unit 33 on the third gate line GL3 connected to the switch SW2' will receive the gate line drive potential, and drive the third gate line GL3 to scan. The timing of the third gate line GL3 also has the gate line driving potential (Vgate (off) to Vgate (on)).

Like the second gate drive shift register circuit 13-2, the fourth gate drive shift register circuit 13-4 will also receive the timing control signal from the outside in addition to receiving the gate line drive potential CKV, when the timing control signal CKV reaches the fourth gate line driving timing pulse Gate4, the gate line driving potential is output to the first pixel unit 34 of the fourth gate line GL4, so at this time The fourth gate line GL4 has the gate line driving potential (Vgate(off) to Vgate(on)) in sequence.

It is worth noting that the second touch and display section 140-2 still has a touch driving switch SW1', which is synchronized with the touch driving switch SW1 of the first touch and display section 140-1. Turn on, because the touch drive of the present invention will only be generated during the interval of the screen, so the touch drive switch SW1 or SW1' of each touch and display section is turned on at the same time when the screen is switched, and Turn off when the gate line starts to scan.

In addition, the display driving switches (SW2, SW2') and the cascade switches (SW3, SW3') can also be turned on at the same time, but it is not limited thereto.

It should be noted that the turn-on time of the touch-driven switches (SW1, SW1') and the turn-on time of the serial switches (SW3, SW3') do not overlap with each other.

FIG. 4 is a detailed flowchart of the first embodiment of the present invention, please refer to FIG. 3 together. In a time t1, the touch and display integrated controller 15 generates the control signals VS1(Tx)-VS3 of the switches SW1-SW3, the touch driving signal STV(Tx), and the gate line driving signal STV (gate); in a time t2 following the time t1, the control signals SV1-SV3 of the switches SW1-SW3 are boosted and then transmitted, and the touch driving signal STV(Tx) and the gate line are driven The signal STV(gate) is boosted and transmitted together with the timing control signal CKV to the first gate drive shift register circuit 13-1, and the boosted touch drive signal STV(Tx) is combined with The timing control signal CKV is transmitted to the third gate drive shift register circuit 13-3;

In a time t3 following time t2 (that is, when the timing control signal CKV reaches the touch driving timing pulse Tx1), all touch driving switches (SW1, SW1') on the panel 12 receive the touch driving switch The control signal SV1 (Tx) is turned on, so that the touch driving potential transmitted by the first gate driving shift register circuit 13-1 and the third gate driving shift register circuit 13-3 can be Enter the touch and display area 14 of the panel 12 through the touch driving switch SW1; in a time t4 following the time t3 (that is, when the timing control signal CKV is carried out to the first gate line driving timing pulse Gate1 ), the display drive switch SW2 connected to the first gate line GL1 receives the display drive switch control signal SV2 (gate) and turns on, so that the first gate drive shift register circuit 13-1 transmits the The gate line drive potential can enter the first gate line GL1 through the display drive switch SW2; at the same time, at time t4, the serial switch SW3 connected to the first gate drive shift register circuit 13-1 receiving the serial switch control signal SV3 and turning it on, so that the gate line driving potential transmitted by the first gate drive shift register circuit 13-1 can be transmitted to the second gate line drive potential through the serial switch SW3 A gate drive shift register circuit 13-2; in a time t5 following time t4 (that is, when the timing control signal CKV is carried out to the second gate line drive timing pulse Gate2), the second gate drive The shift register circuit 13-2 transmits the gate line drive potential to the second gate line GL2 and the third gate drive shift register circuit 13-2;

In a time t6 following time t5 (that is, when the timing control signal CKV reaches the third gate line driving timing pulse Gate3), the display driving switch SW2 connected to the third gate line GL3 receives the display driving The switch control signal SV2 (Tx) is turned on, and the third gate drive shift register circuit 13-3 transmits the gate line drive potential to the third gate line GL3; at the same time, connects the fourth gate The third switch SW3 of the driving shift register circuit 13-4 is turned on by receiving the serial switch control signal SV3, so that the gate line driving potential can be transmitted to the fourth gate driving shift register circuit 13-4; In a time t7 following time t6 (that is, when the timing control signal CKV reaches the fourth gate line driving timing pulse Gate4), the fourth gate driving shift register circuit 13-4 will drive the gate line The driving potential is transmitted to the fourth gate line GL4. In this way, the operation process of a touch drive and a screen display can be completed, and in the next time t8 following the time t7, the step of turning on the touch drive switch SW1 at the time t3 is rerun (or the rerun time t1-t3 step), that is, the operation process of the next touch drive and a screen display starts from time t8.

Therefore, the first embodiment of the present invention integrates the touch drive and gate drive circuits and directly arranges them on the panel of the display device to reduce the cost of the overall system, and simplifies the circuit routing through timing configuration Effect.

FIG. 5 is a main structural diagram of the second embodiment of the display device of the present invention. This embodiment is still an example where two gate drive shift register circuits 13 correspond to a touch and display section 140-1. The total number of gate driving shift register circuits 13 is also four, but there is no limitation in practice. Like the first embodiment, the first switch SW is preferably composed of a touch driving switch SW1 and a display driving switch SW2, so that the touch driving signal STV(Tx) and the gate The potential of the polar line drive signal STV(gate) passes. The difference from the first embodiment is that the second embodiment does not have the serial switch SW3, which is because the gate drive shift register circuit in the second embodiment uses different paths to transmit the touch drive potential and The gate line driving potential, in other words, is directly connected to the next gate driving shift register circuit through the path for transmitting the gate line driving potential. Since the independent paths are used, the second embodiment does not need to combine the touch driving signal STV(Tx) and the gate line driving signal STV(gate), so the front-end circuit GTHZ is not required. It is only necessary to integrate the touch driving signal STV(Tx) and the gate line driving signal STV(gate) with CKV respectively on the gate driving shift register circuit.

FIG. 6(A) is a signal timing diagram of the timing control signal CKV and the switching control signals SV1 - SV2 in the second embodiment. The timing control signal CKV is sequentially composed of a touch driving timing pulse Tx1 and a plurality of gate line driving timing pulses Gate1 to Gate4. In addition, the touch driving switch control signal SV1(Tx) is corresponding to the touch driving timing pulse Tx1 of the timing control signal CKV, and synchronously generates a control voltage to turn on the touch driving switch SW1. The display driving switch control signal SV2 (gate) is corresponding to the first gate line driving timing pulse Gate1, and synchronously generates a control voltage to control the display driving switch SW2 to turn on.

FIG. 6(B) is a timing diagram of signals related to the first touch and display section 140-1 in the second embodiment. The first node is M, which is located in the first gate drive shift register circuit 13- 1 connected to the path of the touch drive switch SW1, the first gate drive shift register circuit 13-1 integrates the timing control signal CKV and the touch drive signal STV(Tx) into an integrated touch drive The signal STV'(Tx)1 is transmitted to the coupling line VCOM through the touch driving switch SW1 and the first data line DL1, so when the timing control signal CKV reaches the touch driving timing pulse Tx1 , the timing of the node M will have the touch driving potential (VTx(off) to VTx(on)). The node N is located on the path where the first gate drive shift register circuit 13-1 is connected to the display drive switch SW2 and the second gate drive shift register circuit 13-2. The drive shift register circuit 13-1 integrates the timing control signal CKV and the gate line drive signal STV(gate) into an integrated gate line drive signal STV'(gate)1, and transmits it through the touch drive switch SW1 to the first scanning line GL1, and at the same time transmit the integrated gate line drive signal STV'(gate)1 to the second gate drive shift register circuit 13-2, so when the timing control signal CKV goes to When the first gate line drives the timing pulse Gate1, the timing of the node N will have the gate line driving potential (Vgate (off) to Vgate (on)), and at the same time, the timing of the first scanning line GL1 will also be will have the gate line drive potential. In addition, when the timing control signal CKV reaches the second gate line driving timing pulse Gate2, the second scanning line GL2 will receive the gate signal from the second gate driving shift register circuit 13-2. line driving signal STV'(gate)2, and the second gate driving shift register circuit 13 transmits the gate line driving potential to the third gate driving shift register circuit 13-3.

FIG. 6(C) is a timing diagram of signals related to the second touch and display section in the second embodiment, and its configuration is similar to that of FIG. 6(B). When the timing control signal CKV reaches the touch driving timing pulse When Tx1, the timing of the node X will have the touch driving potential (VTx(off) to VTx(on)). When the timing control signal CKV reaches the third gate line driving timing Gate3, the timing of the node Y will have the gate line driving potential (Vgate(off) to Vgate(on)), and the third gate line The timing of the scanning line GL3 also has the signal (STV'(gate) 3 ) of the gate line driving potential. When the timing control signal CKV reaches the fourth gate line drive timing pulse Gate4, the fourth scan line GL4 receives the gate line drive potential from the fourth gate drive shift register circuit 13-4 (the potential of STV' (gate) 4), so its timing will have the gate line driving potential (Vgate (off) to Vgate (on)).

Therefore, the present invention provides the second embodiment, the touch drive and gate drive circuits can be respectively arranged on the panel of the display device to reduce the cost of the overall system, and achieve simplified circuit routing through timing configuration. line effect.

The above-mentioned embodiments are only examples for convenience of description, and the scope of rights claimed by the present invention should be determined by the scope of the claims, rather than limited to the above-mentioned embodiments.

Claims (10)

1. A display panel, comprising: a touch-driven switch; a display drive switch; a serial switch; multiple gate drive shift register circuits; Wherein at least one gate drive shift register circuit is electrically connected with the touch drive switch, the display drive switch and the serial switch. 2. The display panel as claimed in claim 1, wherein at least one gate driving shift register circuit also transmits a gate line driving signal to another gate driving shift register circuit through the serial switch. 3. The display panel as claimed in claim 2, wherein the turn-on time of the cascaded switch and the turn-on time of the touch-driven switch do not overlap with each other. 4. The display panel as claimed in claim 1, wherein the display panel has a scan time and an interval time when displaying images. 5. The display panel as claimed in claim 4, wherein the touch-driven switch is turned on during the interval time. 6. The display panel as claimed in claim 4, wherein the display driving switch is turned on during the scan time. 7. The display panel as claimed in claim 1, further comprising a switch control voltage level shifter, the switch control voltage level shifter outputs a touch drive switch control signal and a display drive switch control signal to the The touch driving switch is connected with the display driving switch. 8. A display device comprising: a timing controller; and A panel, connected to the timing controller, and including a touch drive switch, a display drive switch, a series switch and a plurality of gate drive shift register circuits; Wherein at least one gate drive shift register circuit is electrically connected with the touch drive switch, the display drive switch and the serial switch. 9. The display device as claimed in claim 8, wherein at least one gate driving shift register circuit also transmits a gate line driving signal to another gate driving shift register circuit through the serial switch. 10. The display device as claimed in claim 8, wherein the turn-on time of the serial switch and the turn-on time of the touch-driven switch do not overlap with each other.