CN105510803A - Integrated circuit testing device and method - Google Patents
Integrated circuit testing device and method Download PDFInfo
- Publication number
- CN105510803A CN105510803A CN201511022400.3A CN201511022400A CN105510803A CN 105510803 A CN105510803 A CN 105510803A CN 201511022400 A CN201511022400 A CN 201511022400A CN 105510803 A CN105510803 A CN 105510803A
- Authority
- CN
- China
- Prior art keywords
- integrated circuit
- test
- testing
- tested
- tester
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 234
- 238000000034 method Methods 0.000 title abstract description 19
- 239000004606 Fillers/Extenders Substances 0.000 claims description 40
- 238000010998 test method Methods 0.000 claims description 15
- 238000006073 displacement reaction Methods 0.000 claims description 4
- 238000004804 winding Methods 0.000 claims description 4
- 241000283690 Bos taurus Species 0.000 claims description 3
- 230000003044 adaptive effect Effects 0.000 abstract 2
- 230000006870 function Effects 0.000 description 17
- 238000009434 installation Methods 0.000 description 5
- 238000004891 communication Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000011990 functional testing Methods 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000007664 blowing Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009432 framing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention relates to an integrated circuit testing device comprising an adaptive board, a testing base, a tester, and a PC. The adaptive board is equipped with a test region containing multiple test points and the data output interface of the tester. Each of the multiple test points is provided with a unique identifier that can be identified by the tester. The testing base is provided with insert ports connected with the pins of an integrated circuit. The testing base is located in the test region and the insert ports correspond to the test points each other one to one. The tester is provided with data input interfaces correspondingly connected with the multiple test points and used for testing the electrical parameter of the integrated circuit connected via the testing base. The PC is connected with the tester. Further, an integrated circuit testing method is provided. According to the integrated circuit testing device and method, multiple integrated circuits to be tested are placed on the testing base disposed in the test region that can be identified by the tester, and the PC transfers a test program to the tester in order to test the integrated circuits, thereby achieving high test efficiency, low cost, and good practicability.
Description
Technical field
The present invention relates to element test application, particularly relate to integrated circuit test system and method.
Background technology
Integrated circuit (IntegratedCircuit, IC) be a kind of microelectronic device, by adopting certain technique, together with the elements such as transistor required in a circuit, diode, resistance, electric capacity and inductance and wire interconnects, be produced on a fritter or a few fritter semiconductor wafer or dielectric substrate, then be encapsulated in a shell, become the microstructure with required circuit function.When functional test is carried out to electronic product, be generally that functional test is carried out to the integrated circuit of electronic product.When carrying out functional test to integrated circuit, need each functional pin of integrated circuit to be connected to proving installation by Integral circuit keyset.
Current arrangement for testing integrated circuit, in the process of testing integrated circuits, can only test an integrated circuit each time, can not realize testing fast multiple different integrated circuit (IC) chip simultaneously, and like this in the process of test, testing efficiency is low, cost is high.
Summary of the invention
Based on this, be necessary to realize the test of multiple different integrated circuit (IC) chip, testing efficiency is low, cost is high problem for arrangement for testing integrated circuit simultaneously, a kind of arrangement for testing integrated circuit and method are provided.
A kind of arrangement for testing integrated circuit, for testing integrated circuits, comprises card extender, testing base, tester and PC; Described card extender is provided with the test section comprising multiple test point and the data output interface being connected described tester; Multiple described test point has respectively can by the unique identification of described tester identification;
Described testing base has the insert port for connecting described integrated circuit pin, and to connect described integrated circuit, described testing base is positioned at described test section, and insert port and described test point one_to_one corresponding;
Described tester is provided with the Data Input Interface that connect corresponding to multiple described test point, for testing the electrical parameter of the described integrated circuit connected by described testing base;
Described PC is connected with described tester, tests described integrated circuit for test procedure being sent to described tester.
Wherein in an embodiment, described test section is provided with 441 test points be arranged in array, and the spacing between adjacent described test point is 2.45 millimeters; Wherein, by testing, winding displacement is corresponding with the Data Input Interface of described tester to be connected described 425 test points.
Wherein in an embodiment, described Data Input Interface is also provided with the cattle horn socket connector of 2.45 millimeters.
Wherein in an embodiment, described card extender is multilayer board.
Wherein in an embodiment, described testing base is provided with Connection Block, and described Connection Block is for being electrically connected described integrated circuit and described card extender.
Wherein in an embodiment, described PC is also provided with storage unit, for storing the test procedure of the model of tested integrated circuit, judged result and described tested integrated circuit.
A kind of integrated circuit (IC) testing method is provided in addition, comprises the steps:
Connect integrated circuit to be tested, testing base, card extender, tester and PC successively;
Determine that each pin of described integrated circuit to be tested corresponds to the position of the corresponding test point of described card extender;
According to the function type of each pin of described integrated circuit to be tested, function type definition is carried out to the test point on described card extender;
According to DC parameter test principle specification, treat testing integrated circuits and test, and judge the result of described integrated circuit to be tested.
Wherein in an embodiment, described in treat the step that testing integrated circuits carries out testing and comprise:
Set the criterion of the input and output test result corresponding to power pins of described integrated circuit to be tested;
Reverse biased current source is added to described integrated circuit input output to be tested and power pins;
Test the magnitude of voltage of described integrated circuit input output to be tested and power pins;
The performance of integrated circuit to be tested is judged according to described criterion.
Wherein in an embodiment, the criterion setting described integrated circuit input output to be tested test result corresponding to power pins is: the input and output of described integrated circuit to be tested and the magnitude of voltage of power pins are all between-1.2 volts to-0.2 volt.
Wherein in an embodiment, if the model of described integrated circuit to be tested is identical with the model of the integrated circuit stored in storage unit in PC, then directly call the test procedure of described tested integrated circuit.
Utilize said integrated circuit proving installation and method, be placed in testing base by multiple integrated circuit to be tested, testing base is positioned at that have can on the test section of the multiple test point of unique identification of tested instrument identification and the card extender of the data output interface of connecting test instrument; Tester is connected with card extender by the Data Input Interface connected corresponding to multiple test point, for testing the electrical parameter of the integrated circuit connected by testing base; PC sends test procedure to tester and tests integrated circuit.Can test multiple integrated circuit simultaneously, testing efficiency is high, cost is low, practical.
Accompanying drawing explanation
Fig. 1 is arrangement for testing integrated circuit structural framing figure;
Fig. 2 is test section marked graph;
Fig. 3 is integrated circuit (IC) testing method process flow diagram;
Fig. 4 is an embodiment integrated circuit (IC) testing method process flow diagram.
Embodiment
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.Preferred embodiment of the present invention is given in accompanying drawing.But the present invention can realize in many different forms, is not limited to embodiment described herein.On the contrary, provide the object of these embodiments be make the understanding of disclosure of the present invention more comprehensively thorough.
Unless otherwise defined, all technology used herein and scientific terminology are identical with belonging to the implication that those skilled in the art of the present invention understand usually.The object of term used in the description of the invention herein just in order to describe specific embodiment, is not intended to limit the present invention.Term as used herein "and/or" comprises arbitrary and all combinations of one or more relevant Listed Items.
As shown in Figure 1 be arrangement for testing integrated circuit structural framing figure, for the quality of testing integrated circuits 500 performance, comprise card extender 100, testing base 200, tester 300 and PC 400.Card extender 100 is provided with and comprises the test section 110 of multiple test point and the data output interface 120 of connecting test instrument 300; Multiple test point has respectively can the unique identification that identifies of tested instrument 300.Testing base 200 has the insert port 210 for connecting integrated circuit 500 pin, to connect integrated circuit 500.Testing base 200 is positioned at test section 110, and the insert port 210 in testing base 200 connects one to one with multiple test points of card extender 100.Tester 300 is provided with the Data Input Interface 310 that connect corresponding to multiple test points of multiple card extender 100, for testing the electrical parameter of the integrated circuit 500 connected by testing base 200; PC 400 is connected with tester 300, tests for test procedure being sent to tester 300 pairs of integrated circuit 500.
As shown in Figure 2 be the distribution plan of test section on card extender; In figure, test section 110 is provided with 441 test points of be arranged in array (21*21), and the spacing between adjacent test point is 2.45 millimeters; Wherein have 16 test points vacant, all the other 425 test points have respectively can the unique identification that identifies of tested instrument 300.In figure, the test point in test section 110 has an one's own identity coding, being designated (69) of the test point of such as the second row secondary series, and this test point (69) can identify by tested instrument 300.
Card extender 100 is multilayer board (PrintedCircuitBoard, PCB), card extender 100 is also provided with the data output interface 120 for connecting test instrument 300, there is uniquely identified test point and data output interface 120 connects one to one.There is in test section 110 uniquely identified test point and can carry out exchanges data by data output interface 120 and tester 300.Tester 300 is also provided with Data Input Interface 310 simultaneously, Data Input Interface 310 and data output interface 120 one_to_one corresponding, connected by test winding displacement between card extender 100 and tester 300, namely tester 300 can identify each test point on card extender 100.Input interface 310 is also provided with the cattle horn socket connector of 2.45 millimeters, is convenient to the installation and removal to test winding displacement.
Testing base 200 is PGA (PinGridArray) test bench of standard, is called contact pin grid array packages.Be one of cartridge-type encapsulation, the vertical pins of its bottom surface is in array-like arrangement.Encapsulation base material all adopts multilayer ceramic substrate substantially, and also useable glass epoxy resin printed base plate replaces, for high speed lsi (LargeScaleIntegration, LSI).In the present embodiment, number of pins is 441 (21*21), and pin centre distance is generally 2.54mm, wherein has 16 pins to be vacant pin, and all the other 425 pins and card extender have uniquely identified test point one_to_one corresponding.
Testing base 200 is provided with Connection Block 220, and Connection Block 220 is for being electrically connected integrated circuit 500 and card extender 100.Connection Block 220 refers to the device of connection two active devices, for transmission current or signal, is also called connector, plug and socket.The quantity of Connection Block 220 can be determined according to the quantity of integrated circuit 500 to be tested.Owing to testing base 200 there being 425 test points that can be identified, and the pin comb of integrated circuit 500 is general within 20, so can multiple integrated circuit 500 is inserted in testing base by Connection Block 220 simultaneously, can test multiple integrated circuit simultaneously.
Tester 300 is DC parameter test instrument, and DC test is the steady-state method of test being used for determining device electrical quantity based on Ohm law.Such as, leakage current test is exactly apply voltage at input pin, this makes that the resistance between input pin and power supply or ground has electric current to pass through, then the test of its this pin electric current is measured, output driving current test on output pin, apply certain electric current exactly, then measure this pin and or power supply between voltage difference.In the present embodiment, card extender 100 can be connected with the tester 300 of different model and uses, and being not limited to DC parameter test instrument, can also be numeric type tester, function logic type tester etc.
Tester 300 and PC 400 use Peripheral Component Interconnect standard (PeripheralComponentInterconnect, PCI) to carry out connecting communication, mainly treat the test that testing integrated circuits 500 carries out relevant DC parameter.In the present embodiment, tester provides operating voltage, trims fuse bit for integrated circuit to be tested.Tester and PC use Peripheral Component Interconnect standard (PeripheralComponentInterconnect, PCI) connecting communication is carried out, mainly treat the test that testing integrated circuits carries out relevant DC parameter, in addition, also auxiliary PC carries out the test of logic function to to-be-measured integrated circuit, as provided certain operating voltage for integrated circuit to be tested, trim related fuse byte etc.Fuse bit refers to making alive on specific pin, enough electric currents, just can blow this root fuse of the inside, and after blowing, the program in sheet just cannot be read out to have rewritten, and can only be used for running.Fuse bit is the position can reading fuse state on a specific address, and 0 expression fuses, and 1 expression does not fuse.
Further can be understood as:
When testing integrated circuits 500, integrated circuit 500 to be tested is inserted in testing base 200 by Connection Block 220.By determining that each pin of integrated circuit 500 is inserted in the particular location in testing base 200, corresponding, also just can determine that each pin of integrated circuit 500 corresponds to each test point concrete in card extender 100.Then on PC 400, the function type of each test point according to each pin of integrated circuit 500 is defined; Tester 300 is add reverse biased current in conjunction with PC 400 pairs of integrated circuit 500, records corresponding magnitude of voltage, finally each test item is provided to the result of Pass or Fail.Pass refers to that device reaches or surmounted device design specification; Fail is then contrary, and device does not reach designing requirement, can not be used for final application.
In the present embodiment, storage unit (not shown) is set, for storing the model of tested integrated circuit, the test procedure to the judged result of this performance of integrated circuits quality and the used of this integrated circuit in PC 400.
In the present embodiment, due to cell stores, the DC parameter test result of the model of integrated circuit, integrated circuit or judged result, test the test procedure of this integrated circuit in addition.According to statistics, this integrated circuit (IC) apparatus is minimum tested 15000 kinds of dissimilar integrated circuit (IC) chip, had confirmed that its practicality is high, powerful.In follow-up test process, if when the model of electrical testing integrated circuit 500 also stores in the memory unit, then do not need again to edit test procedure, directly can call, save time, efficiency is high.Owing to storing DC parameter test result or the judged result of all kinds of chip, may be used for the behavior pattern analyzing dissimilar integrated circuit, be convenient to the screening to integrated circuit.
As shown in Figure 3 be integrated circuit (IC) testing method process flow diagram, comprise the steps:
S100: connect integrated circuit to be tested, testing base, card extender, tester and PC successively.
With reference to figure 1, card extender 100, tester 300 and PC 400 are electrically connected successively, and are plugged in testing base 200 by integrated circuit 500 to be tested by Connection Block 220, testing base 200 is fixedly connected on the test section 110 of card extender 100.Wherein, the number of integrated circuit 500 to be tested can be multiple, and the type of integrated circuit 500 to be tested also can be identical or different, wherein, the type of integrated circuit 500 divides according to the pin number of integrated circuit, if pin number is identical, thinks that the quantity of multiple integrated circuit is all identical; If pin number is different, then think that the quantity of integrated circuit is different.
S200: determine that each pin of integrated circuit to be tested corresponds to the position of the corresponding test point of card extender.
Each for integrated circuit to be tested pin is connected with testing base by Connection Block, and determines that the pin of each integrated circuit to be tested corresponds to the position of the corresponding test point of card extender.With reference to figure 2, the integrated circuit on to be tested has three, and the type of integrated circuit is different; First integrated circuit is 6 pins, represents in figure by solid box; Second integrated circuit is 8 pins, is indicated by the dashed box in figure; 3rd integrated circuit is 16 pins, represents in figure by dotted box.Such as: the first pin of the first integrated circuit is to six test points (285,284,319,309,308,345) on the 6th pin (P1-P6) respectively corresponding card extender; Accordingly, determine the second integrated circuit respectively, position that each pin of the 3rd integrated circuit corresponds to the corresponding test point of card extender.
S300: according to the function type of each pin of integrated circuit to be tested, carries out function type definition to the test point on card extender.
After determining that each pin of integrated circuit to be tested corresponds to the position of corresponding test point of card extender, then determine the function type of each pin of integrated circuit to be tested, its function type comprises power pins, grounding pin and input and output pin.Correspondingly, according to the function type of each pin of integrated circuit to be tested, treat the corresponding test point that each pin of testing integrated circuits corresponds to card extender and carry out function type definition.
For the first integrated circuit to be tested, it is six pin chips of a standard, and six pins are input and output (IO) pin, because its power pins only has one, at IC interior, this power pins can be used as input and output (IO) pin.First pin of the first integrated circuit, to six test points (285,284,319,309,308,345) on the 6th pin (P1-P6) respectively corresponding card extender, can carry out function type definition to six test points: " P1=285=1=IO; P2=284=2=IO; P3=319=3=IO; P6=345=6=IO; P5=308=5=IO; P4=309=4=IO; " also the function type of test point is defined consistent with the function type of each pin of integrated circuit to be tested itself.
In other integrated circuit to be tested, if power pins is multiple, then need to define respectively each power pins separately.In this manner, the function type of each test point is defined.
S400: according to DC parameter test principle specification, treat testing integrated circuits and test, and judge the result of described integrated circuit to be tested.
According to DC parameter test principle specification, to dissimilar pin setting test result criterion.DC test is the steady-state method of test being used for determining device electrical quantity based on Ohm law.Such as, leakage current test is exactly apply voltage at input pin, this makes that the resistance between input pin and power supply or ground has electric current to pass through, then the test of its this pin electric current is measured, output driving current test on output pin, apply certain electric current exactly, then measure this pin and or power supply between voltage difference.
Treat the step that testing integrated circuits carries out testing, with reference to figure 4, comprising:
S410: the criterion setting the input and output test result corresponding to power pins of integrated circuit to be tested;
The criterion setting integrated circuit to be tested input output test result corresponding to power pins is: the input and output of integrated circuit to be tested and the magnitude of voltage of power pins are all between-1.2 volts to-0.2 volt.
S420: treat testing integrated circuits input and output and power pins adds current source.
By the editor to test procedure, input and output and the power pins for the treatment of the integrated circuit of test when controlling tester simultaneous respectively apply back biased electric current, and wherein back biased electric current is 600 microamperes, makes it form test loop.
S430: the magnitude of voltage testing integrated circuit to be tested input output and power pins.
According to added back biased electric current, the magnitude of voltage of the test loop of testing integrated circuits input and output and power pins.
S440: the performance judging integrated circuit to be tested according to criterion.
If the magnitude of voltage of a certain pin of integrated circuit to be tested is between [-1.2 ~-0.2 volt], then judge that this pin is Pass; If the magnitude of voltage of a certain pin is not between [-1.2 ~-0.2 volt], then judge that this pin is Fail.
If the magnitude of voltage of the middle input and output of integrated circuit to be tested and power pins is all between [-1.2 ~-0.2 volt], then judges that this integrated circuit is normal, represent that this integrated circuit reaches or surmounted the design specification of device; If the magnitude of voltage of one of them input and output and power pins is not in [-1.2 ~-0.2 volt] scope, then judge that this integrated circuit is abnormal, device does not reach designing requirement, can not be used for final application.
According to above-mentioned test result criterion, integrated circuit to be tested is tested, and be stored in PC test result or according to the judged result after this test result judges.Also be kept in the lump in PC to the test procedure of dissimilar integrated circuit simultaneously, in follow-up test process, if when the model of integrated circuit to be tested also stores in the memory unit, then do not need again to edit test procedure, directly can call corresponding test procedure, save time, efficiency is high.
In the present embodiment, tester provides operating voltage, trims fuse bit for integrated circuit to be tested.Tester and PC use Peripheral Component Interconnect standard (PeripheralComponentInterconnect, PCI) connecting communication is carried out, mainly treat the test that testing integrated circuits carries out relevant DC parameter, in addition, also auxiliary PC carries out the test of logic function to to-be-measured integrated circuit, as provided certain operating voltage for integrated circuit to be tested, trim related fuse byte etc.Fuse bit refers to making alive on specific pin, enough electric currents, just can blow this root fuse of the inside, and after blowing, the program in sheet just cannot be read out to have rewritten, and can only be used for running.Fuse bit is the position can reading fuse state on a specific address, and 0 expression fuses, and 1 expression does not fuse.
By said integrated circuit proving installation and method, can realize arrangement for testing integrated circuit can support the use with dissimilar tester, practical; Can test by multiple of the same type or dissimilar integrated circuit in the process of test, efficiency is high, cost is low simultaneously simultaneously; Also can change control program in real time according to the actual requirements, realize the test to dissimilar integrated circuit.Utilize said integrated circuit proving installation and method to test 15000 kinds of different integrated circuit (IC) chip, and be stored in the storage unit of PC by all test results or judged result, practicality is very high, powerful.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this instructions is recorded.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. an arrangement for testing integrated circuit, for testing integrated circuits, comprises card extender, testing base, tester and PC; It is characterized in that, described card extender is provided with the test section comprising multiple test point and the data output interface being connected described tester; Multiple described test point has respectively can by the unique identification of described tester identification;
Described testing base has the insert port for connecting described integrated circuit pin, and to connect described integrated circuit, described testing base is positioned at described test section, and insert port and described test point one_to_one corresponding;
Described tester is provided with the Data Input Interface that connect corresponding to multiple described test point, for testing the electrical parameter of the described integrated circuit connected by described testing base;
Described PC is connected with described tester, tests described integrated circuit for test procedure being sent to described tester.
2. arrangement for testing integrated circuit according to claim 1, is characterized in that, described test section is provided with 441 test points be arranged in array, and the spacing between adjacent described test point is 2.45 millimeters; Wherein, by testing, winding displacement is corresponding with the Data Input Interface of described tester to be connected 425 test points.
3. arrangement for testing integrated circuit according to claim 2, is characterized in that, described Data Input Interface is also provided with the cattle horn socket connector of 2.45 millimeters.
4. arrangement for testing integrated circuit according to claim 1, is characterized in that, described card extender is multilayer board.
5. arrangement for testing integrated circuit according to claim 1, is characterized in that, described testing base is provided with Connection Block, and described Connection Block is for being electrically connected described integrated circuit and described card extender.
6. arrangement for testing integrated circuit according to claim 1, is characterized in that, described PC is also provided with storage unit, for storing the test procedure of the model of tested integrated circuit, judged result and described tested integrated circuit.
7. an integrated circuit (IC) testing method, is characterized in that, comprises the steps:
Connect integrated circuit to be tested, testing base, card extender, tester and PC successively;
Determine that each pin of described integrated circuit to be tested corresponds to the position of the corresponding test point of described card extender;
According to the function type of each pin of described integrated circuit to be tested, function type definition is carried out to the test point on described card extender;
According to DC parameter test principle specification, treat testing integrated circuits and test, and judge the result of described integrated circuit to be tested.
8. integrated circuit (IC) testing method according to claim 7, is characterized in that, described in treat the step that testing integrated circuits carries out testing and comprise:
Set the criterion of the input and output test result corresponding to power pins of described integrated circuit to be tested;
Reverse biased current source is added to described integrated circuit input output to be tested and power pins;
Test the magnitude of voltage of described integrated circuit input output to be tested and power pins;
The performance of integrated circuit to be tested is judged according to described criterion.
9. integrated circuit (IC) testing method according to claim 8, it is characterized in that, the criterion setting described integrated circuit input output to be tested test result corresponding to power pins is: the input and output of described integrated circuit to be tested and the magnitude of voltage of power pins are all between-1.2 volts to-0.2 volt.
10. integrated circuit (IC) testing method according to claim 7, it is characterized in that, if the model of described integrated circuit to be tested is identical with the model of the integrated circuit stored in storage unit in PC, then directly call the test procedure of described tested integrated circuit.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511022400.3A CN105510803A (en) | 2015-12-30 | 2015-12-30 | Integrated circuit testing device and method |
| PCT/CN2016/076625 WO2017113516A1 (en) | 2015-12-30 | 2016-03-17 | Apparatus and method for testing integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511022400.3A CN105510803A (en) | 2015-12-30 | 2015-12-30 | Integrated circuit testing device and method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105510803A true CN105510803A (en) | 2016-04-20 |
Family
ID=55718920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511022400.3A Pending CN105510803A (en) | 2015-12-30 | 2015-12-30 | Integrated circuit testing device and method |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN105510803A (en) |
| WO (1) | WO2017113516A1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111871865A (en) * | 2020-06-30 | 2020-11-03 | 绍兴网策科技有限公司 | Integrated circuit testing device and testing method |
| WO2023168796A1 (en) * | 2022-03-08 | 2023-09-14 | 长鑫存储技术有限公司 | Data analysis method and apparatus, and storage medium |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040119487A1 (en) * | 2002-12-13 | 2004-06-24 | Yoon-Gyu Song | Test board for testing IC package and tester calibration method using the same |
| CN1766649A (en) * | 2005-10-10 | 2006-05-03 | 王云阶 | Apparatus for detecting electronic element, circuit and circuit board |
| CN1847858A (en) * | 2005-04-15 | 2006-10-18 | 华硕电脑股份有限公司 | Test riser card and its test equipment |
| CN101930016A (en) * | 2009-06-19 | 2010-12-29 | 旺矽科技股份有限公司 | Replaceable probe device and probe card applied by same |
| CN201698002U (en) * | 2010-06-29 | 2011-01-05 | 北京自动测试技术研究所 | Universal test device aiming at FPGA chips |
| CN201796120U (en) * | 2010-09-08 | 2011-04-13 | 成都理工大学 | An Integrated Chip Tester Based on ARM and CPLD |
| CN205484691U (en) * | 2015-12-30 | 2016-08-17 | 深圳市科美集成电路有限公司 | Device for testing integrated electric apparatus |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7412342B2 (en) * | 2004-10-28 | 2008-08-12 | Intel Corporation | Low cost test for IC's or electrical modules using standard reconfigurable logic devices |
| CN101865946B (en) * | 2010-06-26 | 2012-07-25 | 天水天光半导体有限责任公司 | Alternating current parameter testing system and method of programmable digital integrated circuit |
| CN102591624B (en) * | 2011-01-06 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Method for surpassing arrangement mode of probe station |
| CN102353867A (en) * | 2011-06-08 | 2012-02-15 | 伟创力电子技术(苏州)有限公司 | Interconnection test equipment and method |
| CN103105578A (en) * | 2012-12-28 | 2013-05-15 | 苏州瀚瑞微电子有限公司 | Testing system of universal chip |
-
2015
- 2015-12-30 CN CN201511022400.3A patent/CN105510803A/en active Pending
-
2016
- 2016-03-17 WO PCT/CN2016/076625 patent/WO2017113516A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040119487A1 (en) * | 2002-12-13 | 2004-06-24 | Yoon-Gyu Song | Test board for testing IC package and tester calibration method using the same |
| CN1847858A (en) * | 2005-04-15 | 2006-10-18 | 华硕电脑股份有限公司 | Test riser card and its test equipment |
| CN1766649A (en) * | 2005-10-10 | 2006-05-03 | 王云阶 | Apparatus for detecting electronic element, circuit and circuit board |
| CN101930016A (en) * | 2009-06-19 | 2010-12-29 | 旺矽科技股份有限公司 | Replaceable probe device and probe card applied by same |
| CN201698002U (en) * | 2010-06-29 | 2011-01-05 | 北京自动测试技术研究所 | Universal test device aiming at FPGA chips |
| CN201796120U (en) * | 2010-09-08 | 2011-04-13 | 成都理工大学 | An Integrated Chip Tester Based on ARM and CPLD |
| CN205484691U (en) * | 2015-12-30 | 2016-08-17 | 深圳市科美集成电路有限公司 | Device for testing integrated electric apparatus |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111871865A (en) * | 2020-06-30 | 2020-11-03 | 绍兴网策科技有限公司 | Integrated circuit testing device and testing method |
| CN111871865B (en) * | 2020-06-30 | 2021-08-13 | 绍兴网策科技有限公司 | Integrated circuit testing device and testing method |
| WO2023168796A1 (en) * | 2022-03-08 | 2023-09-14 | 长鑫存储技术有限公司 | Data analysis method and apparatus, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2017113516A1 (en) | 2017-07-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7659738B2 (en) | Test sockets having peltier elements, test equipment including the same and methods of testing semiconductor packages using the same | |
| US6822469B1 (en) | Method for testing multiple semiconductor wafers | |
| US6392427B1 (en) | Testing electronic devices | |
| US7306957B2 (en) | Fabrication method of semiconductor integrated circuit device | |
| KR20140112135A (en) | Semiconductor Device on DIB and Test System | |
| US10082535B2 (en) | Programmable test structure for characterization of integrated circuit fabrication processes | |
| CN109633417B (en) | Multi-chip simultaneous testing structure and method | |
| KR100989588B1 (en) | tester | |
| CN1332433C (en) | Test system for testing integrated chips and an adapter element for a test system | |
| CN105510803A (en) | Integrated circuit testing device and method | |
| CN112462243B (en) | Automatic programming method of open-short circuit test system | |
| CN205484691U (en) | Device for testing integrated electric apparatus | |
| CN107490755B (en) | DUT test board and method of use | |
| US8201124B1 (en) | System in package and method of creating system in package | |
| US6507205B1 (en) | Load board with matrix card for interfacing to test device | |
| KR101781895B1 (en) | System for testing multi chip package | |
| US7126836B2 (en) | Semiconductor device, system device using it, and manufacturing method of a semiconductor device | |
| US7821284B2 (en) | Semiconductor test head apparatus using field programmable gate array | |
| TW497243B (en) | Integrated circuit with a test driver and test facility for testing an integrated circuit | |
| CN107271888A (en) | A kind of method that single test chip realizes multiple IP chip testings | |
| US7138792B2 (en) | Programmable power personality card | |
| CN220040663U (en) | Testing device and testing machine box | |
| KR20040054904A (en) | Socket and managing system for test results of semiconductor device using the socket | |
| KR100821095B1 (en) | Semiconductor test apparatus and test method | |
| CN220730355U (en) | Chip test board and test system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20190326 |
|
| AD01 | Patent right deemed abandoned |