CN105489476A - Patterning method and semiconductor structure - Google Patents

Abstract

The present invention discloses a patterning method, which includes: providing a substrate having a material layer; forming a patterned hard mask layer on the material layer, wherein the hard mask layer has a plurality of first holes; then, forming a mask layer, wherein the mask layer includes a plurality of line pattern masks, the line pattern masks extend along a direction, and separate each first hole into a second hole and a third hole; using the patterned hard mask layer and the mask layer as masks, patterning the material layer to form a patterned material layer having a plurality of fourth holes and a fifth hole. The present invention also provides a semiconductor structure.

Description

Patterning Methods and Semiconductor Structures

technical field

The present invention relates to an integrated circuit, and more particularly to a patterning method and semiconductor structure.

Background technique

In the known photolithography technology such as ArF immersion lithography (immersionlithography), a single process can only produce a pitch of about 76nm. To make a smaller pitch, a secondary photolithography and secondary etching process is required. However, the pattern made in this way may be misaligned, and due to the difficulty in process, it is also difficult to control the critical dimension uniformity. Therefore, there is an urgent need in the industry for a method that can be implemented using the existing photolithography process, but can also obtain a smaller pattern pitch.

Contents of the invention

The invention provides a patterning method, which can obtain smaller pattern spacing and critical dimensions, and align the produced patterns with each other, improve the problem of misalignment, and improve the uniformity of critical dimensions.

The present invention proposes a patterning method as follows. A material layer, a first hard mask layer, a second hard mask layer and a first mask layer are sequentially formed on the substrate. Using the first mask layer as an etching mask, etching the second hard mask layer to form a patterned second hard mask layer having a plurality of first holes along the The critical dimension (CD) in the first direction is greater than the critical dimension along the second direction. Next, the first mask layer is removed to form a second mask layer, which includes a plurality of line pattern masks extending along the second direction, and separates each first hole into a second hole and a third hole. Using the patterned second hard mask layer and the second mask layer as an etching mask, etching the exposed first hard mask layer and material layer in the second hole and the third hole to form a patterned first A hard mask layer and patterned material layer. Then, the patterned first hard mask layer, the patterned second hard mask layer, and the second mask layer are removed to expose the patterned material layer, which has a plurality of fourth holes and a plurality of fifth holes. hole.

In an embodiment of the present invention, in the patterning method, the first holes form a first hole array, and the patterned second hard mask layer is a mesh hard mask layer.

In an embodiment of the present invention, the patterning method further includes filling each line pattern mask into a plurality of first holes in the second direction, and covering part of the patterned second hard mask layer .

In an embodiment of the present invention, the patterning method further includes filling each line pattern mask into a single first hole along the second direction.

In an embodiment of the present invention, the patterning method further includes adjusting the critical dimension of the line pattern mask in the first direction, so as to adjust the formed fourth hole and the fifth hole along the first direction. critical size.

In an embodiment of the present invention, the second mask layer may include a patterned organic bottom layer on the first hard mask layer, and a patterned silicon-containing hard mask bottom antireflective layer on the patterned on the organic bottom layer.

The present invention further provides a patterning method as follows. A substrate having a material layer is provided. A patterned hard mask layer having a plurality of first holes is formed on the material layer. Next, a mask layer is formed, which includes a plurality of line pattern masks extending along the second direction and separating each first hole into a second hole and a third hole. Then, using the patterned hard mask layer and the mask layer as a mask, the material layer is patterned to form a patterned material layer having a plurality of fourth holes and a plurality of fifth holes.

In an embodiment of the present invention, the patterning method further includes filling each line pattern mask into a plurality of first holes in the second direction and covering part of the patterned hard mask layer.

In an embodiment of the present invention, the patterning method further includes filling each line pattern mask into a single first hole along the second direction.

The invention also proposes a semiconductor structure, including a patterned material layer, configured on a substrate. The patterned material layer has a hole array, which includes a plurality of hole rows extending along the first direction and parallel to each other, and each hole row includes a plurality of holes arranged in a row along the first direction, and the holes in the hole row Sides along the first direction of each hole are aligned with each other, and sides along the second direction are also aligned with each other.

In the patterning method of the present invention, the line pattern mask is superimposed on the patterned second hard mask layer as an etching mask, so that smaller pattern pitches and critical dimensions can be obtained, and the patterns made are aligned with each other , improve the misalignment problem, and improve the uniformity of key dimensions.

In the patterning method of the present invention, by adjusting the critical dimensions of the overlapped line pattern masks, the pitch and critical dimension of the pattern can be adjusted.

In the semiconductor structure of the present invention, in the patterned material layer, the sides of each hole in the first direction and the second direction are aligned with each other, and have a high critical dimension uniformity.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

1A to 1E are top views illustrating the flow of a patterning method according to an embodiment of the present invention.

FIGS. 2A to 2E are schematic cross-sectional views illustrating a cut line AA′ in FIGS. 1A to 1E .

3A to FIG. 3E are schematic cross-sectional views showing the cut line B-B' in FIG. 1A to FIG. 1E .

FIG. 4 is a top view illustrating the flow of a patterning method according to another embodiment of the present invention.

5A to 5B are cross-sectional schematic diagrams illustrating the flow of a patterning method according to yet another embodiment of the present invention.

FIG. 6A is a top view of a semiconductor structure according to an embodiment of the present invention.

FIG. 6B is a schematic cross-sectional view illustrating the semiconductor structure of FIG. 6A .

FIG. 7 is a top view of a semiconductor structure according to another embodiment of the present invention.

【Symbol Description】

10. 802: Base

12: material layer

12a, 804, 904: patterned material layer

14: First hard mask layer

14a: Patterned first hard mask layer

16: Second hard mask layer

16a: Patterned second hard mask layer

18: First mask layer

19. O: hole

20: Second mask layer

22: Organic bottom material layer

22a: Patterned organic bottom layer

24: hard mask bottom anti-reflective material layer

24a: Patterned silicon-containing hard mask bottom anti-reflective layer

26: Patterned photoresist layer

800: Semiconductor Structures

810, 910: hole row

D1: first direction

D2: Second direction

P1, P3, P5: spacing along the first direction

P2, P4, P6: spacing along the second direction

O1: the first hole

O2: Second Hole

O3: The Third Hole

O4: Hole Four

O5: The Fifth Hole

O6: Hole Six

O7: The Seventh Hole

detailed description

FIG. 1A to FIG. 1E are top views illustrating the flow of a patterning method according to an embodiment of the present invention. FIGS. 2A to 2E are schematic cross-sectional views illustrating a cut line AA′ in FIGS. 1A to 1E . 3A to FIG. 3E are schematic cross-sectional views showing the cut line B-B' in FIG. 1A to FIG. 1E .

Referring to FIGS. 1A to 3A , a substrate 10 is provided, and a material layer 12 is formed on the substrate 10 . The substrate 10 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor-over-insulator (SOI) substrate. Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed of atoms of group IIIA and group VA, such as gallium arsenide. The material layer 12 is, for example, a conductor layer, and its material is, for example, metal, polysilicon, polycide, or metal silicide, but not limited thereto. For example, a dielectric layer, other semiconductor material layers or semiconductor elements may also be disposed between the substrate 10 and the material layer 12 , but not limited thereto. Next, a first hard mask layer 14 , a second hard mask layer 16 and a first mask layer 18 are sequentially formed on the material layer 12 . The materials of the first hard mask layer 14 and the second hard mask layer 16 are different. Materials of the first hard mask layer 14 and the second hard mask layer 16 can be, for example, silicon oxide, silicon oxynitride, silicon nitride or polysilicon, respectively. The first mask layer 18 is, for example, a patterned photoresist layer. The patterned photoresist layer can be formed by, for example, firstly forming a photoresist material layer, then performing an exposure process, and then developing. The mask used in the exposure process is, for example, a half-tone phase shift mask (HalfTonePhaseShiftMask, HTPSM), a binary mask (binarymask, BIM) or an opaque MoSiOnGlass mask on glass (OpaqueMoSiOnGlassMask, OMOG); For example Kr, ArF, i-ArF or EUV. The first mask layer 18 has a plurality of holes 19 , and the holes 19 expose part of the second hard mask layer 16 . The first mask layer 18 is, for example, a mesh mask layer; the holes 19 form a hole array. The CD (CD) of each hole 19 along the first direction D1 is larger than the CD along the second direction D2. In one embodiment, the CD along the first direction D1 of each hole 19 in the first mask layer 18 is, for example, about 64 nm, and the CD along the second direction D2 is, for example, about 43 nm. limit. The second direction D2 is different from the first direction D1. The second direction D2 and the first direction D1 may be, for example, perpendicular to each other. The first direction D1 may be the X direction or the Y direction; the second direction D2 may be the Y direction or the X direction. In the drawings of this embodiment, the first direction D1 is, for example, the Y direction; the second direction D2 is, for example, the X direction.

Referring to FIGS. 1A to 3A and FIGS. 1B to 3B, the second hard mask layer 16 is etched using the first mask layer 18 as an etching mask to form a patterned second hard mask layer 16a. . The etching process may be an anisotropic etching process, such as a dry etching process. The dry etching process is, for example, a plasma etching process. There are a plurality of first holes O1 in the patterned second hard mask layer 16a. In one embodiment, the first holes O1 form a first hole array, and the patterned second hard mask layer 16a is a mesh hard mask layer. The first hole O1 exposes part of the first hard mask layer 14 , and the CD of the first hole O1 along the first direction D1 is larger than the CD along the second direction D2 . In one embodiment, the pitch P1 along the first direction D1 and the pitch P2 along the second direction D2 are both about 86 nm, for example, the CD of the first hole O1 along the first direction D1 is about 64 nm, for example, The CD along the second direction D2 is, for example, about 43 nm, but not limited thereto. Next, the first mask layer 18 is removed.

Referring to FIG. 1B to FIG. 3B , FIG. 1C to FIG. 3C and FIG. 4 , next, a second mask layer 20 is formed. The material of the second mask layer 20 and the second hard mask layer 16 a is different from that of the first hard mask layer 14 or/and the material layer 12 . The second mask layer 20 is, for example, a patterned photoresist layer, but not limited thereto. The patterned photoresist layer can be formed by, for example, firstly forming a photoresist material layer, then performing an exposure process, and then developing. The mask used in the exposure process is, for example, a halftone phase-shift mask, a binary mask, or an opaque molybdenum silicon mask on glass; the light source is, for example, Kr, ArF, i-ArF or EUV. The mask and light source used to form the second mask layer 20 may be the same as or different from those used to form the first mask layer 18 . The second mask layer 20 includes a plurality of line pattern masks. The line pattern mask extends along the second direction D2 and separates each first hole O1 into a second hole O2 and a third hole O3 . In one embodiment, each first hole O1 is divided into two small holes of equal size. In other words, CDs along the first direction D1 of the separated second hole O2 and third hole O3 are equal, but not limited thereto. In another embodiment, the second holes O2 and the third holes O3 form a second hole array, and the patterned second hard mask layer 16 a and the second mask layer 20 form a mesh etching mask.

In one embodiment, as shown in FIG. 1B and FIG. 1C, each line pattern mask used as the second mask layer 20 is filled in a plurality of first holes O1 in the second direction D2, and extends continuously to cover Partially patterned second hard mask layer 16a. In another embodiment, as shown in FIG. 4, each line pattern mask used as the second mask layer 20 is filled in a single first hole O1 in the second direction D2, and each line pattern mask is along the The length along the second direction D2 is equal to the CD of the corresponding first hole O1 along the second direction D2.

Next, please continue to refer to FIG. 1C to FIG. 3C and FIG. 1D to FIG. 3D , using the patterned second hard mask layer 16a and the second mask layer 20 as an etching mask to etch the second hole O2 and The third hole O3 exposes the first hard mask layer 14 and the material layer 12 to form a patterned first hard mask layer 14 a and a patterned material layer 12 a, as shown in FIG. 2D and FIG. 3D . The etching process may be an anisotropic etching process, such as a dry etching process. The dry etching process is, for example, a plasma etching process. The materials of the second mask layer 20 and the second hard mask layer 16 a are different from those of the first hard mask layer 14 and/or the material layer 12 .

Then, referring to FIG. 1E to FIG. 3E , the patterned first hard mask layer 14a, the patterned second hard mask layer 16a and the second mask layer 20 are removed to expose the patterned material layer 12a. The patterned material layer 12a has a plurality of fourth holes O4 and a plurality of fifth holes O5. In one embodiment, the fourth hole O4 and the fifth hole O5 form a third hole array, and the patterned material layer 12a is a mesh material layer. In another embodiment, CDs of the fourth hole O4 and the fifth hole O5 along the first direction D1 are equal, that is, the sizes of the fourth hole O4 and the fifth hole O5 are equal, but not limited thereto.

Please refer to FIG. 1C, FIG. 4 and FIG. 1E, the CD of the line pattern mask used as the second mask layer 20 in the first direction D1 can be adjusted to adjust the separated second hole O2 and third hole O3 The CD of the fourth hole O4 and the fifth hole O5 formed in the patterned material layer 12 a along the first direction D1 is further adjusted. In other words, if the CD of the line pattern mask used as the second mask layer 20 in the first direction D1 is larger, the CD of the separated second hole O2 and third hole O3 along the first direction D1 is larger. The CD of the fourth hole O4 and the fifth hole O5 formed in the patterned material layer 12a along the first direction D1 is also smaller. Conversely, if the CD of the line pattern mask used as the second mask layer 20 in the first direction D1 is smaller, the CD of the separated second hole O2 and third hole O3 along the first direction D1 is smaller. The CD of the fourth hole O4 and the fifth hole O5 formed in the patterned material layer 12a along the first direction D1 is also larger.

On the other hand, please refer to FIG. 1C, FIG. 4 and FIG. 1E, when filling multiple or single first holes O1 in the second direction D2 with the line pattern mask as the second mask layer 20, according to In an embodiment of the present invention, the line pattern mask can be aligned with the center line of the first hole O1 in the first direction D1 and filled. In this way, the first hole O1 can be divided into two holes of equal size, that is, the CDs of the separated second hole O2 and third hole O3 along the first direction D1 are equal. Then, patterning the material layer 12 can make the CDs of the fourth hole O4 and the fifth hole O5 in the patterned material layer 12a equal along the first direction D1, that is, the CD of the fourth hole O4 and the fifth hole O5 equal in size.

In addition, please continue to refer to FIG. 1B, FIG. 1C, FIG. 4 and FIG. 1E. According to an embodiment of the present invention, the CD of the first hole O1 along the first direction D1 is, for example, about 64 nm, and the CD along the second direction D2 The CD of is about 43 nm, for example; the pitch P1 along the first direction D1 and the pitch P2 along the second direction D2 are both about 86 nm, for example. Adjust the CD of the line pattern mask used as the second mask layer 20 in the first direction D1, so that the CD of the hole O2 or O3 along the first direction D1 is the distance from the holes O2 and O3 along the first direction D1 quite. In one embodiment, the CD of the line pattern mask used as the second mask layer 20 in the first direction D1 is, for example, about 21 nm. Next, when using the line pattern mask to fill in multiple or single first holes O1 in the second direction D2, align the line pattern mask with the centerline of the first hole O1 in the first direction D1 and fill in. In this way, the first hole O1 can be divided into two holes of equal size, that is, the CDs of the separated second hole O2 and third hole O3 along the first direction D1 are equal. Then, patterning the material layer 12 can make the CDs of the fourth hole O4 and the fifth hole O5 in the patterned material layer 12a equal along the first direction D1, that is, the CD of the fourth hole O4 and the fifth hole O5 equal in size. The CDs of the fourth hole O4 and the fifth hole O5 along the first direction D1 are, for example, about 21 nm, and the CDs along the second direction D2 are, for example, about 43 nm. What is more noteworthy is that the fourth hole O4 and the fifth hole O5 of equal size are formed at this time, wherein the pitch P3 along the first direction D1 is equal to each other, and the pitch P4 along the second direction D2 is also equal to each other. The distance P3 between the fourth hole O4 and the fifth hole O5 of equal size along the first direction D1 is, for example, about 43 nm, and the distance P4 along the second direction D2 is, for example, about 86 nm. More specifically, the patterned material layer 12a formed at this time is a network material layer having a plurality of holes O4 and O5 of equal size, and the pitch P3 of each hole O4 and O5 along the first direction D1 is equal to each other. , the pitches P4 along the second direction D2 are also equal to each other.

5A to 5B are cross-sectional schematic diagrams illustrating the flow of a patterning method according to yet another embodiment of the present invention. The processes in FIGS. 5A-5B are similar to the aforementioned processes, so the same components are denoted by the same reference numerals, and only the differences will be described in detail here.

5A to 5B, according to another embodiment of the present invention, wherein the second mask layer 20 may include a patterned organic bottom layer (organic underlayer, ODL) 22a located on the first hard mask layer 14, And a patterned silicon-containing hard-mask bottom anti-reflection coating (SHB) 24a on the patterned organic bottom layer 22a. The patterned organic bottom layer 22a is, for example, a self-assembled organic molecular monolayer or a spin-coated organic layer. The material of the patterned silicon-containing hard mask bottom anti-reflective layer 24 a can be, for example, organosilicon polymer or polysilane for a bottom anti-reflective coating (silicon-containing bottom-manti-reflective coating, BARC). The method of forming the second mask layer 20 is as follows. Referring to FIG. 5A , an organic bottom material layer 22 , a hard mask bottom anti-reflective material layer 24 and a patterned photoresist layer 26 are sequentially formed on the first hard mask layer 14 . Using the patterned photoresist layer 26 as a mask, etch the organic bottom material layer 22 and the hard mask bottom anti-reflective material layer 24 to form a patterned organic bottom layer 22a and a patterned silicon-containing hard mask bottom The anti-reflection layer 24a is shown in FIG. 5B. The etching process may be an anisotropic etching process, such as a dry etching process. The dry etching process is, for example, a plasma etching process. Next, the patterned photoresist layer 26 is removed. In this way, the structure of the second mask layer 20 shown in FIG. 5B is formed.

FIG. 6A is a top view of a semiconductor structure according to an embodiment of the present invention. FIG. 6B is a schematic cross-sectional view illustrating the semiconductor structure of FIG. 6A . FIG. 7 is a top view of a semiconductor structure according to another embodiment of the present invention.

Referring to FIGS. 6A-6B , the semiconductor structure 800 includes a substrate 802 and a patterned material layer 804 , wherein the patterned material layer 804 is disposed on the substrate 802 . The substrate 802 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate on an insulating layer. Semiconductors are, for example, atoms of group IVA, such as silicon or germanium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of group IVA, such as silicon carbide or germanium silicide, or a semiconductor compound formed of atoms of group IIIA and group VA, such as gallium arsenide. The patterned material layer 804 is, for example, a conductor layer, and its material is, for example, metal, polysilicon, metal polycide or metal silicide, but not limited thereto. For example, a dielectric layer, other semiconductor material layers or semiconductor elements may be disposed between the substrate 802 and the material layer 804 , but not limited thereto. Although the drawings of the present invention do not show the situation that a dielectric layer or other semiconductor material layers are disposed between the substrate 802 and the material layer 804, FIGS. 6A to 6B are only for illustration purposes and are not intended to limit the present invention.

Please continue to refer to FIG. 6A to FIG. 6B , the patterned material layer 804 has a hole array, the hole array includes a plurality of hole rows 810 extending along the first direction D1 and parallel to each other, each hole row 810 includes a plurality of holes along the The holes O are arranged in a row along the first direction D1, wherein the sides of each hole O in each hole row 810 are aligned with each other along the first direction D1, and the sides along the second direction D2 are also aligned with each other. The second direction D2 is different from the first direction D1. The second direction D2 and the first direction D1 may be, for example, perpendicular to each other. The first direction D1 may be the X direction or the Y direction; the second direction D2 may be the Y direction or the X direction. In the drawings of this embodiment, the first direction D1 is, for example, the Y direction; the second direction D2 is, for example, the X direction.

Please continue to refer to FIGS. 6A to 6B. According to an embodiment of the present invention, the size of each hole O in the patterned material layer 804 is the same, that is, the CDs of each hole O along the first direction D1 are equal to each other, and along the The CDs of the second direction D2 are also equal to each other. On the other hand, according to yet another embodiment of the present invention, not only the size of each hole O in the patterned material layer 804 is the same, but also the pitch P5 along the first direction D1 is equal to each other, and the pitch P6 along the second direction D2 is also equal. equal to each other. At this time, the CD of the hole O along the first direction D1 is about 21 nm, for example, and the CD along the second direction D2 is about 43 nm; the pitch P5 along the first direction D1 is about 43 nm, for example, along the second direction The pitch P6 of D2 is, for example, about 86 nm.

Please refer to FIG. 7, according to the method of the above-mentioned embodiment of the present invention, when the line pattern mask used as the second mask layer 20 in FIG. 1C or FIG. The centerline in the first direction D1 separates the two holes with different sizes, so that the sixth hole O6 and the seventh hole O7 formed in the material layer 904 have different sizes. More specifically, the hole array in the patterned material layer 904 includes a plurality of hole rows 910 extending along the first direction D1 and parallel to each other, and each hole row 910 includes a plurality of holes arranged along the first direction D1. The sixth hole O6 and the seventh hole O7 of a row. The sizes of the sixth hole O6 and the seventh hole O7 are different. In other words, CDs of the sixth hole O6 and the seventh hole O7 along the first direction D1 are not equal to each other, but CDs along the second direction D2 are equal to each other. However, sides along the first direction D1 of each pair of sixth holes O6 and seventh holes O7 are still aligned with each other, and sides along the second direction D2 are also aligned with each other. Moreover, each sixth hole O6 and each seventh hole O7 in each hole row 910 are aligned with each other along sides along the first direction D1 , and are also aligned with each other along sides along the second direction D2 .

To sum up, in the patterning method provided by the present invention, a plurality of line pattern masks are superimposed on a network hard mask layer with a plurality of holes as a mask for photolithography. Each hole of the mesh hard mask layer is divided into two smaller holes, therefore, the pattern pitch and critical dimension can be formed smaller than the known method, and the patterns made are aligned with each other, so that the misalignment can be improved problems and improve critical dimension uniformity. In addition, by adjusting the width of the overlapped line pattern mask, the pattern pitch and CD size can be adjusted. In addition, in the semiconductor structure provided by the present invention, in the patterned material layer, the sides of each hole in the first direction and the second direction are aligned with each other, and have higher critical dimension uniformity.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (10)

1. A patterning method comprising: sequentially forming a material layer, a first hard mask layer, a second hard mask layer and a first mask layer on a substrate; Using the first mask layer as an etching mask, etching the second hard mask layer to form a patterned second hard mask layer, the patterned second hard mask layer has multiple a first hole having a critical dimension (CD) along a first direction greater than a CD along a second direction; removing the first mask layer; A second mask layer is formed, the second mask layer includes a plurality of line pattern masks extending along the second direction and separating each first hole into a second hole and a first hole. three holes; using the patterned second hard mask layer and the second mask layer as an etching mask, etching the first hard mask layer and the material layer exposed by the second holes and the third holes, to form a patterned first hard mask layer and a patterned material layer; and removing the patterned first hard mask layer, the patterned second hard mask layer and the second mask layer, exposing the patterned material layer, the patterned material layer has a plurality of first Four holes and multiple fifth holes. 2. The patterning method according to claim 1, wherein the first holes form a first hole array, and the patterned second hard mask layer is a mesh hard mask layer. 3. The patterning method according to claim 1, wherein each line pattern mask fills a plurality of first holes in the second direction and covers part of the patterned second hard mask layer. 4. The patterning method according to claim 1, wherein each line pattern mask fills in a single first hole in the second direction. 5. The patterning method according to claim 1, further comprising adjusting the CD of the line pattern masks in the first direction to adjust the formed fourth holes and the fifth holes along the first direction. Directions to the CD. 6. The method of patterning according to claim 1, wherein the second mask layer comprises: a patterned organic bottom layer on the first hard mask layer; and A patterned silicon-containing hard mask bottom anti-reflection layer is located on the patterned organic bottom layer. 7. A method of patterning, comprising: providing a substrate having a material layer; A patterned hard mask layer is formed on the material layer, the patterned hard mask layer has a plurality of first holes, and the CD along a first direction of these first holes is larger than that along a second direction. Direction CD; forming a mask layer including a plurality of line pattern masks extending along the second direction and separating each first hole into a second hole and a third hole; and Using the patterned hard mask layer and the mask layer as a mask, the material layer is patterned to form a patterned material layer having a plurality of fourth holes and a plurality of fifth holes. 8. The patterning method according to claim 7, wherein each line pattern mask fills a plurality of first holes in the second direction and covers part of the patterned hard mask layer. 9. The patterning method of claim 7, wherein each line pattern mask fills in a single first hole in the second direction. 10. A semiconductor structure comprising: A patterned material layer is disposed on a substrate, the patterned material layer has a hole array, the hole array includes a plurality of hole rows extending along a first direction and parallel to each other, each hole row comprising a plurality of holes aligned along the first direction, wherein Each hole in the rows of holes is aligned with each other along sides along the first direction, and sides along a second direction are also aligned with each other.