CN105486999A - Boundary scanning digital circuit test system based on PXI bus and test method thereof - Google Patents
Boundary scanning digital circuit test system based on PXI bus and test method thereof Download PDFInfo
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- CN105486999A CN105486999A CN201510863074.2A CN201510863074A CN105486999A CN 105486999 A CN105486999 A CN 105486999A CN 201510863074 A CN201510863074 A CN 201510863074A CN 105486999 A CN105486999 A CN 105486999A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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Abstract
The invention discloses a boundary scanning digital circuit testing system based on a PXI bus and a testing method thereof. The test system comprises a PXI backboard, a main controller, a JTAG controller, 1-N interface expansion modules, 1-M function expansion modules and an adapter board. The PXI backboard is connected with the main controller, the JTAG controller, the interface expansion module and the function expansion module, and the adapter board is connected with the main controller, the JTAG controller, the interface expansion module and the function expansion module; the main controller is connected with the keyboard and the mouse of the computer through a USB interface and is also connected with the display of the computer through a DVI. The invention has advanced architecture and strong expandability, solves the problems that the prior testing equipment has strong pertinence, the boundary scan test is incompatible with the functional test, and the system test can not be realized, and can be used as a general development platform. The invention also discloses a test method of the boundary scanning digital circuit test system based on the PXI bus.
Description
Technical field
The present invention relates to a kind of test macro and method of testing thereof, relate to a kind of boundary scan digital circuit test system based on PXI bus and method of testing thereof especially.
Background technology
Along with the develop rapidly of electronic technology, the ratio of digital circuit shared by communication, the every field such as military, industrial, medical is also increasing.And along with the development of digital circuit, chip encapsulation technology is constantly towards Highgrade integration, high performance, multioutlet and fine-pitch future development.The application of technology in Circuits System such as surface mount device (SMD), multi-chip module (MCM), multilayer board (MPCB) makes device packing density improve constantly.What all these changes brought is the raising of level of integrated system, the reduction of physical size, simultaneously can be also more and more less for the internodal of test, and what have becomes recessive unreachable node even completely.The traditional method of testing such as needle-bar, probe has been difficult to effectively test circuit board.The appearance of boundary scan technique solves this difficult problem, the JTAG chain that " virtual probe " technology of its uniqueness can be formed by the jtag interface of multiple boundary scanning device, use TAP signal control and detect pin that is all and JTAG chain associated components, thus reach the object of test.
The time that boundary scan technique is used for testing apparatus is not long, the boundary scan testing platform before market occurred, interface is single, cannot be compatible with functional test, does not possess high-speed interface test function, and System test function, does not more possess test optical fiber function.
Summary of the invention
The object of the present invention is to provide a kind of boundary scan digital circuit test system based on PXI bus and test macro thereof, in order to solve above-mentioned existing digital circuit test intersystem problem, PXI technology is expand towards the PCI of instrument system, be convenient to the integrated of various test instrumentation, extendability is strong, the test only needing the interface changing or increase corresponding function can realize its function when different test interfaces.In conjunction with the advantage of PXI bus and boundary scan technique, all difficult problems in above testing apparatus can be solved.
The present invention is achieved through the following technical solutions: a kind of boundary scan digital circuit test system based on PXI bus, and its computer is for testing each performance of measured piece or system under test (SUT); Described test macro have employed PXI bus architecture, and comprises PXI backboard, master controller, jtag controller, 1 ~ N interfacing expansion module, 1 ~ M function expanding module, adaptation board; Wherein, N, M are positive integer; PXI backboard is all connected with master controller, jtag controller, interfacing expansion module, function expanding module, and adaptation board is all connected with master controller, jtag controller, interfacing expansion module, function expanding module; Master controller is connected by the keyboard of USB interface and described computing machine, mouse, is also connected with the display of described computing machine by DVI.
As the further improvement of such scheme, PXI backboard is as the backboard of the test cabinet of the described test macro of collecting, and jtag controller is connected with JTAG and PXI backboard by PXI bus, and interfacing expansion module is connected with JTAG and PXI backboard by PXI bus equally.
As the further improvement of such scheme, jtag controller controls by JTAG each interfacing expansion module being positioned at test machine case on the one hand, on the other hand JTAG is drawn described test cabinet to measured piece or system under test (SUT) by adaptation board, described test cabinet is for accommodating described test macro.
Further, jtag controller comprises PXI connector P1, PXI connector P2, PCI bridge, FPGA, JTAG bridge; Due to the expansion that two PXI connectors are PCI bridges, the interface of two PXI connectors is while reservation PCI function, turn increase Trigger Bus, Trigger Bus on PXI connector P2 is connected with FPGA, and the pci bus on PXI connector P1 is connected with PCI bridge, after pci bus is converted to local bus by PCI bridge, deliver in FPGA, FPGA, by Instruction decoding, generates corresponding jtag test vector, delivers to JTAG bridge by jtag interface; JTAG bridge have JTAG expanded function with by 1 road JTAG signal extension to multichannel, controlled the jtag interface in other modules in test cabinet by PXI connector P1, and all jtag interfaces in measured piece and system under test (SUT) simultaneously.
As the further improvement of such scheme, interfacing expansion module is expanded according to the pin number of measured piece, for the loopback test of boundary scan; Interfacing expansion module is connected with JTAG and PXI backboard by PXI bus on the one hand, is connected on the other hand by adaptation board with measured piece or system under test (SUT).
As the further improvement of such scheme, the function that function expanding module is tested needed for system under test (SUT) is expanded, for functional test; Function expanding module is connected with JTAG and PXI backboard by PXI bus on the one hand, is connected on the other hand by adaptation board with measured piece or system under test (SUT).
Further, function expanding module comprises PXI connector P1, PXI connector P2, PCI bridge, JTAG bridge, FPGA and external interface; Trigger Bus on PXI connector P2 is connected with FPGA, pci bus on PXI connector P1 is connected with PCI bridge, JTAG and JTAG bridge on PXI connector P1 is connected, the jtag interface of the FPGA on PXI backboard is also connected with JTAG bridge, and the idle pin on PXI connector P2 is as the expansion of JTAG cascade.
As the further improvement of such scheme, adaptation board is as the external interface of the test cabinet of the described test macro of collecting, and adaptation board is connected with measured piece or system under test (SUT).
As the further improvement of such scheme, described test macro also comprises power module (7), and power module (7) is as the supply module of the test cabinet of the described test macro of collecting; Extraneous 220V is exchanged input by power module (7), is converted to required power supply in described test cabinet, and powers to measured piece and system under test (SUT).
The present invention also provides a kind of above-mentioned arbitrarily based on the method for testing of the boundary scan digital circuit test system of PXI bus, master controller sends test instruction to jtag controller, after jtag controller controls to produce test vector, the FPGA in each boundary scanning device in system under test (SUT) and the interfacing expansion module in test macro is controlled by jtag controller, realize in system under test (SUT) peripheral interface and system under test (SUT), the interconnection situation of signal between measured piece, final testing result shows under the control of master controller in described display, and forms test report.
Beneficial effect of the present invention is as follows:
Test macro in the present invention have employed the bus architecture of PXI, and all functional modules and interface module all can be expanded according to the actual requirements, and this system architecture is advanced rationally, extendability is strong.And have employed modular design concept, whole system can flexible configuration according to the actual requirements, and not only hardware expanding is convenient, and software extensions is also very convenient.
Accompanying drawing explanation
Fig. 1 is the boundary scan digital circuit test system architecture diagram based on PXI bus of the embodiment of the present invention;
Fig. 2 is the jtag controller fundamental diagram of the embodiment of the present invention;
Fig. 3 is the interfacing expansion module structural representation of the embodiment of the present invention;
Fig. 4 is the PXI back board structure schematic diagram of the embodiment of the present invention;
Fig. 5 is the system level testing fundamental diagram of the embodiment of the present invention.
Embodiment
Below in conjunction with embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, do not limit the present invention.
Boundary scan digital circuit test system based on PXI bus of the present invention, for the test of digital circuitry, mainly comprises: test cabinet and keyboard, mouse, display.Described test machine case comprises PXI backboard, master controller, jtag controller, interfacing expansion module, function expanding module, adaptation board, power module etc.This test macro have employed PXI bus architecture, and extendability is strong, has the test function of high-speed channel and optical-fibre channel.While providing boundary scan testing function, also compatible functional test, not only can carry out single-board testing but also the test of feasible system level, and greatly improve the tempo of development of testing engineering, improve the efficiency of product test and maintenance.
As shown in Figure 1, test macro of the present invention comprises test cabinet and keyboard/mouse, display composition, is applicable to the test of various digital circuit board and digital display circuit.
Described test machine case comprises: master controller, jtag controller, interfacing expansion module, function expanding module, PXI backboard, adaptation board, power module etc.
Particularly, master controller is the computer module of PXI interface, and as the control core of whole test macro, by external connection keyboard/display device with mouse, running the testing software residing at inside can test.
Described jtag controller, there is PXI interface, for the generation of boundary scan testing vector, by pci bus, receive the test instruction that master controller transmits, and test instruction is generated the jtag interface that jtag test vector is sent to measured piece and interfacing expansion module, simultaneously, receive test result by jtag interface, and be converted to pci bus, return to master controller.
As shown in Figure 2, jtag controller is by P1, P2 two PXI connectors, and PCI bridge, FPGA, JTAG bridge forms.Due to the expansion that PXI is PCI, so its interface is while reservation PCI function, turn increase Trigger Bus.So in jtag controller, Trigger Bus on P2 connector is connected with FPGA, pci bus on P1 connector is connected with PCI bridge, after pci bus is converted to local bus by PCI bridge, deliver in FPGA, FPGA is by Instruction decoding, generate corresponding jtag test vector, JTAG bridge is delivered to by jtag interface, JTAG bridge has JTAG expanded function, can by 1 road JTAG signal extension to multichannel, simultaneously can jtag interface in other modules in control PXI cabinet by P1 connector, and all jtag interfaces in measured piece and system under test (SUT).
Described interfacing expansion module, has PXI interface, is mainly used in the loopback test of signal in boundary scan testing, and has the function of the functional test that can customize.In system, the quantity of interfacing expansion module carries out selection collocation according to interface quantity in measured piece and system under test (SUT).
As shown in Figure 3, interfacing expansion module is primarily of P1, P2 two PXI connectors, and PCI bridge, JTAG bridge, FPGA and external interface form.In interfacing expansion module, Trigger Bus on P2 connector is connected with FPGA, pci bus on P1 connector is connected with PCI bridge, JTAG and JTAG bridge on P1 connector is connected, the jtag interface of the FPGA on plate is also connected with JTAG bridge, idle pin on P2 connector is as the expansion of JTAG cascade, and such master controller can manage polylith interfacing expansion module by JTAG simultaneously.And external interface is as the interface with measured piece, comprising common low-speed interface, high-speed interface, after adaptation board installs optical module, can make system not only support high-speed channel but also support the test function of optical-fibre channel.In boundary scan testing, jtag controller carries out transmission and the reception of data by the boundary scan cell in the FPGA in JTAG control interface expansion module, the low-speed interface of measured piece and system under test (SUT) can be tested under IEEE1149.1 standard, and under IEEE1149.6 standard, the high-speed interface that module is reserved can be tested the high-speed interface in measured piece and system under test (SUT), and in these test processs, pci bus can be in idle condition.And in functional test procedures, primary controller by the register of PXI bus marco FPGA inside, can carry out corresponding functional test, such as send data, receive data, send the operations such as Control timing sequence, and by JTAG real-time update functional test program, realize multifunctional testing.
Described PXI backboard, compatible PXI bus, comprises one or two power supply slot, a master controller slot, a jtag controller slot, N number of interfacing expansion module slot, M function expanding module slot.
As shown in Figure 4, power supply provides the main supply voltage of direct current+5V ,+3.3V to test macro, and the accessory power supply of +/-12V, and each board in each system accessed by master controller by pci bus.
Described adaptation board, is mainly used in the connection of test macro and measured piece and system under test (SUT), comprises the adaptation etc. of level, all can realize on adaptation board.Can use card insert type, cable type etc. with the type of attachment of measured piece, according to different measured piece type unrestricted choice, as card format can adopt card insert type, the measured piece of extension set form can adopt cable type to connect.
Described function expanding module, can compatible PXI instrument conventional in the market, and such as oscillograph, multimeter, logic analyser etc., can provide strong support to the test of systemic-function.
As further technical scheme of the present invention, this test macro additionally provides System test function.As shown in Figure 5, owing to including the interfacing expansion module that can customize logic in system, can boundary scan testing be realized, can test by practical function again, greatly improve testing efficiency.When boundary scan testing, the input/output signal of system under test (SUT) is connected with test macro adaptation board by cable, in tested system, the jtag interface of each measured piece needs to be connected with the jtag interface that adaptation board is expanded, after various level form is carried out adaptation by adaptation board, introduce interfacing expansion module.When test starts, primary controller sends test instruction to jtag controller, after JTAG controls to produce test vector, the FPGA in each boundary scanning device in system under test (SUT) and the interfacing expansion module in test macro is controlled by JTAG, system under test (SUT) peripheral interface (comprising input and output) can be realized, and in system under test (SUT), the interconnection situation of signal between measured piece, final testing result can show in primary controller, and forms test report.
When functional test, especially for the test of system under test (SUT) high speed interface and optical interface agreement, the interfacing expansion module in native system can be utilized to realize.In order to support high-speed communication, PXIExpress Interface Expanding supported by primary controller and backboard, by programming in the FPGA in interfacing expansion module, test that is self-defined, each high-speed serial communication agreement such as RapidIO, Aurora can be realized, by adaptation board increases optical module, the test of fiber optic communication protocol in system under test (SUT) can be realized.
In sum, the invention provides a kind of boundary scan digital circuit test system based on PXI bus, at least can bring following beneficial effect:
1) test macro of the present invention have employed PXI bus architecture, improves the extendability of test macro, and tester according to the testing requirement of self, can select test module voluntarily.
2) boundary scan testing in test macro of the present invention, i.e. the test of low-speed interface in compatible traditional IEEE1149.1 standard, the test of compatible IEEE1149.6 standard high speed interface, has good compatibility for boundary scan testing especially.
3) test macro of the present invention is not only applicable to boundary scan testing, and compatible especially functional test, greatly improves the tempo of development of testing engineering, improve the efficiency of product test and maintenance.
4) test macro of the present invention have employed high-speed interface, i.e. the IEEE1149.6 standard of compatible boundary scan testing, again for tester provides the test function of self-defined high speed serialization agreement, has greatly enriched test function.
5) the system testing scheme of test macro proposition of the present invention, by force functional, is applicable to the test of current most of digital display circuit.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1., based on a boundary scan digital circuit test system for PXI bus, its computer is for testing each performance of measured piece or system under test (SUT); It is characterized in that: described test macro have employed PXI bus architecture, and comprise PXI backboard, master controller, jtag controller, 1 ~ N interfacing expansion module, 1 ~ M function expanding module, adaptation board; Wherein, N, M are positive integer; PXI backboard is all connected with master controller, jtag controller, interfacing expansion module, function expanding module, and adaptation board is all connected with master controller, jtag controller, interfacing expansion module, function expanding module; Master controller is connected by the keyboard of USB interface and described computing machine, mouse, is also connected with the display of described computing machine by DVI.
2. as claimed in claim 1 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: PXI backboard is as the backboard of the test cabinet of the described test macro of collecting, jtag controller is connected with JTAG and PXI backboard by PXI bus, and interfacing expansion module is connected with JTAG and PXI backboard by PXI bus equally.
3. as claimed in claim 1 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: jtag controller controls to be positioned at each interfacing expansion module of test machine case on the one hand by JTAG, on the other hand JTAG is drawn described test cabinet to measured piece or system under test (SUT) by adaptation board, described test cabinet is for accommodating described test macro.
4., as claimed in claim 3 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: jtag controller comprises PXI connector P1, PXI connector P2, PCI bridge, FPGA, JTAG bridge; Due to the expansion that two PXI connectors are PCI bridges, the interface of two PXI connectors is while reservation PCI function, turn increase Trigger Bus, Trigger Bus on PXI connector P2 is connected with FPGA, and the pci bus on PXI connector P1 is connected with PCI bridge, after pci bus is converted to local bus by PCI bridge, deliver in FPGA, FPGA, by Instruction decoding, generates corresponding jtag test vector, delivers to JTAG bridge by jtag interface; JTAG bridge have JTAG expanded function with by 1 road JTAG signal extension to multichannel, controlled the jtag interface in other modules in test cabinet by PXI connector P1, and all jtag interfaces in measured piece and system under test (SUT) simultaneously.
5., as claimed in claim 1 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: interfacing expansion module is expanded according to the pin number of measured piece, for the loopback test of boundary scan; Interfacing expansion module is connected with JTAG and PXI backboard by PXI bus on the one hand, is connected on the other hand by adaptation board with measured piece or system under test (SUT).
6., as claimed in claim 1 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: the function that function expanding module is tested needed for system under test (SUT) is expanded, for functional test; Function expanding module is connected with JTAG and PXI backboard by PXI bus on the one hand, is connected on the other hand by adaptation board with measured piece or system under test (SUT).
7., as claimed in claim 6 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: function expanding module comprises PXI connector P1, PXI connector P2, PCI bridge, JTAG bridge, FPGA and external interface; Trigger Bus on PXI connector P2 is connected with FPGA, pci bus on PXI connector P1 is connected with PCI bridge, JTAG and JTAG bridge on PXI connector P1 is connected, the jtag interface of the FPGA on PXI backboard is also connected with JTAG bridge, and the idle pin on PXI connector P2 is as the expansion of JTAG cascade.
8. as claimed in claim 1 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: adaptation board is as the external interface of the test cabinet of the described test macro of collecting, and adaptation board is connected with measured piece or system under test (SUT).
9. as claimed in claim 1 based on the boundary scan digital circuit test system of PXI bus, it is characterized in that: described test macro also comprises power module (7), power module (7) is as the supply module of the test cabinet of the described test macro of collecting; Extraneous 220V is exchanged input by power module (7), is converted to required power supply in described test cabinet, and powers to measured piece and system under test (SUT).
10. the method for testing based on the boundary scan digital circuit test system of PXI bus as in one of claimed in any of claims 1 to 9, it is characterized in that: master controller sends test instruction to jtag controller, after jtag controller controls to produce test vector, the FPGA in each boundary scanning device in system under test (SUT) and the interfacing expansion module in test macro is controlled by jtag controller, realize in system under test (SUT) peripheral interface and system under test (SUT), the interconnection situation of signal between measured piece, final testing result shows under the control of master controller in described display, and form test report.
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| CN107692901A (en) * | 2017-10-31 | 2018-02-16 | 惠州市永力实业有限公司 | Intelligent knife rest control circuit and its application |
| CN108062055A (en) * | 2017-12-29 | 2018-05-22 | 陕西海泰电子有限责任公司 | A kind of PXIe controllers remote control system and method based on optical fiber |
| CN109065986A (en) * | 2018-08-27 | 2018-12-21 | 苏州索贝斯新能源科技有限公司 | A kind of battery temperature control circuit |
| CN109116314A (en) * | 2018-07-06 | 2019-01-01 | 中国电子科技集团公司第十四研究所 | VPX module universal testing method |
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| CN107505512A (en) * | 2017-04-27 | 2017-12-22 | 中国人民解放军海军航空工程学院 | Electronics intelligent fault monitoring method and device based on JTAG technologies |
| CN107692901A (en) * | 2017-10-31 | 2018-02-16 | 惠州市永力实业有限公司 | Intelligent knife rest control circuit and its application |
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| CN109116314A (en) * | 2018-07-06 | 2019-01-01 | 中国电子科技集团公司第十四研究所 | VPX module universal testing method |
| CN109065986A (en) * | 2018-08-27 | 2018-12-21 | 苏州索贝斯新能源科技有限公司 | A kind of battery temperature control circuit |
| CN109655736A (en) * | 2018-12-21 | 2019-04-19 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of quick pinpoint method of chip solder failure |
| CN109541445A (en) * | 2018-12-26 | 2019-03-29 | 中核控制系统工程有限公司 | A kind of fpga chip device for testing functions and method |
| CN110907857B (en) * | 2019-12-10 | 2022-05-13 | 上海国微思尔芯技术股份有限公司 | Automatic connector detection method based on FPGA |
| CN110907857A (en) * | 2019-12-10 | 2020-03-24 | 思尔芯(上海)信息科技有限公司 | FPGA-based connector automatic detection method |
| CN111289876A (en) * | 2020-03-02 | 2020-06-16 | 电子科技大学 | A Boundary Scan Interconnect Test Vector Generation Method for Large-Scale Circuits |
| CN111398795A (en) * | 2020-04-07 | 2020-07-10 | 华北水利水电大学 | FPGA internal DSP unit testing device and using method |
| CN111579974B (en) * | 2020-06-09 | 2021-09-03 | 中国电子科技集团公司第十四研究所 | Embedded system for realizing boundary scan test and test method |
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| CN115443413A (en) * | 2020-08-31 | 2022-12-06 | 华为技术有限公司 | Chip test circuit and circuit test method |
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