CN105468485A - Character-oriented memory test method - Google Patents
Character-oriented memory test method Download PDFInfo
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- CN105468485A CN105468485A CN201510808092.0A CN201510808092A CN105468485A CN 105468485 A CN105468485 A CN 105468485A CN 201510808092 A CN201510808092 A CN 201510808092A CN 105468485 A CN105468485 A CN 105468485A
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- 238000010998 test method Methods 0.000 title abstract 3
- 238000012360 testing method Methods 0.000 claims abstract description 119
- 230000008878 coupling Effects 0.000 claims abstract description 21
- 238000010168 coupling process Methods 0.000 claims abstract description 21
- 238000005859 coupling reaction Methods 0.000 claims abstract description 21
- 238000007711 solidification Methods 0.000 claims description 7
- 230000008023 solidification Effects 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 9
- 238000001514 detection method Methods 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
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- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a character-oriented memory test method. The method comprises the following steps: in allusion to different to-be-tested memory error types, respectively generating memory test model sequences according to memory chip bit widths; and carrying out memory test according to the generated memory test model sequences. Through the character-oriented memory test method, the memory test model sequences are generated according to the memory chip bit widths by adopting a character-oriented design manner, so that the memory bit widths are fully utilized and the memory test efficiency is improved; through listing the set of error conditions and simplifying the redundant error conditions in the set, a simplest closed-loop double-bit test sequence containing all the to-be-covered error conditions is obtained and guided into a basic model sequence which is generated according to the memory chip bit widths so as to generate the memory test model sequences, and the generated memory test model sequences are used for carrying out memory test, so that a shortest path is adopted to detect all the to-be-covered error conditions between every two bits and finally the efficient detection of coupling errors is realized.
Description
Technical field
The present invention relates to memory test technical field, particularly relate to a kind of word-oriented internal storage testing method.
Background technology
Memory test has a lot of classic algorithm, and march serial algorithm is exactly one of them, but the march algorithm of classics is all towards position (bitoriented), and this is determined by the physical arrangement of early stage internal memory.Internal memory is now all based on word (word), and memory chip bit wide (chipwidth) is in the majority with 4 (bit) or 8 (bit).Therefore under nowadays condition still application surface mainly contain two to the march algorithm of position (bitoriented) in shortcoming:
First, test performance can be lower;
Secondly, the mistake of coupling fault (couplingfaults) type cannot be detected.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The invention provides a kind of efficient word-oriented internal storage testing method, and realize further detecting coupling fault.
The invention provides a kind of word-oriented internal storage testing method, comprising:
For different EMS memory error types to be measured, according to memory chip bit wide each self-generating memory test Model sequence;
The each described memory test Model sequence generated is utilized to carry out memory test.
The word-oriented internal storage testing method that the many embodiments of the present invention provide generates memory test Model sequence according to memory chip bit wide, have employed word-oriented design and generate memory test Model sequence, make full use of internal memory bit wide, improve the efficiency of memory test;
The error condition that the word-oriented internal storage testing method that some embodiments of the invention provide needs to cover by enumerating test, enumerate the set of the issuable error condition of dibit combination of two, simplify the error condition of redundancy in set again, obtain the simplest closed loop dibit cycle tests comprising the error condition that all needs cover, the shortest detection path of all error conditions can be detected; Again the simplest closed loop dibit cycle tests is directed into the basic model sequence generated according to memory chip bit wide, generates memory test Model sequence; Finally utilize the memory test Model sequence of generation to carry out memory test, achieve and adopt shortest path to detect all error conditions needing to cover between every two, finally achieve the efficient detection to coupling fault (couplingfaults).
Accompanying drawing explanation
Below with reference to the accompanying drawings illustrate embodiments of the invention, above and other objects, features and advantages of the present invention can be understood more easily.Parts in accompanying drawing are just in order to illustrate principle of the present invention.In the accompanying drawings, same or similar technical characteristic or parts will adopt same or similar Reference numeral to represent.
The process flow diagram of the word-oriented internal storage testing method that Fig. 1 provides for one embodiment of the invention.
Fig. 2 is the process flow diagram of step S30 in internal storage testing method shown in Fig. 1.
Fig. 3 is the process flow diagram of step S31 in internal storage testing method shown in Fig. 2.
Fig. 4 be dibit 00 in one embodiment of the invention, 01,10, the schematic diagram of the set of error condition that produces of 11 4 kind of state combination of two.
Fig. 5 is the schematic diagram after the error condition of redundancy has been simplified in set shown in Fig. 4.
Embodiment
With reference to the accompanying drawings embodiments of the invention are described.The element described in an accompanying drawing of the present invention or a kind of embodiment and feature can combine with the element shown in one or more other accompanying drawing or embodiment and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.
The process flow diagram of the word-oriented internal storage testing method that Fig. 1 provides for one embodiment of the invention.
As shown in Figure 1, in the present embodiment, word-oriented internal storage testing method provided by the present invention comprises:
S30: for different EMS memory error types to be measured, according to memory chip bit wide each self-generating memory test Model sequence;
S50: utilize each described memory test Model sequence generated to carry out memory test.
The word-oriented internal storage testing method that above-described embodiment provides generates memory test Model sequence according to memory chip bit wide, have employed word-oriented design and generates memory test Model sequence, make full use of internal memory bit wide, improve the efficiency of memory test.
Fig. 2 is the process flow diagram of step S30 in internal storage testing method shown in Fig. 1.
As shown in Figure 2, in a preferred embodiment, step S30 specifically comprises:
S31: according to described EMS memory error type to be measured, generate the simplest closed loop dibit cycle tests;
S33: according to described memory chip bit wide formation base Model sequence;
S35: the simplest described closed loop dibit cycle tests is directed in described basic model sequence, obtains described memory test Model sequence.
Fig. 3 is the process flow diagram of step S31 in internal storage testing method shown in Fig. 2.
As shown in Figure 3, in a preferred embodiment, step S31 specifically comprises:
S311: according to described EMS memory error type to be measured, enumerates in test the error condition needing to cover;
S313: enumerate dibit 00,01,10, the set of described error condition that produces of 11 4 kind of state combination of two;
S315: the error condition of simplifying redundancy in the set of described error condition, obtains the simplest closed loop dibit cycle tests comprising the error condition that all needs cover.
In a preferred embodiment, described EMS memory error type to be measured is coupling fault (couplingfaults), at least comprise and be inverted coupling fault (inversionCFs, be called for short CFin), solidification coupling fault (idempotentCFs, be called for short CFid), interference and coupling fault (disturbCFs, be called for short CFdst) and state coupling fault (stateCFs is called for short CFst).
In a preferred embodiment, described memory chip bit wide is 4 or 8.Particularly, in the present embodiment, memory chip bit wide is 8, in more embodiments, memory chip bit wide can adopt 4 or other meet chip standard design figure place, do not exceed the protection domain of technical solution of the present invention.
Comprise solidification coupling fault below by way of an EMS memory error type to be measured, memory chip bit wide is that the example of 8 is described in detail.
S30: for solidification coupling fault to be measured, generates memory test Model sequence according to memory chip bit wide.The memory test Model sequence generated for the coupling fault of other type is not specifically addressed at this.
To test solidification coupling fault:
S311: according to solidification coupling fault to be measured, list in test the error condition needing to cover: (the change trend of change position state, the wrong variation tendency of the associated bit state that the change changing position state causes), specifically comprise (c0 liter, c1 liter), (c0 liter, c1 falls), (c0 falls, c1 liter), (c0 falls, c1 falls), (c1 liter, c0 liter), (c1 liter, c0 falls), (c1 falls, c0 liter) and (c1 falls, c0 falls), wherein c0 is the last position in described dibit, and c1 is latter one in described dibit.
S313: enumerate dibit 00,01,10, the set of above-mentioned error condition that produces of 11 4 kind of state combination of two.
Fig. 4 be dibit 00 in the present embodiment, 01,10, the schematic diagram of the set of error condition that produces of 11 4 kind of state combination of two.
As shown in Figure 4, dibit (c0, c1) be respectively 00,01,10,11 4 kind of issuable mistake of state combination of two comprise:
00 → 01:(c1 liter, c0 liter);
01 → 00:
(c1 falls, c0 liter);
00 → 11:(c0 liter, c1 falls), (c1 liter, c0 falls);
11 → 00:(c0 falls, c1 liter), (c1 falls, c0 liter);
00 → 10:
(c0 liter, c1 liter);
10 → 00:
(c0 falls, c1 liter);
01 → 11:
(c0 liter, c1 falls);
11 → 01:
(c0 falls, and c1 falls);
01 → 10:(c0 liter, c1 liter), (c1 falls, and c0 falls);
10 → 01:(c0 falls, and c1 falls), (c1 liter, c0 liter);
11 → 10:
(c1 falls, and c0 falls);
10 → 11:
(c1 liter, c0 falls);
Fig. 5 is the schematic diagram after the error condition of redundancy has been simplified in set shown in Fig. 4.
Can be found out by above-mentioned enumerating, the error condition indicating underscore has repeated and redundant, and therefore its test path can be simplified.
S315: the error condition of simplifying redundancy in the set of described error condition, obtains the simplest closed loop dibit cycle tests comprising the error condition that all needs cover.
As shown in Figure 5, simplify rear remaining test path and comprise 00 → 01,00 → 11,11 → 00,01 → 10,10 → 01.
Resulting in and can cover all the simplest closed loop test paths 00 → 11 → 00 → 01 → 10 → 01 needing the type of error detected, be i.e. the simplest closed loop dibit cycle tests (00,11,00,01,10,01).
S33: according to described memory chip bit wide formation base Model sequence.
Particularly, according to the memory chip bit wide of 8, adopt first foundation Model sequence 01-23-45-67, the second basic model sequence 02-13-46-57 and the 3rd basic model sequence 04-15-26-37.
S35: the simplest described closed loop dibit cycle tests is directed in described basic model sequence, obtains described memory test Model sequence.
Particularly, the simplest closed loop dibit cycle tests (00,11,00,01,10,01) is directed in first foundation Model sequence 01-23-45-67, obtains the first memory test Model sequence:
From above-mentioned first memory test Model sequence, first memory test Model sequence, except can covering all error conditions of 01,23,45,67 these 4 pairs of dibits, also can cover all error conditions of the dibits such as 03,05,07,21,25,27,41,43,47,61,63,65 simultaneously.
The simplest closed loop dibit cycle tests (00,11,00,01,10,01) is directed in the second basic model sequence 02-13-46-57, obtains the second memory test Model sequence:
From above-mentioned second memory test Model sequence, second memory test Model sequence, except can covering all error conditions of 02,13,46,57 these 4 pairs of dibits, also can cover all error conditions of the dibits such as 03,06,07,12,16,17,42,43,47,52,53,57 simultaneously.
The simplest closed loop dibit cycle tests (00,11,00,01,10,01) is directed in the 3rd basic model sequence 04-15-26-37, obtains the 3rd memory test Model sequence:
From above-mentioned 3rd memory test Model sequence, 3rd memory test Model sequence, except can covering all error conditions of 04,15,26,37 these 4 pairs of dibits, also can cover all error conditions of the dibits such as 05,06,07,14,16,17,24,25,27,34,35,36 simultaneously.
Therefore, above-mentioned three groups of memory test Model sequence can cover all error conditions of in 0-7 these 8 any two.
Because before each group in above-mentioned three groups of memory test Model sequence, two row be " 0 " and " 1 " respectively, the type of error covered is identical, and one group can cover the error condition of any two, therefore can simplify during merging, retain one group.
Merge described first memory test Model sequence, the second memory test Model sequence and the 3rd memory test Model sequence, simplify the sequence after merging, obtain described memory test Model sequence:
S50: utilize each described memory test Model sequence generated to carry out memory test.
The error condition that the word-oriented internal storage testing method that the above embodiment of the present invention provides needs to cover by enumerating test, enumerate the set of the issuable error condition of dibit combination of two, simplify the error condition of redundancy in set again, obtain the simplest closed loop dibit cycle tests comprising the error condition that all needs cover, the shortest detection path of all error conditions can be detected; Again the simplest closed loop dibit cycle tests is directed into the basic model sequence generated according to memory chip bit wide, generates memory test Model sequence; Finally utilize the memory test Model sequence of generation to carry out memory test, achieve and adopt shortest path to detect all error conditions needing to cover between every two, finally achieve the efficient detection to coupling fault (couplingfaults).
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although with reference to previous embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a word-oriented internal storage testing method, is characterized in that, comprising:
For different EMS memory error types to be measured, according to memory chip bit wide each self-generating memory test Model sequence;
The each described memory test Model sequence generated is utilized to carry out memory test.
2. internal storage testing method according to claim 1, is characterized in that, described for different EMS memory error types to be measured, generates memory test Model sequence separately comprise according to operation bit wide:
According to described EMS memory error type to be measured, generate the simplest closed loop dibit cycle tests;
According to described memory chip bit wide formation base Model sequence;
The simplest described closed loop dibit cycle tests is directed in described basic model sequence, obtains described memory test Model sequence.
3. internal storage testing method according to claim 2, is characterized in that, described according to described EMS memory error type to be measured, generates the simplest closed loop dibit cycle tests and comprises:
According to described EMS memory error type to be measured, enumerate in test the error condition needing to cover;
Enumerate dibit 00,01,10, the set of described error condition that produces of 11 4 kind of state combination of two;
Simplify the error condition of redundancy in the set of described error condition, obtain the simplest closed loop dibit cycle tests comprising the error condition that all needs cover.
4. the internal storage testing method according to any one of claim 2-3, is characterized in that, described EMS memory error type to be measured is coupling fault, at least comprises and is inverted coupling fault, solidification coupling fault, interference and coupling fault and state coupling fault.
5. the internal storage testing method according to any one of claim 1-3, is characterized in that, described memory chip bit wide is 4 or 8.
6. internal storage testing method according to claim 3, it is characterized in that, when described EMS memory error type to be measured is for solidification coupling fault, the described error condition covered that needs is (the change trend of change position state, the wrong variation tendency of the associated bit state that the change changing position state causes), specifically comprise (c0 liter, c1 liter), (c0 liter, c1 falls), (c0 falls, c1 liter), (c0 falls, and c1 falls), (c1 liter, c0 liter), (c1 liter, c0 falls), (c1 falls, c0 liter) and (c1 falls, and c0 falls);
Wherein c0 is the last position in described dibit, and c1 is latter one in described dibit.
7. internal storage testing method according to claim 6, is characterized in that, the simplest closed loop dibit cycle tests obtained after simplifying the error condition of redundancy is (00,11,00,01,10,01).
8. internal storage testing method according to claim 7, it is characterized in that, described memory chip bit wide is 8, and described basic model sequence comprises first foundation Model sequence 01-23-45-67, the second basic model sequence 02-13-46-57 and the 3rd basic model sequence 04-15-26-37.
9. internal storage testing method according to claim 8, is characterized in that, is describedly directed in described basic model sequence by the simplest described closed loop dibit cycle tests, obtains described memory test Model sequence and comprises:
The simplest closed loop dibit cycle tests (00,11,00,01,10,01) is directed in first foundation Model sequence 01-23-45-67, obtains the first memory test Model sequence:
The simplest closed loop dibit cycle tests (00,11,00,01,10,01) is directed in the second basic model sequence 02-13-46-57, obtains the second memory test Model sequence:
The simplest closed loop dibit cycle tests (00,11,00,01,10,01) is directed in the 3rd basic model sequence 04-15-26-37, obtains the 3rd memory test Model sequence:
Merge described first memory test Model sequence, the second memory test Model sequence and the 3rd memory test Model sequence, simplify the sequence after merging, obtain described memory test Model sequence:
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Cited By (2)
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| CN109086180A (en) * | 2018-08-24 | 2018-12-25 | 郑州云海信息技术有限公司 | A kind of memory inspection testing method |
| US11335102B2 (en) | 2018-08-09 | 2022-05-17 | Zhejiang Dahua Technology Co., Ltd. | Methods and systems for lane line identification |
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| US20090199057A1 (en) * | 2008-01-31 | 2009-08-06 | University Of Kuwait | March DSS: Memory Diagnostic Test |
| CN102157205A (en) * | 2011-05-10 | 2011-08-17 | 北京航空航天大学 | Method for testing fault of multiposition memorizer inlaid in FPGA |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11335102B2 (en) | 2018-08-09 | 2022-05-17 | Zhejiang Dahua Technology Co., Ltd. | Methods and systems for lane line identification |
| CN109086180A (en) * | 2018-08-24 | 2018-12-25 | 郑州云海信息技术有限公司 | A kind of memory inspection testing method |
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