CN105448932A - Thin film transistor structure and manufacturing method thereof - Google Patents

Abstract

A low-temperature polysilicon thin-film transistor structure, including a glass base layer, a buffer layer, an active layer, a gate insulating layer, a gate layer with a gate and an independent electrode, an internal dielectric layer, a source/ The drain layer, an organic material layer, a common electrode layer, a passivation layer and a pixel electrode layer. The source/drain layer has a source and a drain connected to the active layer, and a first conductive material connected to the independent electrode. The drain has a laterally extending portion above the independent electrode. The common electrode layer has a second conductive material connected to the first conductive material. Thereby, a first capacitor is formed by the pixel electrode layer and the common electrode layer, and a second capacitor is formed by the drain lateral extension and the independent electrode.

Description

Thin film transistor structure and manufacturing method

technical field

The present invention relates to a thin film transistor (ThinFilmTransistor, TFT) structure and manufacturing method, and especially a thin film transistor structure suitable for low temperature polysilicon (Low Temperature Poly-silicon (LTPS)) process, with an increased storage capacitor (Cst).

Background technique

In a thin film transistor liquid crystal display (Liquid Crystal Display (LCD)) manufactured by a low-temperature polysilicon process, the storage capacitor is mainly composed of a common electrode (Com) and a pixel electrode (Pixel). The common electrode and the pixel electrode are generally made of transparent indium tin oxide (ITO). Along with the development of high-pixel products, the charging time of the pixel electrode is getting shorter and shorter, and its size is getting smaller and smaller, which leads to insufficient charging of the storage capacitor, thereby affecting the image quality.

Referring to FIG. 1 , it is a conventional TFT structure 100 based on low-temperature polysilicon process, including a glass layer (glass layer) 102, a buffer layer (buffer layer) 104, an active layer 106 made of semiconductor materials, a gate insulation Edge (gateinsulation) layer 108, a gate (gate) layer 110, an internal dielectric layer (ILD) 112, a source / drain (SD) layer 114, an organic material (organic) layer 116, a common electrode ( COM) layer 118 , a passivation (PV) layer 120 and a pixel electrode (pixel) layer 122 . Wherein, the common electrode layer 118 and the pixel electrode layer 122 are both made of transparent indium tin oxide. A storage capacitor Cst is formed by the common electrode layer 118 and the pixel electrode layer 122 . Such a single storage capacitor structure cannot meet the increasing pixel count requirements of high-resolution screens.

Contents of the invention

The invention is a thin film transistor structure suitable for Low Temperature Poly-silicon (LTPS) process, which has two storage capacitors. According to the teaching of the present invention, the thin film transistor structure includes a glass base layer, an active layer is located above the glass base layer, a gate layer is located above the active layer, and a gate layer is located above the active layer. directly above and an independent electrode, a source/drain layer is located above the gate layer, has a source connected to the active layer, a drain connected to the active layer, and a first conductive The material is connected to the independent electrode, and the drain has a lateral extension above the independent electrode; a common electrode is located above the source/drain layer, and has a second conductive material connected to the first conductive material and a pixel electrode layer located above the source/drain layer, having a pixel electrode connected to the drain, the pixel electrode and the common electrode forming a first storage capacitor, the lateral extension of the drain and the drain The individual electrodes form a second storage capacitor.

According to a further teaching of the present invention, the thin film transistor structure further includes a buffer layer located between the glass base layer and the active layer.

According to another teaching of the present invention, the TFT structure further includes a gate insulating layer on the buffer layer and wrapping the active layer therein.

Moreover, according to the teaching of the present invention, the thin film transistor structure further includes an internal dielectric layer on the gate insulating layer and covering the gate and the independent electrode therein, the source and the drain are extending downward through the inner dielectric layer and the gate insulating layer to be connected to the active layer.

Meanwhile, according to the teaching of the present invention, the gate of the thin film transistor structure is located between the source and the drain.

Further, according to the thin film transistor structure of the present invention, it further includes an organic material layer located above the internal dielectric layer and covering the source, drain lateral extensions and the first conductive material therein, the common electrode layer A line is formed on the organic material layer, and the second conductive material line extends downward through the organic material layer to connect with the first conductive material.

Finally, according to the thin film transistor structure of the present invention, it further includes a passivation layer located above the common electrode layer and covering the common electrode layer therein, the pixel electrode layer is anchored on the passivation layer, and the pixel electrode A line extends down through the passivation layer to connect to the drain.

Description of drawings

The invention is herein described, by way of example only, with reference to the accompanying drawings, in which:

Fig. 1 is a cross-sectional view, which shows a low temperature polysilicon thin film transistor structure made according to conventional technology;

Fig. 2 is a cross-sectional view, which shows a structure of a low-temperature polysilicon thin film transistor made according to the present invention;

Fig. 3 is a cross-sectional view showing the first to fifth steps of manufacturing the low-temperature polysilicon thin film transistor structure of the present invention;

4 is a cross-sectional view showing the sixth to seventh steps of manufacturing the low-temperature polysilicon thin film transistor structure of the present invention;

Fig. 5 is a cross-sectional view showing an eighth step of manufacturing the low-temperature polysilicon thin film transistor structure of the present invention;

Fig. 6 is a cross-sectional view showing a ninth step of manufacturing the low temperature polysilicon thin film transistor structure of the present invention; and

7 is a cross-sectional view showing a tenth step of manufacturing the low temperature polysilicon thin film transistor structure of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention is a low-temperature polysilicon thin film transistor structure, which can be used in liquid crystal displays, and each thin film transistor structure has two storage capacitors.

The principles, operation and fabrication of a thin film transistor structure according to the present invention may be better understood with reference to the drawings and accompanying descriptions.

The following descriptions of the various embodiments refer to the accompanying drawings to illustrate specific embodiments in which the present invention can be practiced. The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are for reference only The orientation of the attached schema. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

In the figures, structurally similar units are denoted by the same reference numerals.

Please refer to the accompanying drawings now, FIG. 2 shows a thin film transistor 200 constructed according to the present invention, which has: a glass base layer 202, a buffer layer 204, an active layer 206, a gate insulating layer along the direction from bottom to top. The edge layer 208 , a gate layer 210 , an internal dielectric layer 212 , a source/drain layer 214 , an organic material layer 216 , a common electrode layer 218 , a passivation layer 220 and a pixel electrode layer 222 . It can be understood that the glass substrate 202 can have a large size to form a plurality of thin film transistors 200 thereon to form a thin film transistor array.

According to the present invention, the active layer 206 is made of semiconductor material. The gate layer 210 has a gate 2102 and an independent electrode 2104 electrically isolated from the gate 2102 . The source/drain layer 214 has a source 2142 and a drain 2144 electrically connected to the active layer 206, wherein the drain 2144 has an extension 2146 parallel to the top of the independent electrode 2104, and is connected to the independent electrode 2104. The individual electrodes 2104 are spaced apart by the inner dielectric layer 212 . The gate 2102 is located between the source 2142 and the drain 2144 . A first via hole 2122 is defined in the internal dielectric layer 212 at one side of the drain extension 2146 and communicates with the independent electrode 2104 . The first through hole 2122 is filled with a first conductive material 2124 for forming the source/drain 2142 , 2144 . A second through hole 2162 is formed in the organic material layer 216 to communicate with the first through hole 2122 . The second through hole 2162 is filled with a second conductive material 2164 forming the common electrode layer 218 , and the second conductive material 2164 and the common electrode layer 218 are integrally formed. Thus, the common electrode layer 218 is electrically connected to the individual electrode 2104 through the second and first conductive materials 2164 , 2124 . The pixel electrode layer 222 has a downwardly extending portion 2222 passing through the region 2202 of the passivation layer 220 between the common electrode layer 218 and the organic material layer 216 to be electrically connected to the drain 2144 . According to the present invention, a first storage capacitor Cst1 is formed between the pixel electrode layer 222 and the common electrode layer 218, and a second storage capacitor Cst2 is formed between the drain extension 2146 and the individual electrode Between 2104.

The present invention also provides a method for manufacturing the thin film transistor 200 of the present invention, the steps of which are as follows:

1. With reference to Fig. 3, at first provide a base layer 202, preferably (but not limited to) glass is made, change ground, this base layer 202 also can be made of such as transparent plastic plate;

2. Form a buffer layer 204 on the glass base layer 202 by deposition method, the buffer layer 204 can be aluminum nitride or copper nitride;

3. An active layer 206 is formed on the buffer layer 204, which is made of a semiconductor material. In the present invention, the semiconductor material is preferably polysilicon;

4. A gate insulating layer 208 is formed on the active layer 206, which can be made of silicon dioxide;

5. A gate layer 210 is formed on the gate insulating layer 208, including a gate 2102 and an independent electrode 2104. The gate layer 210 can be made of a metal, such as aluminum is formed on the gate by sputtering. on the gate insulating layer 208;

6. Next, please refer to FIG. 4 , an internal dielectric layer 212 is formed on the gate insulating layer 208 and wraps the gate layer 210 therein. The inner dielectric layer 212 can be made of silicon nitride, and a first via hole 2122 is formed in the inner dielectric layer 212 to connect the top of the inner dielectric layer 212 and the independent electrode 2104;

7. Forming a source/drain layer 214 on the inner dielectric layer 212 includes a source 2142 and a drain 2144, wherein the bottom of the source 2142 extends through the inner dielectric layer 212 and the gate insulation Layer 208 is connected to the outer end 2062 of the active layer 206 , and the bottom of the drain 2144 extends through the inner dielectric layer 212 and the gate insulating layer 208 to connect to the inner end 2064 of the active layer 206 . The drain 2144 has a lateral extension 2146 positioned parallel to and spaced above the independent electrode 2104. A first conductive material 2124 is formed on the inner dielectric while the source/drain layer 214 is being formed. Layer 212 extends upward and downward through the first via 2122 to connect with the individual metal electrode 2104 . The source 2142, the drain 2144 and the first conductive material 2124 are separated from each other;

8. Referring to FIG. 5 , an organic material layer 216 is formed on the inner dielectric layer 212 and covers the source 2142 , the drain lateral extension 2146 and the first conductive material 2124 . The organic material layer 216 has a middle cavity 2160 to expose the top of the drain 2144 and a second via hole 2162 connecting the top of the organic material layer 216 and the top of the first conductive material 2124;

9. With reference to Fig. 6, a common electrode layer 218 is formed on the top of the organic material layer 216, wherein, when forming the common electrode layer 218, a second conductive material 2164 integrated with the common electrode layer 218 is directed toward The bottom extends through the second through hole 2162 to connect with the first conductive material 2122 . The common electrode layer 218 is made of transparent conductive material, such as indium tin oxide (ITO);

10. With reference to FIG. 7, a passivation layer 220 is formed on the common electrode layer 218, and extends down into a middle via hole (not shown) of the common electrode layer 218 and a middle cavity of the organic material layer 216. 2160 in. The passivation layer 220 has a middle via hole 2202 connecting the top of the passivation layer 220 and the top of the drain 2144 ;

11. Referring to FIG. 2, finally, a pixel electrode layer 222 is formed on the passivation layer 220. The pixel electrode layer 222 is made of a transparent conductive material such as indium tin oxide (ITO), wherein a middle The pixel electrode extends down through the middle via hole 2202 of the passivation layer 220 to connect with the drain 2144 . Such a low-temperature polysilicon thin film transistor 200 disclosed in the present invention is obtained, which has two parallel storage capacitors Cst1, Cst2, which can effectively increase the charging of the storage capacitors to improve the picture quality of high-resolution screens.

It will be appreciated that the above description is by way of example only, and that many other embodiments are possible within the spirit and scope of the invention.

Claims (10)

1. a low-temperature polycrystalline silicon thin film transistor structure, is characterized in that, includes:

One basic unit;

One active layer position is above this basic unit;

The top of one this active layer of grid layer position, includes a grid position directly over this active layer and an absolute electrode;

One source/drain layer position is above this grid layer, there is the one source pole be separated from each other be connected with this active layer, one drain electrode is connected with this active layer, and be connected with this absolute electrode with the first electric conducting material, this drain electrode has a horizontal expansion position above this absolute electrode;

Community electrode layer position is above this source/drain layer, and one second electric conducting material with one is connected with this first electric conducting material; And

One pixel electrode layer position is above this source/drain layer, there is a pixel electrode be connected with this drain electrode, this pixel electrode layer and this common electrode layer form one first reservior capacitor, and this drain electrode lateral extensions and this absolute electrode form one second reservior capacitor.

2. low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 1, is characterized in that: include a resilient coating further between this basic unit and this active layer.

3. low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 2, is characterized in that: include further a gate insulator position on this resilient coating and this active layer coated wherein.

4. low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 3, it is characterized in that: include further an internal dielectric layer position on this gate insulator and this grid coated and absolute electrode wherein, this source electrode and this drain electrode system extend downwardly through this internal dielectric layer and this gate insulator to be connected with this active layer.

5. low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 4, is characterized in that: this grid system position is between this source electrode and drain electrode.

6. low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 4, it is characterized in that: include further an organic material layer position above this inner Jie portion electric layer and this source electrode coated, drain electrode lateral extensions and this first electric conducting material wherein, these common electrode series of strata are formed on this organic material layer, and this second electric conducting material system extends downwardly through this organic material layer to be connected with this first electric conducting material.

7. low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 6, it is characterized in that: including a passivation layer position further above this common electrode layer covers this common electrode layer wherein, this pixel electrode series of strata position is on this passivation layer, and this pixel electrode system extends downwardly through this passivation layer to be connected with this drain electrode.

8. manufacture a method for low-temperature polycrystalline silicon thin film transistor structure, it is characterized in that, the method includes following step:

A. a basic unit is formed;

B. a resilient coating is formed in this basic unit;

C. form an active layer on this resilient coating, this active layer is made by semi-conducting material;

D. be shaped one first insulating barrier on this resilient coating and this active layer coated wherein;

E. form a grid layer on this insulating barrier, include a grid and an absolute electrode;

F. formed an internal dielectric layer position on which insulating layer and this grid layer coated wherein;

G. a source/drain layer and the first electric conducting material is formed on this internal dielectric layer, this source/drain layer has one source pole to extend downwardly through this internal dielectric layer and this insulating barrier to be connected with one end of this active layer, extend downwardly through this internal dielectric layer with a drain electrode to be connected with the other end of this active layer with this insulating barrier, this drain electrode has a horizontal expansion position above this absolute electrode, and this first electric conducting material extends downwardly through this inner Jie portion electric layer to be connected with this absolute electrode;

H. one second insulating barrier is formed on this inner Jie portion electric layer;

I. form community electrode on this second insulating barrier, this common electrode has the second electric conducting material of an one to extend downwardly through this second insulating barrier to be connected with this first electric conducting material;

J. a passivation layer position is formed on this common electrode layer; And

K. form a pixel electrode layer position on this passivation layer, this pixel electrode layer some extend downwardly through this passivation layer come be connected with this drain electrode;

Wherein, one first storage capacitor system is formed between this pixel electrode layer and this common electrode layer, and one second storage capacitor system is formed between this drain electrode lateral extensions and this absolute electrode.

9. the method manufacturing low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 8, is characterized in that: this second insulating barrier is an organic material layer.

10. the method manufacturing low-temperature polycrystalline silicon thin film transistor structure as claimed in claim 8, is characterized in that: this grid system position is between this source electrode and this drain electrode.