CN105448684B - The method for forming grid - Google Patents

Abstract

The invention provides a method for forming a gate, comprising: providing a substrate, so that the substrate has a first region and a second region; forming a dummy gate and an interlayer dielectric layer; forming a sacrificial layer; removing the dummy gate located in the first region , to form a first opening in the interlayer dielectric layer in the first region; form a first metal layer in the surface of the sacrificial layer located in the second region, the surface of the interlayer dielectric layer in the first region, and the first opening; by chemical mechanical Part of the first metal layer and part of the sacrificial layer are removed by grinding to form a first gate. The beneficial effect of the present invention is that the dummy gate in the second region is not exposed during the chemical mechanical polishing process, and the problem of recess formation due to excessive removal of the dummy gate in the second region by chemical mechanical polishing is reduced, so that the dummy gate and the The surface formed by the interlayer dielectric layer is relatively smooth and has a relatively consistent height, which is beneficial to reduce bridging problems that may occur when the gate is subsequently formed.

Description

Method of Forming a Gate

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a gate.

Background technique

Complementary Metal Oxide Semiconductor (CMOS) is the basic unit in modern logic circuits, including PMOS and NMOS devices.

Both the PMOS and NMOS devices are composed of a gate (Gate), a P-type or N-type source region (Source) region or a drain region (Drain) region located in the substrate on both sides of the gate, and a drain region located between the source region and the drain region. The channel (Channel) constitutes.

With the development of semiconductor technology, the gate-last process (gate-last) is gradually used in the prior art to form the gate of the semiconductor device. This process generally forms a dummy gate first, and then forms a source region and a drain region. The interlayer dielectric layer is covered again, and the dummy gate is removed to form an opening in the interlayer dielectric layer, and the opening is filled with metal to form a metal layer. After the metal layer is formed, excess metal needs to be removed through a planarization process, and the metal in the opening is reserved to serve as the gate of the semiconductor device.

A chemical mechanical polishing (CMP) process is one of the planarization processes widely used at present. This process is one of the methods to achieve global planarization, especially with the reduction of feature size, the application range of chemical mechanical polishing is more extensive. For example, in the aforementioned gate-last process, chemical mechanical polishing may be used to remove unnecessary parts of the metal layer after the metal layer is formed.

However, transistors formed in the gate-last process have the problem of being easy to bridge with other devices.

Contents of the invention

The problem to be solved by the present invention is to provide a method for forming a gate, so as to reduce the problem that the gate is easily bridged with other devices.

In order to solve the above problems, the present invention provides a method for forming a gate, including:

providing a substrate having a first region for forming a first device and a second region for a second device;

forming dummy gates on the substrates of the first region and the second region respectively;

forming an interlayer dielectric layer on the substrate in the first region and the second region, and making the surface of the dummy gate flush with the surface of the interlayer dielectric layer;

forming a sacrificial layer on the interlayer dielectric layer located in the second region and the dummy gate located in the second region;

removing the dummy gate located in the first region to form a first opening in the interlayer dielectric layer in the first region;

forming a first metal layer on the surface of the sacrificial layer located in the second region, the surface of the interlayer dielectric layer in the first region, and the first opening;

removing part of the first metal layer by chemical mechanical polishing, and the first metal layer located in the first opening serves as a first grid;

After forming the first gate, the sacrificial layer is removed.

Optionally, the step of forming the sacrificial layer includes: forming a sacrificial layer of oxide or nitride material.

Optionally, the step of forming the sacrificial layer includes: forming a sacrificial layer with a higher density than the interlayer dielectric layer.

Optionally, the step of forming a sacrificial layer includes: forming a sacrificial layer with a thickness in a range of 30-80 angstroms.

Optionally, the step of chemical mechanical polishing includes: the polishing rate of the sacrificial layer is lower than that of the first metal layer.

Optionally, the step of chemical mechanical polishing includes: the polishing rate of the sacrificial layer is not greater than one-twentieth of the polishing rate of the first metal layer.

Optionally, after the step of forming the sacrificial layer and before the step of removing the dummy gate located in the first region, the method further includes: forming a hard mask on the surface of the sacrificial layer; removing the hard mask located in the first region;

The step of removing the dummy gate located in the first region includes: using the remaining hard mask as an etching mask to etch and remove the dummy gate located in the first region.

Optionally, the step of forming a hard mask includes forming a hard mask of titanium nitride material.

Optionally, the step of forming a hard mask includes forming a hard mask with a thickness in a range of 50˜100 angstroms.

Optionally, the step of removing the hard mask located in the first region includes removing the hard mask located in the first region by means of plasma etching.

Optionally, the step of forming the first metal layer includes forming the first metal layer of aluminum material.

Optionally, the step of forming the first metal layer further includes, before forming the first metal layer of aluminum material, forming a work function metal layer on the bottom and sidewalls of the first opening.

Optionally, the step of forming dummy gates on the substrates in the first region and the second region includes forming dummy gates made of polysilicon material.

Optionally, after the step of forming the first gate, further include:

removing the remaining sacrificial layer to expose the dummy gate in the second region;

removing the dummy gate located in the second region to form a second opening in the interlayer dielectric layer located in the second region;

forming a second metal layer in the second opening and on the surface of the interlayer dielectric layer;

The second metal layer on the surface of the interlayer dielectric layer is removed by chemical mechanical polishing, and the second metal layer located in the second opening serves as a second grid.

Optionally, the first region is used to form a PMOS, and the second region is used to form an NMOS; or, the first region is used to form an NMOS, and the second region is used to form a PMOS.

Optionally, the step of removing part of the first metal layer by chemical mechanical polishing further includes: partially removing the sacrificial layer.

Compared with the prior art, the technical solution of the present invention has the following advantages:

Before forming the first metal layer, a sacrificial layer is formed on the surface of the interlayer dielectric layer and the dummy gate located in the second region, so that when the first metal layer is chemically mechanically polished, the chemical mechanical polishing can be prevented from contacting The dummy gate located in the second region of the substrate can reduce the problem of recesses caused by excessive removal of the dummy gate in the second region by chemical mechanical polishing, so that the surface formed by the dummy gate and the interlayer dielectric layer is relatively smooth and has a relatively consistent height. This helps to reduce bridging problems that may occur when the gate is subsequently formed.

Description of drawings

Fig. 1 is the structural representation of CMOS device in the prior art;

2 to 10 are structural schematic diagrams of various steps in an embodiment of the method for forming a gate according to the present invention.

Detailed ways

In order to solve the problem of easy bridging between transistors and other devices, the various steps of the gate-last process are analyzed. When chemical mechanical polishing (CMP) is used to remove some unnecessary metal layers, due to the difference between different materials (by ) There may be a large difference in the grinding rate (RR), which will cause a height difference between different materials after chemical mechanical grinding, which will cause bridging problems.

Specifically, referring to FIG. 1 , manufacturing a CMOS device requires forming gates of a PMOS device and an NMOS device respectively. Taking the metal gate 3 of the PMOS device formed first as an example, when the metal gate 3 of the PMOS device is formed by chemical mechanical polishing, there is still a dummy gate 4 to be removed in the NMOS device at this time.

Although in general, the chemical mechanical polishing of the metal gate 3 of the PMOS device stops when the interlayer dielectric layer 2 is detected, the polishing rate of the dummy gate 4 is obviously faster than that of the metal gate due to chemical mechanical polishing. Therefore, the removal speed of the dummy gate 4 in the NMOS device will be significantly faster than the removal speed of the metal gate 3 in the PMOS device, which will cause the dummy gate 4 of the NMOS device and part of the interlayer around the dummy gate The surface of the dielectric layer 2 is prone to depressions, that is to say, the surface topography in the CMOS device is relatively uneven at this time, and there is an increased height difference between the PMOS device region and the NMOS device region.

This height difference will lead to the fact that when the metal is formed in the NMOS device, since the surface of the NMOS device is lower than the surface of the PMOS device region, the chemical mechanical polishing of the metal layer of the NMOS device will easily stop on the surface of the PMOS device with a relatively higher surface, Metallic material located in recesses in the NMOS device region cannot be ground. These remaining metal materials are likely to cause bridging between the metal gate of the NMOS device and other surrounding devices.

Therefore, in order to solve the above problems, the present invention provides a method for forming a gate, comprising the following steps:

A substrate is provided, so that the substrate has a first region for forming a first device and a second region of a second device; dummy gates are respectively formed on the substrate in the first region and the second region; Form an interlayer dielectric layer on the substrate in the first region and the second region, and make the surface of the dummy gate flush with the surface of the interlayer dielectric layer; Forming a sacrificial layer on the dummy gate in the second region; removing the dummy gate in the first region to form a first opening in the interlayer dielectric layer in the first region; A first metal layer is formed on the surface of the interlayer dielectric layer and in the first opening; part of the first metal layer and part of the sacrificial layer are removed by chemical mechanical grinding, and the first metal layer located in the first opening is used as a first grid.

Through the above steps, before forming the first metal layer, a sacrificial layer is formed on the surface of the interlayer dielectric layer and the dummy gate located in the second region, so that when the first metal layer is chemically mechanically polished, the chemical The mechanical polishing does not contact the dummy gate located in the second region of the substrate, which can reduce the problem of recesses caused by excessive removal of the dummy gate in the second region by chemical mechanical polishing, so that the surface formed by the dummy gate and the interlayer dielectric layer is relatively flat, The height is relatively consistent, which is beneficial to reduce bridging problems that may occur when the gate is subsequently formed.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 2 to FIG. 10 are structural schematic diagrams of each step in an embodiment of the method for forming a gate according to the present invention. It should be noted that, in order to make the drawings more clear and concise, only the substrate is shown in FIG. 2 , and the substrates are omitted in FIG. 3 to FIG. 10 , which should not limit the present invention.

Referring first to FIG. 2 , a substrate 10 is provided, wherein the substrate 10 includes a first region for forming a first device, and a second region for forming a second device.

In this embodiment, the substrate 10 may be a silicon substrate or silicon-on-insulator, but the present invention is not limited thereto.

The first region is a PMOS region for forming a PMOS device, and correspondingly, the second region is an NMOS region for forming an NMOS device.

It should be noted that, in other embodiments of the present invention, the first region may also be an NMOS region for forming an NMOS device, and the corresponding second region is a PMOS region for forming a PMOS device. This is not limited.

In this embodiment, structures such as sidewalls 120 , 220 , gate dielectric layer 210 , and silicide layer 110 are formed around the dummy gate 200 . However, these structures are common structures in the field, and the present invention will not describe them in detail, and at the same time, do not make any limitation thereto.

Please continue to refer to FIG. 2 , dummy gates 200 are respectively formed on the substrates of the NMOS region and the PMOS region.

Specifically, the dummy gate 200 uses polysilicon (poly) as a material, but the present invention is not limited thereto.

After that, an interlayer dielectric layer 100 is formed on the substrate 10, and the surface of the dummy gate 200 is flush with the surface of the interlayer dielectric layer 100 (referred to here as the dummy gate 200 and the The heights of the interlayer dielectric layers 100 are equivalent, and may not be exactly the same), that is to say, the dummy gates 200 are exposed from the interlayer dielectric layer 100 .

In this embodiment, the interlayer dielectric layer 100 may be formed of a material with a higher removal rate in chemical mechanical polishing than the sacrificial layer, that is, the sacrificial layer formed in a subsequent step The removal rate is lower, while the removal rate of the interlayer dielectric layer 100 is higher.

The reason for selecting the interlayer dielectric layer 100 with a relatively higher removal rate is that, in the subsequent process of removing the first metal layer located in the first region (in this embodiment, the PMOS region) by chemical mechanical polishing, the chemical mechanical When the grinding is near the end, the interlayer dielectric layer 100 in the PMOS region will be exposed. At this time, the sacrificial layer with a lower removal rate than the interlayer dielectric layer 100 is beneficial to ensure that the sacrificial layer itself will not be completely removed, thereby causing The effect of protecting the dummy gate in the NMOS region below the sacrificial layer from being exposed.

Specifically, in this embodiment, the interlayer dielectric layer 100 may be formed of a material with a lower density than that of the sacrificial layer. For example, some low-density silicon dioxide materials are used to achieve the above-mentioned purpose of making the sacrificial layer difficult to be completely removed. But the present invention is not limited thereto.

Continuing to refer to FIG. 3 , a sacrificial layer 310 is sequentially formed on the interlayer dielectric layer in the first region and the second region and the dummy gate in the second region, and the sacrificial layer 310 is used in the subsequent chemical mechanical polishing step Protect the dummy gate 200 .

Specifically, in this embodiment, the first gate in the first region is formed first, that is, the sacrificial layer 310 is used to make the first gate in the second region The dummy gate 200 in the region of the NMOS device in this embodiment is not exposed during the chemical mechanical polishing process.

Further, the polishing rate of the sacrificial layer 310 is lower than the polishing rate of the first metal layer, so that when the first gate is formed by chemical mechanical polishing, the polishing is easier to stop on the sacrificial layer 310, and also That is to say, try to make the sacrificial layer 310 difficult to be completely removed, so that the dummy gate 200 located in the second region (the NMOS region in this embodiment) is not exposed.

Specifically, the grinding rate of the sacrificial layer 310 can be made to be one-twentieth of the grinding rate of the first metal layer or lower, which further helps to ensure that the sacrificial layer 310 will not be removed when grinding the first metal layer .

In this embodiment, the sacrificial layer 310 may be a sacrificial layer of oxide or nitride material, for example, the sacrificial layer 310 may be silicon oxide or silicon nitride. The grinding rate of the sacrificial layer 310 of this material is lower than the grinding rate of the first metal layer, and the material of the sacrificial layer 310 and the material of the interlayer dielectric layer 100 (in this embodiment, a lower density Silica material) is relatively close, which is conducive to the subsequent chemical mechanical polishing step. The specific material is not limited in the present invention, and can be selected according to actual conditions.

As mentioned above, the sacrificial layer 310 can be made of a material with higher density than the interlayer dielectric layer 100 . The sacrificial layer 310 with higher density means that the polishing rate is lower than that of the interlayer dielectric layer 100, so that in the subsequent chemical mechanical polishing step, the sacrificial layer 310 is not easily removed, further ensuring that the The dummy gate 200 is not exposed during the chemical mechanical polishing step.

In actual operation, the sacrificial layer 310 with higher density can be formed by chemical vapor deposition, specifically, the density of the formed sacrificial layer 310 can be adjusted by changing the reactive precursors during chemical vapor deposition .

On the one hand, if the thickness of the sacrificial layer 310 is too small, it is difficult to ensure that the dummy gate 200 in the NMOS region is not exposed, so that a good protective effect cannot be achieved; on the other hand, if the thickness of the sacrificial layer 310 is too large, it needs to be removed later. It is cumbersome to further remove the dummy gate 200 in the NMOS region by the sacrificial layer 310 , or it may easily lead to an excessively large height difference between the NMOS region and the PMOS region, which affects the subsequent chemical mechanical polishing. Therefore, in this embodiment, the thickness of the formed sacrificial layer 310 may be in the range of 30-80 angstroms.

However, it should be noted that this value is only used in this embodiment. In actual operation, the thickness of the sacrificial layer 310 should be adjusted according to the actual situation, which is not limited in the present invention.

In this embodiment, a hard mask 320 is further formed on the sacrificial layer 310, and the hard mask 320 is used to protect the dummy gate 200 located in the second area when the dummy gate 200 located in the first area is subsequently etched. The sacrificial layer is not affected by the etch mask.

In this embodiment, titanium nitride is used as a material to form the hard mask 320 , but the present invention is not limited thereto, and other materials such as tantalum nitride can also be used as the material of the hard mask 320 .

Further, in order to make the formed hard mask 320 sufficiently function as the etching mask mentioned above, and at the same time not be too thick to affect the entire manufacturing process, in this embodiment, a hard mask 320 with a thickness in the range of 50-100 angstroms is formed. Hard mask 320 .

Referring to FIG. 4, a photoresist 50 with a pattern is formed on the hard mask 320 in the second region, and then the photoresist 50 with a pattern is used as an etching mask to remove the hard mask 320 in the first region. and a sacrificial layer 310 to expose the dummy gate 200 in the first region.

Specifically, in this embodiment, the hard mask 320 and the sacrificial layer 310 may be removed by plasma etching. For example, a gas containing fluorine or chlorine is used to etch the hard mask 320 made of titanium nitride first, and then a gas containing fluorine is used to etch the sacrificial layer 310 .

In actual operation, the etching method and etchant can be adjusted according to the actual situation and specific materials of the sacrificial layer 310 and the hard mask 320 , which is not limited in the present invention.

Referring to FIG. 5, using the remaining photoresist 50 and the hard mask 320 as an etching mask, the dummy gate 200 located in the first region is removed, and then the first interlayer dielectric layer 100 located in the first region is formed. opening 201 . The first opening 201 is used to fill a metal layer in a subsequent step to form a first gate.

It should be noted that, during the process of etching the dummy gate 200 in the first region, the photoresist 50 may be completely removed, and after the photoresist 50 is removed, the hard mask 320 acts as a second area of the etch mask. The situation shown in FIG. 5 is the situation that the photoresist is not completely removed, and the etching mask of the second region is still the photoresist 50 at this moment.

In this embodiment, before the subsequent formation of the first metal layer, the following steps are further included:

A work function layer (not shown in the figure) is formed in the formed first opening 201, and the work function layer is used to adjust the work function of the entire PMOS device.

However, it should be noted that the present invention does not limit whether the work function layer must be formed. At the same time, the work function layer itself is a prior art, which is not described in detail in the present invention, and the material and formation method of the work function layer are not limited.

Referring to FIG. 6, in the first opening 201, the photoresist 50 and the interlayer dielectric layer 100 in the first region and the second region cover the first metal layer 401, and the first metal layer 401 is used to form the first region The first gate of the PMOS device.

In this embodiment, the first metal layer 401 is an aluminum metal layer. However, the present invention is not limited thereto, for example, other metals such as tungsten can also be used as the material of the first metal layer 401 .

Referring to FIG. 7 , a portion of the first metal layer 401 is removed by chemical mechanical polishing, leaving the first metal layer in the first opening to form the first gate 400 in the PMOS device region.

In this embodiment, after the formation of the first gate 400, the sacrificial layer 310 is partially removed, however, the present invention intends not to expose the dummy gate 200 in the second region, for the sacrificial layer 310 Whether it is partially removed is not limited, and in other embodiments of the present invention, the sacrificial layer 310 may not be removed, or the amount removed is basically negligible.

Since the material of the sacrificial layer 310 is relatively close to the material of the interlayer dielectric layer 100, and the thickness of the sacrificial layer 310 is relatively small (30-80 angstroms in this embodiment), the chemical mechanical polishing In the process, the chemical mechanical polishing can use the sacrificial layer 310 as a polishing stop layer in the NMOS device region where the sacrificial layer 310 is formed, and use the interlayer dielectric layer 100 as the polishing stop layer in the PMOS device region without the sacrificial layer 310. stop layer.

During the chemical mechanical polishing process, due to the barrier of the sacrificial layer 310, the chemical mechanical polishing in this step will not contact the dummy gate 200 in the second region, so the dummy gate 200 and the dummy gate 200 in the prior art are avoided as much as possible. The problem that part of the surrounding interlayer dielectric layer 100 is excessively removed.

After that, the dummy gate in the NMOS device region needs to be removed. In this embodiment, before removing the dummy gate in the NMOS device region, the remaining sacrificial layer 310 is removed to expose the dummy gate 200 in the second region. Since the thickness of the sacrificial layer 310 in this embodiment is in the range of 30-80 angstroms, the sacrificial layer 310 will not be too thick, and thus basically will not affect the progress of this step.

Specifically, in this embodiment, the remaining sacrificial layer 310 may be etched with a fluorine-containing gas, but the present invention is not limited thereto.

Referring to FIG. 8 , the dummy gate 200 located in the second region is removed to form a second opening 202 in the interlayer dielectric layer 100 located in the second region. The second opening 202 is used to form a second gate of the NMOS device.

Referring to FIG. 9 , a second metal layer 402 is formed in the second opening 202 and on the surface of the interlayer dielectric layer 100 in the first region and the second region.

In this embodiment, the second metal layer 402 may be made of the same aluminum as that of the first metal layer 401 . However, the present invention is not limited thereto.

Referring to FIG. 10 , part of the second metal layer 402 is removed by chemical mechanical polishing, leaving the second metal layer 402 in the second opening 202 to form the second gate 403 in the second region. At this time, the chemical mechanical polishing in this step may stop the polishing when the polishing device detects the material of the interlayer dielectric layer 100 . That is to say, in the chemical mechanical polishing step in this step, the interlayer dielectric layer 100 is used as a polishing stop layer.

Since the interlayer dielectric layer 100 located in the first region and the second region are substantially flush with each other, the material of the second metal layer located on the surface of the interlayer dielectric layer 100 in the second region can be completely ground away, basically without In the prior art, the problem of incomplete removal of the metal material due to the depression on the surface of the interlayer dielectric layer 100 occurs, thereby solving the bridging problem that may be caused by the residual metal material on the surface of the interlayer dielectric layer 100 .

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (16)

1. A method for forming a gate, comprising: providing a substrate having a first region for forming a first device and a second region for a second device; forming dummy gates on the substrates of the first region and the second region respectively; forming an interlayer dielectric layer on the substrate in the first region and the second region, and making the surface of the dummy gate flush with the surface of the interlayer dielectric layer; forming a sacrificial layer on the interlayer dielectric layer located in the second region and the dummy gate located in the second region; removing the dummy gate located in the first region to form a first opening in the interlayer dielectric layer in the first region; forming a first metal layer on the surface of the sacrificial layer located in the second region, the surface of the interlayer dielectric layer in the first region, and the first opening; removing part of the first metal layer by chemical mechanical polishing, and the first metal layer located in the first opening serves as a first gate; After forming the first gate, the sacrificial layer is removed. 2. The method for forming a gate according to claim 1, wherein the step of forming a sacrificial layer comprises: forming a sacrificial layer of oxide or nitride material. 3. The method for forming a gate according to claim 1, wherein the step of forming a sacrificial layer comprises: forming a sacrificial layer with a higher density than the interlayer dielectric layer. 4. The method for forming a gate according to claim 1, wherein the step of forming a sacrificial layer comprises: forming a sacrificial layer with a thickness in the range of 30-80 angstroms. 5 . The method for forming a gate according to claim 1 , wherein the step of chemical mechanical polishing comprises: the polishing rate of the sacrificial layer is lower than that of the first metal layer. 6 . The method for forming a gate according to claim 1 , wherein the step of chemical mechanical polishing comprises: the polishing rate of the sacrificial layer is not greater than one-twentieth of the polishing rate of the first metal layer. 7. The method for forming a gate according to claim 1, wherein: After the step of forming the sacrificial layer and before the step of removing the dummy gate located in the first region, the method further includes: forming a hard mask on the surface of the sacrificial layer; removing the hard mask located in the first region; The step of removing the dummy gate located in the first region includes: using the remaining hard mask as an etching mask to etch and remove the dummy gate located in the first region. 8. The method for forming a gate according to claim 7, wherein the step of forming a hard mask comprises forming a hard mask of titanium nitride material. 9. The method for forming a gate according to claim 7 or 8, wherein the step of forming a hard mask comprises forming a hard mask with a thickness in the range of 50-100 angstroms. 10. The method for forming a gate according to claim 7 or 8, wherein the step of removing the hard mask located in the first region comprises removing the hard mask located in the first region by plasma etching. 11. The method for forming a gate according to claim 1, wherein the step of forming the first metal layer comprises forming the first metal layer of aluminum material. 12. The method for forming a gate according to claim 11, wherein the step of forming the first metal layer further comprises, before forming the first metal layer of aluminum material, forming A work function metal layer is formed on the wall. 13 . The method for forming a gate according to claim 1 , wherein the step of forming dummy gates on the substrates in the first region and the second region respectively comprises forming dummy gates of polysilicon material. 14 . 14. The method for forming a gate according to claim 1, further comprising: after the step of forming the first gate: removing the remaining sacrificial layer to expose the dummy gate in the second region; removing the dummy gate located in the second region to form a second opening in the interlayer dielectric layer located in the second region; forming a second metal layer in the second opening and on the surface of the interlayer dielectric layer; The second metal layer on the surface of the interlayer dielectric layer is removed by chemical mechanical polishing, and the second metal layer located in the second opening serves as a second grid. 15. The method for forming a gate according to claim 1, wherein the first region is used to form a PMOS, and the second region is used to form an NMOS; or, the first region is used to form an NMOS , the second region is used to form a PMOS. 16. The method for forming a gate according to claim 1, wherein: The step of removing part of the first metal layer by chemical mechanical polishing further includes: partially removing the sacrificial layer.