CN105446935B - Shared storage concurrent access processing method and device - Google Patents

Abstract

The invention discloses a method for processing concurrent access to shared storage. The method includes: for access queues on each access interface, arbitrarily selecting unfinished storage accesses from any one or more of the access queues, and selecting the storage accesses of the selected storage accesses. There is no bank conflict between them; the selected memory accesses are decoded in parallel and transmitted to their respective banks. Correspondingly, the present invention also discloses a shared storage concurrent access processing device, which can more effectively avoid access conflicts and fully utilize the interface bandwidth, and is basically not affected by the access mode.

Description

Shared storage concurrent access processing method and device

technical field

The present invention relates to the field of digital chips, in particular to a method and device for processing concurrent access to shared storage.

Background technique

At present, most systems on a chip (SOC, System on Chip) have more than one processor and coprocessor, and the main data interaction between these processors is realized through shared storage. With the wide application of multi-core SOCs, the access conflicts and insufficient bandwidth of shared storage have become more and more bottlenecks restricting system performance.

The existing methods for improving the shared memory interface mainly solve the problems of reducing access delay, optimizing cross-boundary access, eliminating unaligned access overhead, simple access conflict avoidance, optimizing the bandwidth and delay of continuous address access, etc. scene optimization.

As shown in Figure 1, it is a common shared storage concurrent access method. Among them, there is only one logically independent memory, and when all four interfaces have memory accesses, only one access can be responded (as shown by the solid line in the figure). In this way, even with 4 independent interfaces, there is only one interface's effective bandwidth.

As shown in Figure 2, it is a shared storage concurrent access method with common conflict avoidance. There are four logically independent logical blocks (Block), but the interface can only access the queue head. When all four interfaces have storage access When it occurs, only accesses without Block conflict can be responded (as shown by the solid line in the figure). In this way, even with 4 independent interfaces, due to the high probability of block collision, the actual effective bandwidth is only 2.7 times that of a single interface.

As shown in Figure 3, it is an ordinary shared storage concurrent access interface return method. The interface from which the access is received is the interface from which the data is returned. Obviously, when there are multiple accesses from the same interface, although these accesses will be accepted by the interface, but at the same time because each interface can only return one data, only those accesses without interface conflict get the actual response. As shown in Figure 3, access0 and access1 enter from interface 0 (Interface0), and access2 and access3 enter from interface 1 (Interface1). Although these accesses will be accepted by the corresponding interfaces, at the same time, each interface can only return one data, so only access0 and access2 got the actual response (solid line means accepted by the interface and got the actual response), access1 and access3 didn't get the actual response (dotted line means accepted by the interface but didn't get the actual response). In this way, even if there are 4 independent interfaces, the actual effective bandwidth is only 2.7 times that of a single interface due to the high probability of interface conflict.

Therefore, it is necessary to propose a new scheme to more effectively avoid access conflicts and make full use of interface bandwidth, solve the problems of access conflicts and insufficient bandwidth of shared storage, and ensure that it is basically not affected by access methods.

SUMMARY OF THE INVENTION

In view of this, the main purpose of the present invention is to provide a shared storage concurrent access processing method and device, which can more effectively avoid access conflicts and utilize interface bandwidth, and solve the access conflicts and bandwidth shortage problems of shared storage.

In order to achieve the above object, the technical scheme of the present invention is achieved in this way:

An embodiment of the present invention provides a method for processing concurrent access to shared storage, including:

For the access queues on each access interface, unfinished storage accesses are arbitrarily selected from any one or more of the access queues, and there is no heap bank conflict between the selected storage accesses;

The selected memory accesses are decoded in parallel and transmitted to their respective banks.

In the above scheme, the method also includes:

Update its transfer status at any time according to the ID of the selected storage access;

The corresponding access interface is notified of the ID of the processed storage access, so that the access interface removes the corresponding storage access from the access queue.

In the above solution, each of the access interfaces corresponds to an access queue containing multiple uncompleted transmissions, and the selected storage access is not greater than the total number of access interfaces.

An embodiment of the present invention also provides a shared storage concurrent access processing device, including: a shared bus, multiple access interfaces, a shared storage access exchange management unit, and a shared memory, wherein,

Shared bus, used to provide read and write channels for storage access from the access source, supports incomplete transfers, and supports out-of-order transfers;

an access interface for accepting the storage access sent through the shared bus, and placing the accepted storage access into an access queue;

The shared storage access exchange management unit includes: an access selection module and a parallel decoding module, wherein,

The access selection module is used to arbitrarily select unfinished storage accesses from any one or more of the access queues for the access queues on each of the access interfaces, and there is no Bank conflict between the selected storage accesses;

a parallel decoding module, used for parallel decoding of the storage access selected by the access selection module, and transmitted to the respective corresponding heap Banks;

The shared memory includes multiple logic blocks, which have no obvious correspondence with the access interface. Each logic block includes multiple banks. The logic blocks refer to logical storage units that provide continuous addresses. Banks are used to Smaller physical memory cells with interleaved rows and columns of addresses.

In the above solution, the shared storage access exchange management unit further includes a transmission state update module;

The access selection module is further configured to send the ID of the selected storage access to the transmission state update module after selecting the storage access;

The transmission state update module is used to update its transmission state at any time according to the ID of the storage access; and inform the corresponding access interface of the ID of the storage access that has been processed;

The access interface is further configured to remove the corresponding storage access from the access queue according to the ID of the processed storage access.

In the above solution, each of the access interfaces corresponds to an access queue containing multiple uncompleted transmissions, and the selected storage access is not greater than the total number of access interfaces.

An embodiment of the present invention also provides a method for processing concurrent access to shared storage, including:

For each feedback data that needs to be returned, select any access interface as its passing interface;

The feedback data and its accompanying information are sent to the access interface, and the accompanying information includes the access ID and the identifier of the passing interface.

In the above solution, any access interface is selected as its pass-through interface, including:

The access interface corresponding to the feedback data is preferentially selected as its pass-through interface;

If there is an access conflict on the access interface corresponding to the feedback data, any access interface that does not currently need to return data is selected as the pass-through interface.

In the above scheme, the method also includes:

The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source through the shared bus according to the accompanying information.

An embodiment of the present invention also provides a shared storage concurrent access processing device, including: a shared bus, multiple access interfaces, a shared storage access exchange management unit, and a shared memory, wherein,

Shared bus, used to provide read and write channels for storage access from the access source, supports incomplete transfers, and supports out-of-order transfers;

The access interface is used to accept the storage access sent through the shared bus, and put the accepted storage access into the access queue; and, according to the accompanying information of the feedback data, pass the feedback data that needs to be returned through the shared bus return to the access source;

The shared storage access exchange management unit includes: an interface selection module, configured to select any one of the access interfaces as its pass-through interface for feedback data of storage access, and send the feedback data and accompanying information to the access interface, the The accompanying information includes the ID of the storage access corresponding to the feedback data and the identifier of the passing interface;

The shared memory includes multiple logical blocks, each logical block includes multiple banks, the logical blocks refer to logical storage units that provide consecutive addresses, and banks are smaller physical storage units used for address row and column interleaving.

In the above scheme, the interface selection module is used to select any one of the access interfaces as its pass-through interface for each feedback data that needs to be returned, including:

For each feedback data that needs to be returned, the access interface corresponding to the feedback data is preferentially selected as its pass-through interface; if the access interface corresponding to the feedback data has an access conflict, any access interface that currently does not need to return data is selected as its pass-through interface interface.

In the present invention, the storage access and selection storage access are accepted regardless of the order, and any interface is selected as the pass-through interface when returning data. In this way, multiple interfaces share the memory in the same chip, improve the storage access bandwidth, and can more effectively avoid access. Conflicts and full use of interface bandwidth, and are basically not affected by access methods.

Description of drawings

1 is a schematic diagram of a common shared storage concurrent access mode;

2 is a schematic diagram of a shared storage concurrent access mode with common conflict avoidance;

Fig. 3 is a kind of schematic diagram of the return mode of a common shared storage concurrent access interface;

4 is a schematic diagram of a shared storage concurrent access mode according to an embodiment of the present invention;

5 is a schematic diagram of a return mode of a shared storage concurrent access interface according to an embodiment of the present invention;

6 is a schematic diagram of the composition and structure of a shared storage concurrent access processing apparatus according to an embodiment of the present invention;

7a-7b are schematic diagrams of shared memory address coding of a shared memory concurrent access processing apparatus according to an embodiment of the present invention;

FIG. 8 is a flowchart of a method for processing concurrent access to shared storage according to an embodiment of the present invention.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

The shared storage concurrent access processing method and device provided by the embodiments of the present invention improve storage access bandwidth by sharing the memory in the same chip through multiple interfaces, can more effectively avoid access conflicts and make full use of interface bandwidth, and is basically free from The impact of access methods.

The specific implementation process of the embodiment of the present invention is described below by taking 4 access interfaces, the memory including 4 logic blocks (blocks) and 16 independent heaps (Banks) as examples. It should be noted that the embodiment of the present invention is also applicable to and not limited to a similar structure with 8 interfaces, 8 Blocks, 32 Banks, etc. The main feature of this similar structure is that it has multiple access interfaces, and blocks and banks are organized at two levels. Shared storage.

As shown in Figure 4, there are 4 logically independent blocks and 16 independent Banks in the memory. When storage access occurs on the 4 interfaces, each access interface corresponds to an access queue with multiple unfinished transfers. In this embodiment of the present invention, the out-of-order function can be used to arbitrarily take storage access from any access queue from four access queues access01 to access04, access11 to access14, access21 to access24, and access31 to access34 of four slave devices, and the selected storage access It is not greater than the total number of access interfaces. The selected access storage is processed in parallel. As long as there is no bank conflict, the access will be responded. It is not necessary to process the storage access according to the order of the access queue or the rule of taking one access for each access queue. In this case, the probability of bank collision is close to 0, and the actual effective bandwidth is about 4 times that of a single interface. For example, as shown in Figure 4, access01, access03, access21, and access34 can be taken simultaneously for parallel processing.

For the interface return of concurrent access, in this embodiment of the present invention, the feedback data can be returned through any access interface, and there is no need to return data according to the "rule of "return from wherever it comes from". As long as there is no data to be returned on the current interface, You can use this interface to return feedback data. Use those interfaces that have no data to return to resolve access conflicts on the interface, and all accesses at any time can get actual responses. In this case, the actual effective bandwidth is 4 times that of a single interface. As shown in Figure 5, there is an access conflict between access0 and access1. When returning data, the original interface Interface0 is not used for the feedback data of access1, but the interface Interface1 that has no data to be returned is used to return its feedback data. When there is an access conflict between access2 and access3, both access2 and access3 have data to be returned. The interface Interface2 is used to return the feedback data of access1, and the interface3 is used to return the feedback data of access3.

As shown in FIG. 6, the structure of the shared memory concurrent access processing device with 4 interfaces mainly includes: a shared bus, 4 access interfaces Slave0-Slave3, a shared memory access switch management unit, and a shared memory.

The shared bus provides a read and write channel for storage access from the access source. It can be of any topology but meets the following main characteristics (Figure 6 is a schematic diagram of the separation of read and write channels, and also supports a bus that integrates read and write channels): The master to the slave device (Slave) is routed according to the address; the slave to the master is routed according to the ID; supports outstanding transmission (outstanding); supports out of order transmission (out of order).

The four access interfaces Slave0~Slave3 are managed uniformly, and the access queue of each access interface in Slave0~Slave3 has 4 positions (WID0&RID0~WID3&RID3), which are used to accept the storage access sent through the shared bus, and will Storage accesses are put into the access queue; in addition, the access interface can also be used to remove the corresponding storage access from the access queue based on the ID of the completed storage access. In addition, it can also be used to return the feedback data to be returned to the access source through the shared bus according to the accompanying information of the feedback data.

The shared storage access exchange management unit includes an access selection (access select) module, a parallel decoding (parallel decoding) module, a transmission state update (transaction state update) module, and an access selection module for each of the access queues on the access interface , arbitrarily select unfinished storage accesses from any one or more access queues, and there is no Bank conflict between the selected storage accesses; the parallel decoding module is used for parallel decoding of the storage accesses selected by the access selection module The access selection module is also used to send the ID of the selected storage access to the transmission state update module after selecting the storage access; the transmission state update module uses According to the ID of the storage access, update its transmission status at any time; and notify the corresponding access interface of the ID of the storage access that has been processed. In addition, an interface selection (date feedback & interface select) module may also be included, for selecting any one of the access interfaces as the pass-through interface for each feedback data, and sending the feedback data and its accompanying information to the access interface an interface, and the accompanying information includes the ID of the storage access corresponding to the feedback data and the identifier of the passing interface.

As shown in Figure 6, the shared memory includes 4 logic blocks Block0-Block3, and each logic block includes four Banks (Bank0-Bank3). The logic blocks refer to logic storage units that provide continuous addresses. Bank is used for Smaller physical memory cells with address row and column interleaving. Each bank is responsible for multiple addresses, that is, the addresses of multiple accesses are located in the same bank. When the access arrives, the access is placed in the corresponding bank according to the accessed address. In practical applications, the shared memory can be organized in two levels, as shown in Figure 7a, including four logical blocks (Blocks) coded according to consecutive addresses, which is convenient for storing data according to functions to avoid conflicts between concurrent accesses; as shown in Figure 7b. As shown, each Block contains four Banks coded according to horizontal addresses, which is convenient for storing data according to statistical characteristics to avoid conflicts between concurrent accesses. In the above device, the word length is 128 bits; the first word is in Bank0, the second word is in Bank1, the third word is in Bank2, the fourth word is in Bank3, and so on. That is, sequential addressing within the block, horizontal addressing between banks, discontinuous addresses within the bank (the arithmetic sequence with a tolerance of 4), and the addresses are interleaved between banks.

Wherein, the interface selection module is configured to select any access interface as the pass-through interface for each feedback data to be returned, including: for each feedback data to be returned, preferentially selecting the access interface corresponding to the feedback data as the pass-through interface interface; if there is an access conflict in the access interface corresponding to the feedback data, any access interface that does not need to return data at present is selected as the pass-through interface.

As shown in FIG. 8 , the apparatus shown in FIG. 6 can implement the shared storage concurrent access processing method according to the embodiment of the present invention, and the method may specifically include the following steps:

Step 801: The access source sends the storage access to each access interface Slave0-Slave3 through the shared bus, judges whether to accept the new multiple storage accesses according to the total depth of the four access queues in Slave0-Slave3, and stores the accepted storage accesses. The access is placed in the access queue;

Among them, each access interface preferentially accepts its corresponding storage access. When the total space of the 4 access queues is insufficient, you can choose to accept or not to accept the new storage access according to any policy arbitration, that is, according to the application characteristics.

Step 802: The access selection module of the shared storage access exchange management unit selects 4 storages without Bank conflict regardless of the sequence from the 32 storage accesses that have been accepted but not completed in the 32 positions of the 4 access queues corresponding to Slave0 to Slave3 respectively. access, and the ID of the selected storage access is given to the transmission status update module of the shared storage access exchange management module;

Among them, the storage access can be arbitrated according to any strategy. The key point is to arbitrarily select one or more storage accesses from 32 positions of the four access queues for parallel processing, but the number of storage accesses selected at the same time is not greater than the logic of the shared memory. number of blocks. In this embodiment of the present invention, the number of selected storage accesses may not exceed 4 (the total number of interfaces).

Step 803: The parallel decoding module of the shared storage access exchange management unit decodes the selected non-conflict storage access in parallel, and sends them to the respective corresponding Banks;

Step 804: The transmission status update module updates the transmission status (transmission progress) of each storage access based on the ID of each storage access, and notifies the access interface to remove the storage access from the access queue if the transmission is just completed.

Step 805: The interface selection module of the shared storage access exchange management unit selects an access interface to be passed for each feedback data that needs to be returned.

Here, for each feedback data that needs to be returned, any access interface is selected as its passing interface. The access interface corresponding to the feedback data is preferentially selected as the pass-through interface. For other feedback data with interface conflicts, any access interface that does not need to return data can be selected as the pass-through interface. The interface selection policy can be flexibly set, which is not limited in the embodiment of the present invention.

Step 806: the interface selection module of the shared storage access exchange management unit sends the feedback data and its accompanying information to the access interface;

Among them, the accompanying information mainly includes the ID of the storage access corresponding to the feedback data, and the access interface to which the feedback data is to go, that is, the identifier of the passing interface.

Step 807: The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source through the shared bus according to the accompanying information.

Among them, each of Slave0 to Slave3 selects whether to accept the feedback data according to the accompanying information of the feedback data. If the identification of the interface in the accompanying information is the same as its own identification, then accept it, and store the access ID in the accompanying information according to the ID. The feedback data is returned to the corresponding access source through the shared bus; otherwise, the feedback data is not accepted, and subsequent data return processing is not performed.

For an access that does not need to return data, such as a read access, the process ends at step 804; for an access that needs to return feedback data, such as a write access, the process ends at 807.

Among the above steps, step 802 and step 805 are the main reasons for the improvement of the shared storage access bandwidth; step 801 and step 807 are the improvement, innovation and flexible application of the existing on-chip data bus protocol, and are auxiliary conditions for the effective use of this method. .

Compared with various existing methods and devices for improving the bandwidth of shared storage interfaces, the method and device of the present invention have the following characteristics:

1) In the storage access arbitration of each interface, combined with the outstanding function, schedule and respond out of order, which minimizes the Bank conflict during multi-port storage access and improves the entry and exit of static random access memory (SRAM, StaticRAM). Egress bandwidth.

2) When multiple concurrent accesses occur, each access interface does not work independently, but manages the queue resources in a unified manner, which eliminates the problem that the queue of the access interface with the incoming access is full and other access interfaces cannot accept new access when there is space. Bandwidth loss.

3) When multiple data are returned, abandon the original way of going back and forth. The returned data can be returned through any interface, and the return delay of each interface is the same. The return data of the bus is routed according to the ID, which will not have any ill effects, thus making full use of the egress bandwidth provided by the interface.

Assume that SRAM has only one Block and one access interface. Obviously, this method has nothing to do with the address pattern during access. Assuming that the bus bandwidth of a single interface is 1 (normalized unit), the access bandwidth of shared storage under this scheme is exactly 1 .

1) Four independent bus interfaces and four independent Blocks, using the common method, the four concurrent access sources will appear in the following situations:

The addresses of 4 concurrent accesses fall in exactly 4 different Blocks, and the bandwidth is 4*1=4.

The addresses of the four concurrent accesses fall into three different blocks, and the bandwidth is 3*1=3.

The addresses of 4 concurrent accesses fall in two different blocks, and the bandwidth is 2*1=2.

4 concurrently accessed addresses fall into the same block, and the bandwidth is 1.

Assuming that the access addresses of each access source are independent of each other and the access addresses are evenly distributed, the total number of access situations is:

N=4 ⁴ =256=N ₁ +N ₂ +N ₃ +N ₄

The probability that the addresses of 4 concurrent accesses fall in exactly 4 different Blocks is: N4/N=9.38%.

The probability that four concurrently accessed addresses fall into three different Blocks is: N3/N=56.25%.

The probability that four concurrently accessed addresses fall into two different Blocks is: N2/N=32.81%.

The probability that four concurrently accessed addresses fall into the same Block is: N1/N=1.56%.

Thus, the average bandwidth under this scheme is: B=B1*P1+B2*P2+B2*P2+B2*P2=4*9.38%+3*56.25%+2*32.81%+1*1.56%=2.73.

2) Using the apparatus and method provided by the embodiments of the present invention, it is assumed that the shared bus can support up to 16 outstanding out-of-order functions, that is, each access source supports an average of 4 outstanding out-of-order functions; the memory is divided into 4 logically independent Each Block is divided into 4 Banks with addresses interleaved. Under this scheme, 4 concurrent access sources selected from 16 IDs will have the following situations:

The addresses of the 4 concurrent accesses just fall into four different Banks, and the bandwidth is 4*1G=4.

The addresses of 4 concurrent accesses fall into three different Banks, and the bandwidth is 3*1=3.

The addresses of 4 concurrent accesses fall into two different Banks, and the bandwidth is 2*1=2.

4 concurrently accessed addresses fall into the same bank with a bandwidth of 1.

Assuming that the access addresses of each access source are independent of each other and the access addresses are evenly distributed, the total number of access situations is:

N=N ₁ +N ₂ +N ₃ +N ₄ =16 ¹⁶ =18446744073709551616

N ₄ =NN ₁ -N ₂ -N ₃ =18446744049705622576

The probability that the addresses of 4 concurrent accesses fall in exactly 4 different blocks is: N4/N=99.99%.

The probability that four concurrently accessed addresses fall into three different blocks is: N3/N=0.001%.

The probability that four concurrently accessed addresses fall into two different blocks is: N2/N=0.00%.

The probability that four concurrently accessed addresses fall into the same block is: N1/N=0.00.

Thus, the average bandwidth under this scheme is: B=B1*P1+B2*P2+B2*P2+B2*P2=4*99.99%+3*0.01%+2*0.00%+1*0.00%=4.

Therefore, compared with the common four independent bus interfaces with four independent Blocks, the benefits brought by the method and device of the embodiments of the present invention are increased by 46.5% compared with the common method.

Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the present invention can be implemented by a general-purpose computing device, and they can be centralized on a single computing device or distributed in a network composed of multiple computing devices Alternatively, they may be implemented in program code executable by a computing device, such that they may be stored in a storage device and executed by the computing device, and in some cases, in a different order than here The steps shown or described are performed either by fabricating them separately into individual integrated circuit modules, or by fabricating multiple modules or steps of them into a single integrated circuit module. As such, the present invention is not limited to any particular combination of hardware and software.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (11)

1. a shared storage concurrent access processing method, is characterized in that, described method comprises: For the access queues on each access interface, unfinished storage accesses are arbitrarily selected from any one or more of the access queues, and there is no heap bank conflict between the selected storage accesses; The selected memory accesses are decoded in parallel and transmitted to their respective banks. 2. The method according to claim 1, wherein the method further comprises: Update its transfer status at any time according to the ID of the selected storage access; The corresponding access interface is notified of the ID of the processed storage access, so that the access interface removes the corresponding storage access from the access queue. 3. The method according to any one of claims 1 to 2, wherein each of the access interfaces corresponds to an access queue containing multiple incomplete transfers, and the selected storage access is not greater than the total number of access interfaces. 4. A shared storage concurrent access processing device, wherein the device comprises: a shared bus, a plurality of access interfaces, a shared storage access exchange management unit and a shared memory, wherein, Shared bus, used to provide read and write channels for storage access from the access source, supports incomplete transfers, and supports out-of-order transfers; an access interface for accepting the storage access sent through the shared bus, and placing the accepted storage access into an access queue; The shared storage access exchange management unit includes: an access selection module and a parallel decoding module, wherein, The access selection module is used to arbitrarily select unfinished storage accesses from any one or more of the access queues for the access queues on each of the access interfaces, and there is no Bank conflict between the selected storage accesses; a parallel decoding module, used for parallel decoding of the storage access selected by the access selection module, and transmitted to the respective corresponding heap Banks; The shared memory includes multiple logic blocks, which have no obvious correspondence with the access interface. Each logic block includes multiple banks. The logic blocks refer to logical storage units that provide continuous addresses. Banks are used to Smaller physical memory cells with interleaved rows and columns of addresses. 5. The shared storage concurrent access processing device according to claim 4, wherein the shared storage access exchange management unit further comprises a transmission state update module; The access selection module is further configured to send the ID of the selected storage access to the transmission state update module after selecting the storage access; The transmission state update module is used to update its transmission state at any time according to the ID of the storage access; and inform the corresponding access interface of the ID of the storage access that has been processed; The access interface is further configured to remove the corresponding storage access from the access queue according to the ID of the processed storage access. 6. The shared storage concurrent access processing device according to any one of claims 4 to 5, wherein each of the access interfaces corresponds to an access queue containing multiple unfinished transmissions, and the selected storage access is not greater than The total number of access interfaces. 7. A shared storage concurrent access processing method, wherein the method comprises: For each feedback data that needs to be returned, select any access interface as its passing interface; The feedback data and its accompanying information are sent to the access interface, and the accompanying information includes the access ID and the identifier of the passing interface. 8. The method according to claim 7, characterized in that, selecting any one access interface as its through interface, comprising: The access interface corresponding to the feedback data is preferentially selected as its pass-through interface; If there is an access conflict on the access interface corresponding to the feedback data, any access interface that does not currently need to return data is selected as the pass-through interface. 9. The method according to claim 7, wherein the method further comprises: The access interface receives the feedback data and its accompanying information, and returns the feedback data to the access source through the shared bus according to the accompanying information. 10. A shared storage concurrent access processing device, characterized in that the device comprises: a shared bus, a plurality of access interfaces, a shared storage access exchange management unit and a shared memory, wherein, Shared bus, used to provide read and write channels for storage access from the access source, supports incomplete transfers, and supports out-of-order transfers; The access interface is used to accept the storage access sent through the shared bus, and put the accepted storage access into the access queue; and, according to the accompanying information of the feedback data, pass the feedback data that needs to be returned through the shared bus return to the access source; The shared storage access exchange management unit includes: an interface selection module, configured to select any one of the access interfaces as its pass-through interface for feedback data of storage access, and send the feedback data and accompanying information to the access interface, the The accompanying information includes the ID of the storage access corresponding to the feedback data and the identifier of the passing interface; The shared memory includes multiple logical blocks, each logical block includes multiple banks, the logical blocks refer to logical storage units that provide consecutive addresses, and banks are smaller physical storage units used for address row and column interleaving. 11. The shared storage concurrent access processing device according to claim 10, wherein the interface selection module is used to select any one of the access interfaces as its pass-through interface for each feedback data that needs to be returned, comprising: For each feedback data that needs to be returned, the access interface corresponding to the feedback data is preferentially selected as its pass-through interface; if the access interface corresponding to the feedback data has an access conflict, any access interface that currently does not need to return data is selected as its pass-through interface interface.