CN105446135A - Self-adaptive calibration sampling direct current offset FPGA and intelligent control device - Google Patents

Abstract

The present invention provides a kind of FPGA of self-adaptive calibration sampling DC offset, comprises first, second, the 3rd computing unit and logic shifter; The output end of the third arithmetic unit is connected to the first input end of the third arithmetic unit, the second input end is connected to the output end of the logic shifter, and the output end is connected to the first input end of the second arithmetic unit; the second arithmetic unit is an addition operation The second input terminal is connected to the ADC, and the output terminal is connected to the input terminal of the logic shifter; the third arithmetic unit is a subtraction operator, the second input terminal is connected to the ADC, and the output terminal is connected to the external DSP chip; the logic The shifter realizes the binary number shift through the offset arrangement of the data connection, and the number of bits shifted by the binary number is determined by the sampling frequency of the ADC. The implementation of the present invention can self-adaptively calibrate the DC bias of the sampling result, save time and effort, have scalability and utilize industrial batch production.

Description

FPGA and intelligent control device for self-adaptive calibration sampling DC bias

technical field

The invention relates to the technical field of intelligent control of power system devices, in particular to an FPGA and an intelligent control device for self-adaptive calibration and sampling DC bias.

Background technique

Power system intelligent control devices (such as power quality control devices, harmonic control devices) need to configure sampling equipment to sample target power parameters and output power parameters as the basis and source of control algorithms. However, the electrical energy parameter is usually a high-level voltage of several hundred volts or even 10,000 volts, but the voltage level that the intelligent control device can directly handle is generally about 5 volts to 10 volts.

Therefore, as shown in Figure 1, the original electric energy parameter signal (that is, the high-voltage signal) needs to be converted into a low-voltage sampling signal by one or more stages of PT/CT, and then converted into an ADC (digital-to-analog converter) by a Hall measuring element. Sampling the voltage signal that the chip or board can handle. Under the control of the FPGA chip, the ADC sampling chip completes the sampling process, and delivers the sampled voltage signal to the FPGA chip, which is further output to the core processor DSP of the intelligent control device for calculation.

During the above conversion and sampling process, if the power supply voltage supply of the Hall measuring element is unbalanced or the reference voltage of the ADC chip is unbalanced, a DC bias will appear in the sampling result. Once the DC bias is superimposed on the power frequency 50Hz of the power system, it will have a very adverse impact on the subsequent control algorithm, such as the phase deviation of zero-crossing detection, the offset of RMS calculation and the spectrum distribution of harmonic component calculation errors and so on.

In order to solve the above-mentioned problems existing in the conversion and sampling process, a standard signal source is usually used for calibration. The method is to use a signal source to transmit a standard power frequency voltage signal, and then statistically analyze the final digitized signal, and after extracting the DC component, manually adjust the power supply voltage balance of the sampling device and the reference voltage balance of the ADC chip, or In the digitized signal, the DC correction coefficient calculated by calibration is subtracted from the original sampling value by the digital correction coefficient to obtain the sampling result without DC bias, but the disadvantages of this method are: 1. A lot of manual intervention is time-consuming and labor-intensive; second, it does not have scalability, which is not conducive to industrial mass production.

Contents of the invention

The technical problem to be solved by the embodiments of the present invention is to provide an FPGA and an intelligent control device that can self-adaptively calibrate the sampling DC bias, which can self-adaptively calibrate the DC bias of the sampling results, save time and effort, have scalability and utilize industrial batch Production.

In order to solve the above technical problems, an embodiment of the present invention provides an FPGA for adaptively calibrating the sampling DC bias, which cooperates with the ADC sampling chip, and the FPGA includes a first arithmetic unit, a second arithmetic unit, and a third arithmetic unit and logical shifters; where,

The first computing unit, the second computing unit and the third computing unit each have two input terminals and one output terminal;

The first computing unit is a subtraction computing unit, and its first input terminal is connected to the output terminal of the second computing unit and the first input terminal of the third computing unit, and the second input terminal is connected to the logic displacement The output end of the device is connected, and the output end is connected with the first input end of the second arithmetic unit;

The second arithmetic unit is an addition unit, its second input terminal is connected with the ADC sampling chip, and its output terminal is connected with the input terminal of the logic shifter;

The third arithmetic unit is a subtraction unit, its second input terminal is connected with the ADC sampling chip, and its output terminal is connected with an external DSP chip;

The logic shifter realizes the binary number shift through the offset arrangement of the data connection; wherein, the number of shifted bits of the binary number is determined by the sampling frequency of the ADC sampling chip.

Wherein, when the sampling frequency of the ADC sampling chip is 20KHz, the logic shifter can realize the right shift of 16-bit binary numbers.

Wherein, described FPGA also comprises register, and described register is positioned between the output end of described second arithmetic unit and the first input end of described third arithmetic unit, also with the first input end of described first arithmetic unit and the input terminals of the logic shifter are connected.

An embodiment of the present invention also provides an intelligent control device, which includes the aforementioned FPGA.

Implementing the embodiment of the present invention has the following beneficial effects:

In the embodiment of the present invention, since the binary number of the logic shifter in the FPGA is determined by the sampling frequency of the ADC sampling chip, it can be simulated by the first arithmetic unit, the second arithmetic unit, the third arithmetic unit and the logic shifter. The ADC sampling chip is DC biased and self-adaptively calibrated, so it saves time and effort, is scalable and utilizes industrial mass production.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those of ordinary skill in the art, obtaining other drawings based on these drawings still belongs to the scope of the present invention without any creative effort.

Fig. 1 is the structural representation of the logical design of the FPGA of self-adaptive calibration sampling DC bias in the prior art;

FIG. 2 is a schematic structural diagram of the logic design of the FPGA for adaptively calibrating sampling DC bias provided by Embodiment 1 of the present invention;

FIG. 3 is an application scene diagram of DC offset extraction in an FPGA for adaptively calibrating and sampling DC offset provided by Embodiment 1 of the present invention;

FIG. 4 is an application scene diagram of DC offset calibration in an FPGA for adaptively calibrating sampling DC offset provided by Embodiment 1 of the present invention;

In the figure, 1-first computing unit, 2-second computing unit, 3-third computing unit, 4-logic shifter.

detailed description

In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

The inventors found that during the conversion and sampling process of the intelligent control device, the hardware computing capability of the FPGA can be used to eliminate the DC bias of the ADC sampling result before it is transmitted to the DSP. Therefore, it is proposed to construct a circuit equivalent to a low-pass digital filter on the FPGA to extract the DC component, perform filtering at a certain cut-off frequency, and obtain a filtering result that meets the design conditions of the power system, and then proceed to the next step of calibration.

The principle of the low-pass filter of this circuit is to perform iterative calculation of the formula (1) on the numerical sequence x input by the ADC sampling result to obtain the sequence y of the DC component:

(1)

In formula (1), is the filter coefficient, which is related to the cut-off frequency The relationship is: ;in, and are the sampling period and sampling frequency of the ADC sampling chip, respectively.

After the DC component y is obtained, use the formula (2) to do a subtraction to obtain the AC component z in the input value sequence x of the ADC sampling result, that is, to obtain the sampling result without DC bias:

(2)

Due to filter coefficient is a decimal, after being converted into an integer, the precision of the sampling result can be determined, and according to the precision of the sampling result, the calculation capability of the FPGA is used to realize the DC bias adaptive calibration.

Sampling frequency of ADC sampling chip =20KHz, sampling period =0.5ms as an example, design the cutoff frequency =0.1Hz, get the filter coefficient ;

filter coefficient needs to be first approximated into an integer as , by the transformed filter coefficient It can be seen that the precision of the ADC sampling chip is 16 bits;

Therefore, formula (1) can be transformed into formula (3):

(3)

And further rewrite formula (3) into calculation formula (4) that can be expressed by FPGA hardware calculation:

(4)

In formula (4), the operator "+" means unsigned addition, which can be realized by the arithmetic unit ADDER in the hardware circuit; the operator "-" means unsigned subtraction, which can be realized by the arithmetic unit ADDER in the hardware circuit; The symbol ">" means binary right shift, which is realized through the offset arrangement of the data connection in the hardware circuit.

In summary, as shown in Figure 2, in Embodiment 1 of the present invention, the inventor provides an FPGA for adaptively calibrating sampling DC bias, which cooperates with an ADC sampling chip (not shown), and the FPGA includes The first computing unit 1, the second computing unit 2, the third computing unit 3 and the logic shifter 4; wherein,

The first computing unit 1, the second computing unit 2 and the third computing unit 3 each have two input terminals and one output terminal;

The first computing unit 1 is a subtracting computing unit, its first input terminal is connected with the output terminal of the second computing unit 2 and the first input terminal of the third computing unit 3, and the second input terminal is connected with the output terminal of the logic shifter 4 connected, the output end is connected to the first input end of the second arithmetic unit 2;

The second computing unit 2 is an addition computing unit, its second input terminal is connected with the ADC sampling chip, and the output terminal is connected with the input terminal of the logic shifter 4;

The third arithmetic unit 3 is a subtraction unit, the second input end of which is connected to the ADC sampling chip, and the output end is connected to an external DSP chip (not shown);

The logic shifter 4 realizes the binary number shift through the offset arrangement of the data connection; wherein, the number of bits shifted by the binary number is determined by the sampling frequency of the ADC sampling chip.

It should be noted that the FPGA build cutoff frequency According to the actual sampling frequency of the ADC sampling chip Design, when the actual sampling frequency of the ADC sampling chip is a fixed value, the cutoff frequency constructed by the FPGA is also a fixed value, so that the filter coefficient can be obtained , further deduce the accuracy of the ADC sampling result, and the number of digits shifted by the logic shifter 4 binary number is determined by the accuracy of the ADC sampling result, so the logic shifter 4 binary number displacement is determined by the sampling frequency of the ADC sampling chip.

Sampling frequency of ADC sampling chip =20KHz, sampling period =0.5ms as an example, logic shifter 4 can realize right shift of 16-bit binary number.

Furthermore, the FPGA also includes a register 5, which is located between the output terminal of the second operator 2 and the first input terminal of the third operator 3, and is also connected to the first input terminal of the first operator 1 and the logical displacement The input terminals of device 4 are connected.

As shown in Fig. 3 and Fig. 4, the application scenario of the FPGA with adaptive calibration sampling DC bias in Embodiment 1 of the present invention is further described:

In Figure 3, the intermediate result t of the DC component calculation is saved by the register mean_reg, and the operator Add0 completes the subtraction operation in formula (4), and the calculation is , and send the calculation result to the operator Add1 as the first input; the data x input by the ADC sampling chip enters the operation circuit from the sample port as an input of the operator Add1; the operator Add1 completes the plus sign in formula (4) operator, calculated , the result is transferred to the register mean_reg to complete the update of the intermediate result t.

In Figure 4, after the extraction of the DC component y is completed, the result after calibration It can be obtained by performing another mathematical operation on the basis of the DC component, and the output is completed through the port acresult.

Compared with Embodiment 1 of the present invention, Embodiment 2 of the present invention provides an intelligent control device, which includes the FPGA for adaptively calibrating and sampling DC bias in Embodiment 1 of the present invention, and has the same characteristics as in Embodiment 1 of the present invention. The structure and connection relationship of the FPGA for adaptively calibrating the sampling DC bias are the same, so details will not be repeated here.

Implementing the embodiment of the present invention has the following beneficial effects:

In the embodiment of the present invention, since the binary number of the logic shifter in the FPGA is determined by the sampling frequency of the ADC sampling chip, it can be simulated by the first arithmetic unit, the second arithmetic unit, the third arithmetic unit and the logic shifter. The ADC sampling chip is DC biased and self-adaptively calibrated, so it saves time and effort, is scalable and utilizes industrial mass production.

The above disclosure is only a preferred embodiment of the present invention, which certainly cannot limit the scope of rights of the present invention. Therefore, equivalent changes made according to the claims of the present invention still fall within the scope of the present invention.

Claims (4)

1. An FPGA for adaptive calibration sampling DC bias, characterized in that it cooperates with an ADC sampling chip, and the FPGA includes a first computing unit (1), a second computing unit (2), and a third computing unit (3), and logic shifter (4); where, The first computing unit (1), the second computing unit (2) and the third computing unit (3) each have two input terminals and one output terminal; The first computing unit (1) is a subtracting computing unit, and its first input terminal is connected to the output terminal of the second computing unit (2) and the first input terminal of the third computing unit (3), The second input terminal is connected to the output terminal of the logic shifter (4), and the output terminal is connected to the first input terminal of the second arithmetic unit (2); The second arithmetic unit (2) is an adder, its second input terminal is connected to the ADC sampling chip, and its output terminal is connected to the input terminal of the logic shifter (4); The third computing unit (3) is a subtracting computing unit, its second input terminal is connected to the ADC sampling chip, and its output terminal is connected to an external DSP chip; The logic shifter (4) realizes the binary number shift through the offset arrangement of the data connection; wherein, the number of shifted bits of the binary number is determined by the sampling frequency of the ADC sampling chip. 2. The FPGA according to claim 1, characterized in that, when the sampling frequency of the ADC sampling chip is 20KHz, the logic shifter (4) can realize the right shift of 16-bit binary numbers. 3. FPGA as claimed in claim 1, is characterized in that, described FPGA also comprises register (5), and described register (5) is positioned at the output end of described second operator (2) and described third operation Between the first input terminals of the device (3), it is also connected to the first input terminal of the first arithmetic unit (1) and the input terminal of the logic shifter (4). 4. An intelligent control device, characterized in that it comprises the FPGA according to any one of claims 1 to 3.