CN105429001B - Si/Ge superlattices quantum cascade laser and preparation method thereof - Google Patents

Abstract

The invention discloses a kind of Si/Ge superlattices quantum cascade laser and preparation method thereof, which successively includes silicon substrate, Si from the bottom up_0.5Ge_0.5Buffer layer, silicon and germanium super crystal lattice and SiO₂, at the top of silicon and germanium super crystal lattice and Si_0.5Ge_0.5Aluminium electrode, Si are deposited on buffer layer_0.5Ge_0.5Buffer layer with a thickness of 300nm, the Si_0.5Ge_0.5The germanium intergrowth of silicon and 5nm that buffer layer is 5nm forms silicon and germanium super crystal lattice structure, the Si_0.5Ge_0.5The SiGe ratio of buffer layer is 1: 1.The present invention can either CMOS technique compatible, and can be realized demand of the germanium light source to different wavelengths of light, and photoelectric conversion efficiency with higher, photostability, the processing is simple, conveniently, to realize that on piece light source provides a specific structure and embodiment.

Description

Si/Ge superlattice quantum cascade laser and its fabrication method

technical field

The invention relates to the field of semiconductor optoelectronics, in particular to a Si/Ge superlattice quantum cascade laser and a preparation method thereof.

Background technique

As technical requirements increase day by day, the limits of microfabrication of information processing hardware begin to emerge, hampering the ever-increasing development of technology. Over the past few decades, microelectronics technology has been advancing in accordance with Moore's Law. The most notable feature of progress is that the process size is getting smaller and smaller, the integration level is getting higher and higher, and the cost is getting lower and lower. However, as the size of the microelectronics process advances to the nanoscale, the bottleneck brought by various physical effects is becoming more and more obvious. To break through the bottleneck, the researchers focused on the field of combining microelectronics with optoelectronics, which is called optoelectronic integration (OEIC).

With the unremitting efforts of semiconductor giants such as Intel and IBM, many key devices of silicon optoelectronic technology have been realized on the integrated circuit platform, including breakthroughs in high-speed silicon optical modulators, detectors and waveguide components. However, since silicon is an indirect bandgap material, it is difficult to achieve direct light emission, so the on-chip light source has not been realized, which is the biggest problem that silicon photonics technology has always faced.

Silicon-based optical communication and optoelectronic integration technologies urgently require high-efficiency integrated laser light sources at low cost. So far, lasers on silicon chips have relied on III-V materials grown or bonded to silicon wafers. This creates stability issues and is not conducive to industrial mass production and manufacturing. III-V lasers epitaxial on silicon wafers are limited in lifetime and are quite complex to manufacture. When bonding III-V lasers to silicon wafers are limited due to mismatch issues between silicon and III-V materials. Furthermore, the yield of III-V lasers is quite low relative to silicon CMOS technology.

SUMMARY OF THE INVENTION

In order to solve the above problems, the present invention provides a Si/Ge superlattice quantum cascade laser and a preparation method thereof, which are not only compatible with CMOS technology, but also can meet the requirements of germanium light sources for light of different wavelengths, and have higher optoelectronic properties. Conversion efficiency, light stability, simple and convenient processing, provide a specific structure and implementation scheme for realizing on-chip light sources.

To achieve the above object, the technical scheme adopted in the present invention is:

A Si/Ge superlattice quantum cascade laser, from bottom to top, comprises a silicon substrate, a Si _0.5 Ge _0.5 buffer layer, a silicon germanium superlattice and SiO ₂ , a silicon germanium superlattice and SiO ₂ . Aluminum electrodes are deposited symmetrically, respectively.

The present invention also provides a preparation method of the above-mentioned Si/Ge superlattice quantum cascade laser, comprising the following steps:

A Si _0.5 Ge _0.5 buffer layer with a thickness of 300 nm was grown on a silicon substrate by low molecular beam epitaxy at S1 and 420°C;

Under the conditions of S2 and 420℃, a Ge material with a thickness of 5nm was grown on the obtained Si _0.5 Ge _0.5 buffer layer by low temperature molecular beam epitaxy;

At S3 and 420°C, a Si material with a thickness of 5 nm was grown on the obtained Ge material by low temperature molecular beam epitaxy;

Under the conditions of S4 and 520℃, a Ge material with a thickness of 5nm was grown on the obtained Si material by low temperature molecular beam epitaxy;

S5, repeating steps S3 and S4 to obtain 10-30 layers of Si/Ge;

S6, under the temperature condition of 900°C, grow a layer of SiO ₂ larger than 150 nm on the structure obtained in step S5 by wet oxygen oxidation;

S7, depositing aluminum electrodes on both sides of the obtained Si/Ge and SiO ₂ by a metal evaporation process to obtain a Si/Ge superlattice quantum cascade laser.

Wherein, the silicon germanium buffer layer is a silicon germanium superlattice structure formed by alternating growth of 5 nm silicon and 5 nm germanium.

Wherein, the Si _0.5 Ge _0.5 buffer layer has a silicon germanium ratio of 1:1.

Wherein, the aluminum electrodes are titanium and aluminum in order from bottom to top, and the process conditions are that the thickness of the titanium layer is 20 nm, and the growth rate is The thickness of the aluminum layer is 130 nm, and the growth rate within 10 nm is The growth rate within 10nm to 130nm is

The present invention has the following beneficial effects:

It can not only be compatible with CMOS technology, but also meet the requirements of germanium light sources for light of different wavelengths, and has high photoelectric conversion efficiency, light stability, simple and convenient processing, and provides a specific structure and implementation scheme for realizing on-chip light sources.

Description of drawings

FIG. 1 is a processing meaning diagram of step S1 in an embodiment of the present invention.

FIG. 2 is a schematic view of the processing of step S2 in the embodiment of the present invention.

FIG. 3 is a schematic view of the processing of step S3 in the embodiment of the present invention.

FIG. 4 is a silicon germanium superlattice structure in an embodiment of the present invention.

FIG. 5 is a schematic view of the processing of step S5 in the embodiment of the present invention.

FIG. 6 is a schematic view of the processing of step S6 in the embodiment of the present invention.

FIG. 7 is a schematic view of the processing of step S7 in the embodiment of the present invention.

Detailed ways

In order to make the objects and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

The embodiment of the present invention provides a Si/Ge superlattice quantum cascade laser, which includes a silicon substrate, a Si _0.5 Ge _0.5 buffer layer, a silicon germanium superlattice and SiO ₂ , a silicon germanium superlattice, in order from bottom to top. and SiO ₂ , and aluminum electrodes are deposited symmetrically on both sides, respectively.

As shown in Figures 1-7, an embodiment of the present invention also provides a preparation method of a Si/Ge superlattice quantum cascade laser, including the following steps:

At S1 and 420°C, a Si 0.5 Ge 0.5 buffer layer with a thickness of 300 nm is grown on a silicon substrate by low molecular beam epitaxy; the Si _0.5 Ge _0.5 buffer layer is 5 nm silicon and 5 nm germanium alternately grown to form silicon germanium Superlattice structure with a silicon germanium ratio of 1:1.

Under the conditions of S2 and 420℃, a Ge material with a thickness of 5nm was grown on the obtained Si _0.5 Ge _0.5 buffer layer by low temperature molecular beam epitaxy;

At S3 and 520°C, a Si material with a thickness of 5 nm was grown on the obtained Ge material by a low temperature molecular beam epitaxy method;

Under the temperature conditions of S4 and 420 °C, a Ge material with a thickness of 5 nm is grown on the obtained Si material by a low temperature molecular beam epitaxy method;

S5, repeating steps S3 and S4 to obtain 10-30 layers of Si/Ge;

S6, under the temperature condition of 900°C, grow a layer of SiO ₂ larger than 150 nm on the structure obtained in step S5 by wet oxygen oxidation;

S7, depositing aluminum electrodes on both sides of the obtained Si/Ge and SiO ₂ by a metal evaporation process to obtain a Si/Ge superlattice quantum cascade laser. The aluminum electrodes are titanium and aluminum in order from bottom to top, and the process conditions are that the thickness of the titanium layer is 20 nm, and the growth rate is The thickness of the aluminum layer is 130 nm, and the growth rate within 10 nm is The growth rate within 10nm to 130nm is

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be It is regarded as the protection scope of the present invention.

Claims (5)

1. a kind of preparation method of Si/Ge superlattices quantum cascade laser, which comprises the following steps:

Under the conditions of S1,420 DEG C of temperature, pass through the low molecule beam epitaxy methods Si that growth thickness is 300nm on a silicon substrate_0.5Ge_0.5 Buffer layer；

Under the conditions of S2,420 DEG C of temperature, by low temperature molecular beam epitaxy method in resulting Si_0.5Ge_0.5Growth thickness is on buffer layer The Ge material of 5nm；

Under the conditions of S3,420 DEG C of temperature, by low temperature molecular beam epitaxy method on resulting Ge material growth thickness be 5nm Si Material；

Under the conditions of S4,520 DEG C of temperature, by low temperature molecular beam epitaxy method on resulting Si material growth thickness be 5nm Ge Material；

S5, step S3 and step S4 is repeated, obtains 10-30 layers of Si/Ge；

Under the conditions of S6,900 DEG C of temperature, one layer is grown in the resulting structure of step S5 by wet-oxygen oxidation greater than 150nm's SiO₂；

S7, by evaporation of metal technique at the top of resulting silicon and germanium super crystal lattice and Si_0.5Ge_0.5Aluminium electrode is deposited on buffer layer, is obtained Si/Ge superlattices quantum cascade laser.

2. the preparation method of Si/Ge superlattices quantum cascade laser according to claim 1, which is characterized in that described Si_0.5Ge_0.5The germanium intergrowth of silicon and 5nm that buffer layer is 5nm forms silicon and germanium super crystal lattice structure.

3. the preparation method of Si/Ge superlattices quantum cascade laser according to claim 1, it is characterized in that, it is described Si_0.5Ge_0.5The SiGe ratio of buffer layer is 1: 1.

4. the preparation method of Si/Ge superlattices quantum cascade laser according to claim 1, it is characterized in that, it is described Aluminium electrode sequentially consists of titanium, aluminium, and process conditions are that titanium layer is with a thickness of 20nm, the speed of growthAluminium layer is thick Degree is 130nm, and growth rate is in 10nmGrowth rate is in 10nm to 130nm

5. a kind of preparation method based on claim 1-4 any one Si/Ge superlattices quantum cascade laser is prepared Si/Ge superlattices quantum cascade laser, which is characterized in that from the bottom up successively include silicon substrate, Si_0.5Ge_0.5Buffer layer, Silicon and germanium super crystal lattice and SiO₂, at the top of silicon and germanium super crystal lattice and Si_0.5Ge_0.5Aluminium electrode is deposited on buffer layer.