CN1054228C

CN1054228C - Semiconductor memory device with reduced data bus line load

Info

Publication number: CN1054228C
Application number: CN95109102A
Authority: CN
Inventors: 权健兑; 赵庸哲
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SK Hynix Inc
Priority date: 1994-07-07
Filing date: 1995-07-07
Publication date: 2000-07-05
Anticipated expiration: 2015-07-07
Also published as: GB2291233A; CN1125887A; GB2291233B; KR970003337B1; GB9513937D0

Abstract

The invention relates to a semiconductor memory device which having a plurality of memory blocks and a plurality of sense amplifiers. The semiconductor memory device comprises data bus lines for transferring the data. The data bus lines are divided into first and second parts. The semiconductor memory device further comprises a data bus line load reduction circuit for selecting one of the divided first and second data bus line parts in response to first and second data bus line control signals. The selected data bus line part inputs the data from one of the plurality of memory blocks selected in response to a memory block address. The other data bus line part, not selected, has a minimized load. The first and second data bus line control signals are produced in response to a most significant bit of the memory block address.

Description

Has the semiconductor memory that reduces data bus line load

The invention relates to the semiconductor memory that can reduce data bus line load and increase data transfer rate.

Generally speaking, data bus is used for such as dynamic RAM, static RAM and ROM (read-only memory) or similarly the data in the semiconductor memory of storer transmit.Data bus has such as path electric capacity, additional capacitor, the load of sheet resistance or similar impedance, thereby the delay that has caused data to transmit, path electric capacity is commonly referred to as natural capacity and produces between data bus and semiconductor chip, and additional capacitor is commonly called coupling capacitance, and it is to produce between adjacent data bus.

Referring to Fig. 1, common 16 M (million) static RAM (claiming SRAM later on) will be introduced in the back.

Referring to Fig. 1, provided common 16M SRAM with the square frame form among Fig. 1, as shown in FIG., common 16M SRAM comprises 64 memory block 1001-1064, and each piece wherein has the storage capacity of 256K position.That is, each of 64 storage block 1001-1064 comprises 128 storage unit in the horizontal direction, comprises 2048 storage unit in vertical direction.Generally speaking, along with semiconductor memory is increasing on scale, bit-line load is such as sheet resistance, path electric capacity, additional capacitor and coupling capacitance all increase, the bit-line load that increases produces bad influence in the input and output of data, cause number of memory cells purpose restriction in the storage block.For this reason, semiconductor storage unit comprises a large amount of storage blocks.Here, coupling capacitance is illustrated in the electric capacity that produces on the contact point between bit line and the storage unit.

Common 16M SRAM and then comprise 64 first order sense amplifier array 1101-1164, each of this array from storage block 1001-1064 corresponding one read 8 carry-out bits, here the number of each carry-out bit from storage block 1001-1064 only is to be example with 8, according to the difference of semiconductor access memory device, the figure place of output can be different.

Common 16M SRAM and then comprise 64 second level sensor amplifier 1201-1264, being used for 8 is that weighted units is read carry-out bit from first order sense amplifier array 1101-1164.The carry-out bit of second level sensor amplifier 1201-1264 is by being that weighted units is added on 8 bit data bus with 8, and common 16M SRAM and then comprise 8 third level sensor amplifier 1301-1308 is used for reading the position respectively on the corresponding data bus.Data bus has length like this, down to input block data from all storage block 1001-1064.

Consequently, along with semiconductor memory system becomes on scale greatly, data bus increases on length, has caused the increase of load, and the load increase of data bus has caused the delay of data transmission.

And then, in order to drive the data bus that has increased load, must increase the size of sensor amplifier, the size that increases sensor amplifier can reduce the data reading speed and increase layout area.

Consider this relation, just need data bus line load to reduce circuit and remove to reduce data bus line load, so just can increase data rate, reduce the layout area of sensor amplifier.

In view of the above problems, the present invention has been proposed.The purpose of this invention is to provide the semiconductor storage component part, this device can reduce the load of data bus, to increase data rate, reduces the layout area of sensor amplifier.

According to the present invention, can realize above-mentioned and other purpose by the semiconductor storage component part is provided.This semiconductor storage unit comprises a plurality of storage blocks that are used to store data, and a plurality ofly be used for reading the sensor amplifier device that is stored in a plurality of storage block data, such semiconductor storage unit also comprises: be used to transmit the data bus of the data of being read by a plurality of sensor amplifiers, data bus is divided into first and second portion; Reduce device with data bus, choose in first and second data buss part of being divided one to respond the first and second data bus control signals, thereby import data in make the data bus part be selected from a plurality of storage blocks, to select according to the address of a storage block one, and another does not have selected data bus part can have minimum load, and the first and second data bus control signals produce according to the highest significant position of MBA memory block address.

From below in conjunction with can more being expressly understood above and other objects of the present invention, characteristics and advantage the detailed description of accompanying drawing.

Fig. 1 is the block scheme of common 16M SRAM;

Fig. 2 A is the block scheme of the 16M SRAM in the embodiment of the invention;

Fig. 2 B is the detail circuits figure that the data bus line load of Fig. 2 A reduces circuit;

Fig. 3 is the sequential chart of Fig. 2 A 16M SRAM operation;

Now, having the 16MSRAM that data bus line load in the embodiment of the invention reduces circuit is described in detail with reference to Fig. 2 A and 2B.

Referring to Fig. 2 A, show the block scheme of the 16M SRAM of the embodiment of the invention here, as shown in the drawing, 16M SRAM comprises 64 storage block 2001-2064, each storage block all has the storage capacity of 256 numerical digits.This just says, each among 64 storage block 2001-2064 comprises 128 storage unit in the horizontal direction, comprises 2048 storage unit in vertical direction.

16M SRAM and then comprise 64 first order sense amplifier array 2101-2164, corresponding from storage block 2001-2064 of each in the middle of them reads 8 carry-out bits.Here, the number of the carry-out bit of each output from storage block 2001-2064 be with 8 as an example, according to the difference of semiconductor memory type, the figure place of carry-out bit can be different.

16M SRAM and then comprise 64 second level sensor amplifier 2201-2264 is the carry-out bit of exporting from first order sense amplifier array 2101-2164 of weight unit to read with 8 respectively.Carry-out bit among the sensor amplifier 2201-2264 of the second level is that weighted units is placed on 8 data buses with 8.

Data bus is divided into two parts, that is, first data bus part corresponding the 1st to the 32nd storage block, second data bus part corresponding the 33rd to the 64th storage block.It is to be connected between the 1st and the 2nd data bus part that data bus line load reduces circuit 2400, comes out to choose 1 in the middle of them.

16M SRAM and then comprise 8 third level sensor amplifier 2301-2308 is used for reducing circuit 2400 by data bus line load and reads each position in selected data bus part respectively.

Referring to Fig. 2 B, Fig. 2 B shows data bus line load minimizing circuit 2400 detail circuits figure in Fig. 2 A, label SO1L to SO8L and SO1L to SO8L represent the first of data bus respectively in this figure, and label SO1R to SO8R and SO1R to SO8R represent the second portion of data bus respectively, in first data bus part, data bus SOL and data bus SOL are complementary mutually, are used for transmitting paratope.Similarly, in second bus portion, data bus SOR and data bus SOR are complementary mutually, in order to transmit paratope.

Shown in Fig. 2 B, data bus line load reduces circuit 2400 to be made up of a plurality of CMOS transistor 2511-2586, and each in the middle of them is by being associated in formation to P-type mos (claiming PMOS later on) transistor drain and source electrode with N type metal oxide semiconductor (claiming NMOS later on) transistor drain and source electrode.Each among the CMOS transistor 2511-2586 6 to the complementary data bus correspondence, at each

CMOS transistor

2511,2513,2521,2523 ... in 2581 and 2583, the first data bus control signal PSOLZL is applied to the transistorized grid of PMOS, first data bus control designature PSOLZL is applied to the grid of nmos pass transistor, and the drain electrode of PMOS and nmos pass transistor is connected to one corresponding among the SO1L-SO8L of data bus first and the SO1L-SO8L jointly.The source electrode of PMOS and nmos pass transistor is linked to one corresponding among the 3rd utmost point sensor amplifier 2301-2308 jointly.Similarly,

CMOS transistor

2514,2516,2524,2526 ... in in the middle of 2584 and 2586 each, the second data bus control signal PSOLZR is applied to the transistorized grid of PMOS, second data bus control designature PSOLZR is applied to the grid of nmos pass transistor, the drain electrode of PMOS and nmos pass transistor is linked to one corresponding in the middle of data bus second portion SO1R-SO8R and the SO1R-SO8R jointly, and the source electrode of PMOS and nmos pass transistor is connected among the 3rd utmost point sensor amplifier 2301-2308 corresponding one jointly.Among the 3rd utmost point sensor amplifier 2301-2308 each is read corresponding 1 from the carry-out bit SO1-SO8 that reduces the CMOS transistor 2511-2586 in the circuit 2400 at data bus and SO1-SO8.

CMOS transistor

2512,2522 ... 2582 are used for the complementary data bus of balance first respectively, promptly at

CMOS transistor

2512,2522 ..., 2582 each in the drain electrode of PMOS and NMOS be connected among the data bus SO1L-SO8L of first corresponding one jointly, the source electrode of PMOS and nmos pass transistor is connected to 1 of correspondence of the data bus SO1L-SO8L of first jointly.The first data bus control signal PSOLZL is applied to the grid of nmos pass transistor, and first data bus control designature PSOLZL is applied to the transistorized grid of PMOS.

The

CMOS transistor

2515,2525 similarly ... 2585 are used the complementary data bus of balance second portion respectively.Promptly, at

CMOS transistor

2515,2525 ... in each of 2585, the drain electrode of PMOS and nmos pass transistor is connected among the second portion data bus SO1R-SO8R corresponding 1 jointly, and the source electrode of PMOS and nmos pass transistor is connected to corresponding 1 of data bus SO1R-SO8R of second portion jointly.The second data bus control signal PSOLZR is applied to the grid of nmos pass transistor, and second data bus control designature PSOLZR is applied to the transistorized grid of PMOS.

By suitably making up the MBA memory block address most significant digit, the enabling signal of the balanced signal and second utmost point sensor amplifier can produce first and second data bus control signal PSOLZL and the PSOLZR, and these reduce circuit 2400 with the binding data bus load afterwards and are at length described.It should be noted that when not being selected each

balance CMOS transistor

2512,2522 ... 2582,2515,2525 ... the corresponding data bus of 2585 balances.Therefore, the input and output of data can stably be carried out.

Describe the operation that data bus line load reduces circuit 2400 in detail below in conjunction with Fig. 3.

Fig. 3 has provided the sequential chart of the input and output waveform in data bus line load reduces circuit 2400.As shown in the figure, when the most effective high position of MBA memory block address was logical one, the first data bus control signal PSOLZL was a logical one.Equally, be under the situation of logical zero in the most effective high position of MBA memory block address, the rising edge from the negative edge of balanced signal to second utmost point sensor amplifier enabling signal, the first data bus control signal PSOLZL still remains on its logical one.

When the highest significant position of MBA memory block address was logical zero, the second data bus control signal PSOLZR was a logical one.Equally, when the MBA memory block address highest significant position was logical one, during rising edge from the negative edge of balanced signal to second utmost point sensor amplifier enabling signal, the second data bus control signal PSOLZR still maintained its logical one.

When the first data bus control signal PSOLZL is logical zero, data bus line load reduces circuit 2400 and chooses data bus SO1L-SO8L of first and SO1L-SO8L, in contrast, when the second data bus control signal PSOLZR was logical zero, data bus line load reduced circuit and chooses second portion data bus SO1R-SO8R and SO1R-SO8R.That is, data bus line load reduces circuit 2400 and only chooses one that is activated in the data bus part that is divided, and the data bus that is not selected partly is balanced, thereby does not wherein produce load.The result is that whole data bus line load has reduced half (50%).For example, make up the first and second partial data bus position SO selectively by responding the first and second data bus control signal PSOLZL and PSOLZR _jL, SO _jL, SO _jR and SO _jR can obtain j paratope SO _jAnd SO _j

Method as an alternative, the highest significant position that can directly use MBA memory block address are first and second data bus control signal PSOLZL and the PSOLZR.

Certainly, by all data buss of balance during from the negative edge of balanced signal to the rising edge of second level sensor amplifier enabling signal, can make whole data bus line load reduce manyly.

And then data bus can be divided into 3 parts at least.In this case, the data bus control signal must suitably be readjusted one that is activated in the data bus part that is divided for only choosing.

From foregoing description clearly as can be seen, according to the present invention, desirable one that only is divided into the data bus part is selected, make the bus portion that is not selected not produce load, therefore, whole data bus line load can reduce significantly, and the result is that the present invention has the effect that increases data transfer rate and reduce the sensor amplifier layout area.

Though disclose preferred embodiment of the present invention for illustrated purpose, do not breaking away under disclosed scope of invention of claim and the spiritual condition, the those skilled in the art can carry out various modifications, increases and replacement.

Claims

1, a kind of semiconductor memory, have a plurality of storage blocks of being used to store data, be used for a plurality of sensor amplifier devices read in the data of described a plurality of storage block stored and the data bus that is used to transmit the data of being read by said a plurality of sensor amplifier devices be is characterized in that:

Said data bus is divided into first and second parts; With

In described semiconductor memory, also comprise,

Data bus line load reduces device, be used for responding the first and second data bus control signals and select of first and second data buss parts of said division, make that the data bus part of selecting can be by input data of choosing in response to MBA memory block address from said a large amount of storage blocks, and another does not have selected data bus part can have minimized load, and the described first and second data bus control signals are that the highest significant position of response MBA memory block address produces.

2, the semiconductor memory of claim 1 wherein, is divided into described first and second parts to said data bus on the basis in the middle of a large amount of storage blocks; With

Wherein, the described first and second data bus control signals are highest significant positions of MBA memory block address.

3, the semiconductor memory of claim 2, wherein, from the negative edge of balanced signal rising edge up to the sensor amplifier enabling signal, the foment that the described first and second data bus control signals maintain them with described first and second data buss part of equilibrium the two.

4, the semiconductor memory of claim 2, wherein said data bus line load reduces device and comprises:

A plurality of first switchgears, when the first data bus control signal remained on its not state of activation, each said a plurality of switchgear was chosen of correspondence of the said data bus of said first data bus part;

A plurality of second switch devices, when the second data bus control signal remained on its not state of activation, each said a plurality of switchgear was chosen of correspondence of the said data bus of the said second data bus part;

A plurality of first balance devices, when the first data bus control signal maintains its state of activation, corresponding one of the said data bus of said first data bus part of each balance of said a plurality of first balance devices;

A plurality of second balance devices, when the second data bus control signal maintains its state of activation, corresponding of the said data bus of said second data bus of each balance of said a plurality of second balance devices part.

5, the semiconductor memory of claim 3, wherein, said data bus line load reduces device and comprises;

A plurality of first switchgears, when the first data bus control signal was maintained until its not state of activation, each of said a plurality of first switchgears was chosen corresponding of said first data bus said data bus partly;

A plurality of second switch devices, when the second data bus control signal maintained its not state of activation, each of said a plurality of second switch devices was chosen corresponding of said second data bus said data bus partly;

A plurality of first balance devices, when the first data bus control signal maintains its state of activation, corresponding of the said data bus of said first data bus of said a plurality of first balance device balances part; With