CN105406848B - Zero quiescent dissipation power-on and power-off reset signal generating circuit and power-on and power-off reset chip - Google Patents
Zero quiescent dissipation power-on and power-off reset signal generating circuit and power-on and power-off reset chip Download PDFInfo
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- CN105406848B CN105406848B CN201511029175.6A CN201511029175A CN105406848B CN 105406848 B CN105406848 B CN 105406848B CN 201511029175 A CN201511029175 A CN 201511029175A CN 105406848 B CN105406848 B CN 105406848B
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Abstract
A kind of zero quiescent dissipation power-on and power-off reset signal generating circuit of present disclosure and power-on and power-off reset chip, the power-on and power-off reset signal generating circuit, which includes a reset, makes energy control module, a capacitance control of discharge module, about one reset control module and an output latch module；The reset makes energy control module be electrically connected with the reset control module up and down, to provide enabled control signal to the reset control module up and down；The capacitance control of discharge module is electrically connected with the reset control module up and down, to carry out charge and discharge control to the node capacitor in the reset control module up and down；The reset control module up and down controls to carry out electrification reset control, the control of lower reset and zero quiescent dissipation respectively in power up and in lower electric process；The output latch module is electrically connected with the reset control module up and down, to the output as power-on and power-off reset signal generating circuit after the output signal caching latch by the reset control module up and down.
Description
Technical field
The present invention relates to the Analogical Circuit Technique field of IC design more particularly to a kind of zero quiescent dissipation power-on and power-off
Reset signal generating circuit and power-on and power-off reset chip.
Background technology
Existing reset circuit (POR) is opened first generally by detection circuit (Detector) cycle detection power supply status
Dynamic reference circuit (Bandgap) provides reference voltage Vref, then by RC accesses (resistance R1, resistance R2 and electricity as shown in Figure 1
Hold C) it opens, until when the partial pressure value of resistance R2 reaches reference voltage V ref, comparator (CMP) output switching activity changes and resets
Signal condition.
However, existing reset circuit generally detection power vd D reach safe operating voltage after, reference circuit and comparator
Circuit works normally, and to maintain output reset signal state, thus will produce DC power；In addition, due to CMOS technique compatible
The output of bandgap voltage reference circuit be generally fixed near 1.2V, therefore higher VDD value is needed to ensure the normal of reference circuit
Work.
Invention content
To solve the above-mentioned problems, the present invention provides a kind of zero quiescent dissipation power-on and power-off reset signal generating circuit,
Using the threshold voltage (or cut-in voltage) of metal-oxide-semiconductor (including PMOS tube and NMOS tube) as the switching threshold of internal circuit, this
Sample can work at the lower voltage；And by using self-test side feedback network controlling mechanism, disconnected after reset comes into force straight
Logical circulation road, so that not consumed DC current, to meet low-voltage and low-power dissipation systematic difference.
One side according to the present invention, the present invention provide a kind of zero quiescent dissipation power-on and power-off reset signal generating circuit,
Being resetted including one makes energy control module, a capacitance control of discharge module, about one reset control module and an output latch
Module；The reset makes energy control module be electrically connected with the reset control module up and down, to provide enabled control signal
To the reset control module up and down；The capacitance control of discharge module is electrically connected with the reset control module up and down,
To carry out charge and discharge control to the node capacitor in the reset control module up and down；The reset control module up and down
To carry out electrification reset control, the control of lower reset and zero quiescent dissipation control respectively in power up and in lower electric process
System；The output latch module is electrically connected with the reset control module up and down, the reset up and down is controlled mould
Output after the output signal caching latch of block as power-on and power-off reset signal generating circuit.
In an embodiment of the present invention, the reset makes the energy control module include：One first PMOS tube, one the 6th NMOS
Pipe, one the 7th NMOS tube, a hex inverter, one the 6th capacitance and a first resistor；The source electrode of first PMOS tube connects electricity
Source, the drain electrode of first PMOS tube are respectively electrically connected to the leakage of the input terminal and the 6th NMOS tube of the hex inverter
The grid of pole, first PMOS tube is electrically connected to one end of the first resistor；The source electrode of 6th NMOS tube is electric respectively
Be connected to the bottom crown of the 6th capacitance, the drain electrode and the 7th NMOS tube of the 7th NMOS tube grid；Described
The top crown of six capacitances is electrically connected to power supply；The grid of 6th NMOS tube and the source electrode of the 7th NMOS tube connect respectively
Ground；The output end of the hex inverter is electrically connected to the reset control module up and down；The other end of the first resistor
Ground connection.
In an embodiment of the present invention, the capacitance control of discharge module includes：One second resistance, one the 5th NMOS tube,
One the 5th capacitance, one second PMOS tube, one the 4th NMOS tube and one the 8th NMOS tube；One end of the second resistance is electrically connected to
The other end electrical connection of power supply, the second resistance is respectively electrically connected to the draining of the 5th NMOS tube, the 5th NMOS
The grid of pipe, the grid of second PMOS tube, the 4th NMOS tube grid and the 8th NMOS tube drain electrode；Described 5th
The source electrode of NMOS tube is respectively electrically connected to the top crown of the source electrode and the 5th capacitance of second PMOS tube, and the described 5th
The grid of NMOS tube is respectively electrically connected to the draining of the 8th NMOS tube, the draining of the 5th NMOS tube, described second
The grid of the grid of PMOS tube and the 4th NMOS tube；The bottom crown of 5th capacitance is grounded；Second PMOS tube
Drain electrode is respectively electrically connected to the reset control module up and down, the grid of the 8th NMOS tube and the 4th NMOS tube
Drain electrode, the grid of second PMOS tube are respectively electrically connected to the leakage of the grid and the 8th NMOS tube of the 4th NMOS tube
Pole；The drain electrode of 4th NMOS tube is respectively electrically connected to the grid of the reset control module and the 8th NMOS tube up and down
The grid of pole, the 4th NMOS tube is electrically connected to the drain electrode of the 8th NMOS tube, the source electrode ground connection of the 4th NMOS tube；
The bottom crown of 5th capacitance is grounded；The grid of 8th NMOS tube is electrically connected to the reset control module up and down,
The source electrode of 8th NMOS tube is grounded.
In an embodiment of the present invention, the reset control module up and down includes：One the 0th PMOS tube, one the 0th electricity
Resistance, a zero capacitance, one the 0th NMOS tube, one first capacitance, one first NMOS tube, one first phase inverter, one the oneth RS triggering
Device, one the 0th or door, one the 0th NAND gate, one the 5th phase inverter, one second buffer, one second phase inverter, a third reverse phase
Device, a third NMOS tube, a third capacitance, one second capacitance, one second NMOS tube, one the 4th capacitance, one the 4th phase inverter and
One the 0th phase inverter；The source electrode of 0th PMOS tube is electrically connected to power supply, and the grid of the 0th PMOS tube is electrically connected
Make one end of the grid and the first resistor of the first PMOS tube of energy control module to the reset, the 0th PMOS tube
Drain electrode be respectively electrically connected to one end of the zero resistance, the zero capacitance top crown and the 0th phase inverter input
End；The top crown of the zero capacitance is respectively electrically connected to the input of one end and the 0th phase inverter of the zero resistance
End, the bottom crown ground connection of the zero capacitance；The other end of the zero resistance is electrically connected to the drain electrode of the 0th NMOS tube；
The grid of 0th NMOS tube be respectively electrically connected to the bottom crown of first capacitance, first phase inverter output end and
The drain electrode of first NMOS tube, the source electrode ground connection of the 0th NMOS tube；The top crown of first capacitance is electrically connected to electricity
Source；The source electrode of first NMOS tube is grounded, and the grid of first NMOS tube is respectively electrically connected to first phase inverter
The output end of input terminal and first rest-set flip-flop；The output end of first phase inverter is electrically connected to first capacitance
Bottom crown, the input terminal of first phase inverter are electrically connected to the output end of first rest-set flip-flop；The first RS triggerings
The ends S of device are electrically connected to the output end of the described 0th or door, and the ends R of first rest-set flip-flop are respectively electrically connected to described second
The grid of NMOS tube, the 4th capacitance top crown and the 4th phase inverter output end；Described 0th or door first
Input terminal be electrically connected to it is described reset make energy control module hex inverter output end, the described 0th or door second input
End is respectively electrically connected to the output end of the output latch module and the 0th NAND gate；The first of 0th NAND gate is defeated
Enter the output end that end is electrically connected to second buffer, the second input terminal of the 0th NAND gate is electrically connected to the described 5th
The output end of phase inverter；The input terminal of second buffer is respectively electrically connected to the draining of the third NMOS tube, described
The top crown of three capacitances, the third phase inverter input terminal and second phase inverter output end；The third NMOS tube
Grid be electrically connected to the capacitance control of discharge module the 4th NMOS tube drain electrode, the source electrode of the third NMOS tube connects
Ground；The bottom crown of the third capacitance is grounded；The output end of the third phase inverter is respectively electrically connected to second phase inverter
Input terminal, the input terminal of the 5th phase inverter, second NMOS tube drain electrode and second capacitance bottom crown；Institute
State the second phase inverter input terminal be respectively electrically connected to the input terminal of the 5th phase inverter, second capacitance bottom crown and
The drain electrode of second NMOS tube；The input terminal of 5th phase inverter be respectively electrically connected to second capacitance bottom crown and
The drain electrode of second NMOS tube；The top crown of second capacitance is electrically connected to power supply, the bottom crown electricity of second capacitance
It is connected to the drain electrode of second NMOS tube；The source electrode of second NMOS tube is grounded, the grid difference of second NMOS tube
It is electrically connected to the output end of the top crown and the 4th phase inverter of the 4th capacitance；The bottom crown of 4th capacitance connects
Ground；The input terminal of 4th phase inverter is respectively electrically connected to the output end of the 0th phase inverter and mould is latched in the output
Block；The input terminal of 0th phase inverter is electrically connected to one end of the zero resistance.
In an embodiment of the present invention, the output latch module includes：One Z-buffer, one the 7th phase inverter, one
0th rest-set flip-flop and one first buffer；The input terminal of the Z-buffer is respectively electrically connected to the reset control up and down
The output end of the input terminal and the 0th phase inverter of 4th phase inverter of molding block, the output end of the Z-buffer are electrically connected
It is connected to the ends R of the 0th rest-set flip-flop；The input terminal of 7th phase inverter is respectively electrically connected to the 0th NAND gate
Output end and the described 0th or door the second input terminal, the output end of the 7th phase inverter is electrically connected to the 0th RS triggerings
The ends S of device；The output end of 0th rest-set flip-flop is electrically connected to the input terminal of first buffer；First buffer
Output end be electrically connected the output of the power-on and power-off reset signal generating circuit.
In an embodiment of the present invention, upon power-up, after the supply voltage rises to respective threshold, first PMOS tube
Drain electrode and the points of common connection voltage of drain electrode of the 6th NMOS tube set height, the grid voltage of third NMOS tube drags down, institute
The bottom crown voltage of the bottom crown and second capacitance of stating the first capacitance is increased with the supply voltage, and when power supply electricity
When pressure is more than the maximum value of PMOS tube threshold voltage and NMOS tube threshold voltage, the 0th PMOS tube fills the zero capacitance
The top crown voltage of electricity, the zero capacitance increases, and the output end voltage of the 0th phase inverter is set low, the 4th phase inverter
Output end voltage set it is high and to the 4th capacitor charging, while the input terminal voltage of second phase inverter is set low；Then, described
The output end voltage of second phase inverter set it is high and to the third capacitor charging, while the output end voltage of the NAND gate is set
It is low, and the output end voltage of the 7th phase inverter sets height, the S terminal voltages of the 0th rest-set flip-flop set height so that on described
The output of lower reset signal generating circuit is increased as the supply voltage increases, at the same time, described or door output
Terminal voltage is set low, and the S terminal voltages of first rest-set flip-flop set low and so that the input terminal voltage of first phase inverter sets height,
So that the bottom crown voltage pull-down of first capacitance, the 0th NMOS tube shutdown, to realize without DC power.
In an embodiment of the present invention, in power up, top crown voltage, the 4th electricity when the zero capacitance
The top crown voltage of the top crown voltage of appearance and the third capacitance rises to NMOS tube in the 0th phase inverter, described respectively
In two NMOS tubes and second buffer when threshold voltage of NMOS tube, the output of the power-on and power-off reset signal generating circuit
Voltage overturning makes electrification reset terminate for height, is simultaneously stopped transmission power-on reset signal.
In an embodiment of the present invention, when instantly electric, after the supply voltage is down to respective threshold, first PMOS tube
Drain electrode and the 6th NMOS tube drain electrode points of common connection voltage pull-down, the grid voltage of the third NMOS tube sets
It is high；Then, the input terminal voltage of second buffer is set low, and the output end voltage of the 0th NAND gate sets height, and described
The S terminal voltages of one rest-set flip-flop set it is high and so that the input terminal of first phase inverter is set low, and then first phase inverter
Output end voltage sets height, while the 0th NMOS tube is connected and the zero capacitance discharges to the zero resistance；With
This simultaneously, the input terminal voltage of the 0th phase inverter is set low, so the R terminal voltages of the 0th rest-set flip-flop set it is high so that
The output of the power-on and power-off reset signal generating circuit is reduced as the supply voltage reduces.
In an embodiment of the present invention, instantly in electric process, when the top crown voltage of the zero capacitance is down to described
In zero phase inverter when the threshold voltage of NMOS tube, the output voltage overturning of the power-on and power-off reset signal generating circuit makes to be low
Reset must be descended to start, until stopping sending lower reset signal at the end of lower electric process.
Another aspect according to the present invention, the present invention also provides a kind of power-on and power-off reset chips comprising above-mentioned power-on and power-off
Reset signal generating circuit to realize using metal-oxide-semiconductor cut-in voltage as circuit state switching threshold, and is given birth in upper and lower reset
DC channel is disconnected after effect.
It is an advantage of the current invention that by using simple logic feedback control mechanism, reset up and down of the present invention
Signal generating circuit is enable to respond quickly supply voltage in power-on and power-off repeatedly and within the operating voltage range of 1.5V~6V
Variation, and it is with good stability.And after reset comes into force, DC channel is disconnected, so that not consumed DC current,
To meet low-voltage and low-power dissipation systematic difference needs.Furthermore due to inside power-on and power-off reset signal generating circuit with metal-oxide-semiconductor threshold
Threshold voltage is converted as state, therefore, it is possible to save the reference circuit and comparator circuit in conventional reset circuit, and then is saved
Chip area.
Description of the drawings
Fig. 1 is reset circuit schematic diagram in the prior art；
Fig. 2 is the block architecture diagram of zero quiescent dissipation power-on and power-off reset signal generating circuit of the present invention；
Fig. 3 is the circuit connection diagram of power-on and power-off reset signal generating circuit described in one embodiment of the invention；
Fig. 4 is that power-on and power-off reset signal generates schematic diagram；
Fig. 5 is the simulation architecture schematic diagram of power-on and power-off reset signal generating circuit described in one embodiment of the invention；
Fig. 6 is the Organization Chart of power-on and power-off reset chip described in one embodiment of the invention.
Specific implementation mode
Below in conjunction with the accompanying drawings to the tool of power-on and power-off reset signal generating circuit provided by the invention and power-on and power-off reset chip
Body embodiment elaborates.
In the electronic device of the description present invention, term can be used, such as the zero, the first, second, third, etc. is similar
Word.These terms are and the attribute of a corresponding construction component, secondary merely to a component and other structures component are distinguished
Sequence, sequence etc. should not be so limited to the term.In addition, metal-oxide-semiconductor herein includes PMOS tube and NMOS tube, furthermore,
Described is metal-oxide-semiconductor such as the first PMOS tube, the 6th NMOS tube, the 7th NMOS tube.
Shown in Fig. 2 and Fig. 3, the present invention provides a kind of zero quiescent dissipation power-on and power-off reset signal generating circuit 100,
Being resetted including one keeps energy control module 10, a capacitance control of discharge module 20, about one reset control module 30 and one defeated
Go out latch module 40.The reset makes energy control module 10 be electrically connected with the reset control module 30 up and down, to provide
Enabled control signal is to the reset control module 30 up and down；The capacitance control of discharge module 20 and the reset up and down
Control module 30 is electrically connected, to carry out charge and discharge control to the node capacitor in the reset control module 30 up and down.Institute
State up and down reset control module 30 to carried out respectively in power up and in lower electric process electrification reset control, under reply by cable
Position control and zero quiescent dissipation control.The output latch module 40 is electrically connected with the reset control module 30 up and down,
To be used as power-on and power-off reset signal generating circuit after the output signal caching latch by the reset control module 30 up and down
100 output.
Shown in Figure 3, in an embodiment of the present invention, the reset makes the energy control module 10 include：One the oneth PMOS
Pipe PM1, one the 6th NMOS tube NM6, one the 7th NMOS tube NM7, a hex inverter INV6, the electricity of one the 6th capacitance C6 and one first
Hinder R1；The source electrode of the first PMOS tube PM1 meets supply voltage VDD, and the drain electrode of the first PMOS tube PM1 is respectively electrically connected to
The drain electrode of the input terminal and the 6th NMOS tube NM6 of the hex inverter INV6, the grid electricity of the first PMOS tube PM1
It is connected to one end of the first resistor R1；The source electrode of the 6th NMOS tube NM6 is respectively electrically connected to the 6th capacitance C6
Bottom crown, the 7th NMOS tube NM7 drain electrode and the 7th NMOS tube NM7 grid；The 6th capacitance C6's is upper
Pole plate is electrically connected to supply voltage VDD；The grid of the 6th NMOS tube NM6 and the source electrode difference of the 7th NMOS tube NM7
Ground connection；The output end of the hex inverter INV6 is electrically connected to the reset control module 30 up and down；The first resistor
The other end of R1 is grounded.
The capacitance control of discharge module 20 includes：One second resistance R2, one the 5th NMOS tube NM5, one the 5th capacitance C5,
One second PMOS tube PM2, one the 4th NMOS tube NM4 and one the 8th NMOS tube NM8；One end of the second resistance R2 is electrically connected to
The other end electrical connection of power supply, the second resistance R2 is respectively electrically connected to the draining of the 5th NMOS tube NM5, the described 5th
The grid of NMOS tube NM5, the grid of the second PMOS tube PM2, the grid of the 4th NMOS tube NM4 and the 8th NMOS tube
The drain electrode of NM8；The source electrode of the 5th NMOS tube NM5 is respectively electrically connected to the source electrode and described of the second PMOS tube PM2
The top crown of five capacitance C5, the grid of the 5th NMOS tube NM5 be respectively electrically connected to the drain electrode of the 8th NMOS tube NM8,
The draining of the 5th NMOS tube NM5, the grid of the grid and the 4th NMOS tube NM4 of the second PMOS tube PM2；It is described
The bottom crown of 5th capacitance C5 is grounded；The drain electrode of the second PMOS tube PM2 is respectively electrically connected to the reset control up and down
Module 30, the 8th NMOS tube NM8 grid and the 4th NMOS tube NM4 drain electrode, the grid of the second PMOS tube PM2
Pole is respectively electrically connected to the drain electrode of the grid and the 8th NMOS tube NM8 of the 4th NMOS tube NM4；4th NMOS tube
The drain electrode of NM4 is respectively electrically connected to the grid of the reset control module 30 and the 8th NMOS tube NM8 up and down, and described the
The grid of four NMOS tube NM4 is electrically connected to the drain electrode of the 8th NMOS tube NM8, the source electrode ground connection of the 4th NMOS tube NM4；
The bottom crown of the 5th capacitance C5 is grounded；The grid of the 8th NMOS tube NM8 is electrically connected to the reset control up and down
Module 30, the source electrode ground connection of the 8th NMOS tube NM8.
Reset control module 30 includes above and below described：One the 0th PMOS tube PM0, a zero resistance R0, a zero capacitance
C0, one the 0th NMOS tube NM0, one first capacitance C1, one first NMOS tube NM1, one first phase inverter INV1, one the oneth RS triggerings
Device RSFF1, one the 0th or door OR0, one the 0th NAND gate NAND0, one the 5th phase inverter INV5, one second buffer BUF2, one
Second phase inverter INV2, a third phase inverter INV3, a third NMOS tube NM3, a third capacitance C3, one second capacitance C2, one
Second NMOS tube NM2, one the 4th capacitance C4, one the 4th phase inverter INV4 and one the 0th phase inverter INV0；0th PMOS tube
The source electrode of PM0 be electrically connected to supply voltage VDD, the 0th PMOS tube PM0 grid be respectively electrically connected to it is described reset it is enabled
One end of the grid and the first resistor R1 of first PMOS tube PM1 of control module 10, the drain electrode of the 0th PMOS tube PM0
It is respectively electrically connected to one end of the zero resistance R0, the top crown of the zero capacitance C0 and the 0th phase inverter INV0
Input terminal；The top crown of the zero capacitance C0 is respectively electrically connected to one end of the zero resistance R0 and the 0th phase inverter
The input terminal of INV0, the bottom crown ground connection of the zero capacitance C0；The other end of the zero resistance R0 is electrically connected to described
The drain electrode of zero NMOS tube NM0；The grid of the 0th NMOS tube NM0 be respectively electrically connected to the first capacitance C1 bottom crown,
The drain electrode of the output end of the first phase inverter INV1 and the first NMOS tube NM1, the source electrode of the 0th NMOS tube NM0 connect
Ground；The top crown of the first capacitance C1 is electrically connected to power supply；The source electrode of the first NMOS tube NM1 is grounded, and described first
The grid of NMOS tube NM1 is respectively electrically connected to the input terminal of the first phase inverter INV1 and the first rest-set flip-flop RSFF1
Output end；The output end of the first phase inverter INV1 is electrically connected to the bottom crown of the first capacitance C1, and described first is anti-
The input terminal of phase device INV1 is electrically connected to the output end of the first rest-set flip-flop RSFF1；The first rest-set flip-flop RSFF1's
The ends S are electrically connected to the output end of the described 0th or door OR0, and the ends R of the first rest-set flip-flop RSFF1 are respectively electrically connected to described
The grid of second NMOS tube NM2, the 4th capacitance C4 top crown and the 4th phase inverter INV4 output end；Described
The first input end of zero or door OR0 is electrically connected to the output end of the hex inverter INV6 for resetting and making energy control module 10,
The second input terminal of described 0th or door OR0 is respectively electrically connected to the output latch module 40 and the 0th NAND gate
The output end of NAND0；The first input end of the 0th NAND gate NAND0 is electrically connected to the output of the second buffer BUF2
End, the second input terminal of the 0th NAND gate NAND0 are electrically connected to the output end of the 5th phase inverter INV5；Described second
The input terminal of buffer BUF2 be respectively electrically connected to the draining of the third NMOS tube NM3, the top crown of the third capacitance C3,
The output end of the input terminal of the third phase inverter INV3 and the second phase inverter INV2；The grid of the third NMOS tube NM3
Pole is electrically connected to the drain electrode of the 4th NMOS tube NM4 of the capacitance control of discharge module 20, the source electrode of the third NMOS tube NM3
Ground connection；The bottom crown of the third capacitance C3 is grounded；The output end of the third phase inverter INV3 is respectively electrically connected to described
The input terminal of two phase inverter INV2, the input terminal of the 5th phase inverter INV5, the drain electrode of the second NMOS tube NM2 and described
The bottom crown of second capacitance C2；The input terminal of the second phase inverter INV2 is respectively electrically connected to the 5th phase inverter INV5's
Input terminal, the second capacitance C2 bottom crown and the second NMOS tube NM2 drain electrode；The 5th phase inverter INV5's is defeated
Enter the drain electrode that end is respectively electrically connected to the bottom crown and the second NMOS tube NM2 of the second capacitance C2；Second capacitance
The bottom crown that the top crown of C2 is electrically connected to supply voltage VDD, the second capacitance C2 is electrically connected to the second NMOS tube NM2
Drain electrode；The source electrode of the second NMOS tube NM2 is grounded, and the grid of the second NMOS tube NM2 is respectively electrically connected to described the
The output end of the top crown of four capacitance C4 and the 4th phase inverter INV4；The bottom crown of the 4th capacitance C4 is grounded；It is described
The input terminal of 4th phase inverter INV4 is respectively electrically connected to the output end of the 0th phase inverter INV0 and mould is latched in the output
Block 40；The input terminal of the 0th phase inverter INV0 is electrically connected to one end of the zero resistance R0.
The output latch module 40 includes：One Z-buffer BUF0, one the 7th phase inverter INV7, one the 0th RS triggerings
Device RSFF0 and one first buffer BUF1；The input terminal of the Z-buffer BUF0 is respectively electrically connected to reply by cable above and below described
The output end of the input terminal and the 0th phase inverter INV0 of 4th phase inverter INV4 of position control module 30, the 0th buffering
The output end of device BUF0 is electrically connected to the ends R of the 0th rest-set flip-flop RSFF0；The input terminal of the 7th phase inverter INV7 point
It is not electrically connected to the second input terminal of the output end and the described 0th or door OR0 of the 0th NAND gate NAND0, the described 7th is anti-
The output end of phase device INV7 is electrically connected to the ends S of the 0th rest-set flip-flop RSFF0；The 0th rest-set flip-flop RSFF0's is defeated
Outlet is electrically connected to the input terminal of the first buffer BUF1；The output end of the first buffer BUF1 is electrically connected on described
The output VPOR of lower reset signal generating circuit 100.
Furthermore, reset circuit generation circuit up and down shown in Fig. 3 is provided simultaneously with electrification reset function and lower electricity
Main node A → B → C → D → E → F shown in Fig. 3 → control access H → A of reset function, wherein electrification reset function
It completes, while DC channel is cut off after electrification reset comes into force in the control access；Under reply by cable bit function mainly by M → N → H →
It completes A → B → control access VPOR.Furthermore the reset shown in Fig. 2 makes energy control module 10 and the capacitance control of discharge
Module 20 plays self-test on-off action, wherein as mentioned previously, the reset makes energy control module 10 include first resistor
R1, the first PMOS tube PM1, the 6th NMOS tube NM6, the 7th NMOS tube NM7 and the 6th capacitance C6；The capacitance control of discharge module
20 include second resistance R2, the 5th NMOS tube NM5, the second PMOS tube PM2, the 4th NMOS tube NM4, the 8th NMOS tube NM8 and institute
State the 5th capacitance C5.
The power-on and power-off reset signal generating circuit 100 is act as：Either in power supply electrifying process still in lower electricity
In the process, as long as detect threshold voltages of the supply voltage VDD less than setting, then the reset level signal of one fixed width is exported
(being typically low level signal)；And when threshold voltages of the VDD higher than setting, then VDD value is exported, that is, follows VDD to change.Referring to
Shown in Fig. 4, VTRTo power on threshold voltage, TPRFor the time of power-on reset signal；VTFFor lower electric threshold voltage, TPFIt is replied by cable under
The time of position signal.VPOR shown in Fig. 4 is the output of power-on and power-off reset signal generating circuit 100, in T0<T<When T1, VDD
<VTR, VPOR holding low potentials, i.e. VPOR=0；In T1<T<When T2, VDD>VTRAnd VDD>VTF, VPOR=VDD；T2<T<When T3,
VPOR=0.Electrification reset is during supply voltage VDD rises to stable operating voltage from 0V, as long as VDD<VTR, then
Export power-on reset signal, i.e. VPOR=0.Lower reset is to drop to 0V's from stable operating voltage in supply voltage VDD
In the process, as long as VDD<VTF, then lower reset signal, i.e. VPOR=0 are exported.
Shown in Fig. 3, energy control module 10 is made for the reset：In the present embodiment, when powering on, work as power supply
Voltage rises to the threshold voltage of the first PMOS tube PM1 | Vthp | when, the drain electrode of the first PMOS tube PM1 and described
Points of common connection (node N i.e. shown in Fig. 3) voltage of the drain electrode of six NMOS tube NM6 sets height, and (it is to set high level to set high, hereafter
It is identical).The output end voltage of hex inverter INV6 sets low (set low as set low level, hereafter identical).6th NMOS tube NM6
It is connected for back biased diode, no current flows through.7th NMOS tube NM7 connects for forward-biased diode, threshold voltage Vthn.Cause
This, it is the supply voltage after stablizing that the pressure difference at the both ends the 6th capacitance C6, which is finally clamped down in VDD1-Vthn, wherein VDD1,
Value.When lower electricity, especially quickly under lower electric condition, since the pressure difference at the both ends the 6th capacitance C6 cannot be mutated, then, node
M voltages (points of common connection of the drain electrode of the source electrode and the 7th NMOS tube NM7 of the i.e. described 6th NMOS tube NM6) are with power supply
Voltage VDD variations are VDD- (VDD1-Vthn).When the 6th NMOS tube NM6 meets condition VGS >=Vthn, i.e. 0- [VDD-
(VDD1-Vthn)] >=Vthn, when being reduced to VDD≤VDD1-2Vthn, the 6th NMOS tube NM6 conductings so that node N electricity
Pressure quickly drags down, and the output end voltage of hex inverter INV6 sets height.At this point, the NMOS tube becomes back biased diode connection,
It can not be connected, in this way, the 6th capacitance C6 will not discharge.Therefore, the 6th capacitance C6 can be tieed up within a certain period of time
Hold constant pressure difference.
For the capacitance control of discharge module 20：In the present embodiment, when powering on, the 5th NMOS tube NM5 is just
Inclined diode connection, threshold voltage Vthn.Since the second PMOS tube PM2 can not be connected, nodes X voltage is (i.e.
The both ends pressure difference of the 5th capacitance C5) it is about finally VDD1-Vthn, wherein VDD1 is the supply voltage value after stablizing.Institute
After stating the 4th NMOS tube NM4 conductings, node Y (grid of the i.e. described third NMOS tube NM3) voltage is set low.When lower electricity, especially
It is to ignore the pressure drop of second resistance R2 under quick lower electric condition, after supply voltage VDD is down to Vthn, the 4th NMOS tube NM4
Cut-off.The supply voltage drop to VDD1-Vthn-VDD >=| Vthp | when, the second PMOS tube PM2 conducting meets
Supply voltage VDD≤MIN (Vthn, VDD1-Vthn- | Vthp |) when, the drain electrode and described second of the 4th NMOS tube NM4
Node Y voltages are set height by the points of common connection of the drain electrode of PMOS tube PM2.At this point, after the 8th NMOS tube NM8 conductings, quickly
The grid of 5th NMOS tube NM5 is dragged down.Therefore, the 5th NMOS tube NM5 becomes back biased diode connection, so that described the
Five capacitance C5 will not discharge.Therefore, the 5th capacitance C5 can maintain constant pressure difference within a certain period of time.In this time
It is interior, the third NMOS tube NM3 conductings so that the third capacitance C3 repid discharges, and the voltage pull-down of node E.
Furthermore, upon power-up, after the supply voltage rises to respective threshold, the leakage of the first PMOS tube PM1
Points of common connection (node N i.e. shown in Fig. 3) voltage of the drain electrode of pole and the 6th NMOS tube NM6 sets height, third NMOS tube
The grid voltage of NM3 drags down.According to the principle that the pressure difference on capacitance cannot be mutated, bottom crown (i.e. Fig. 3 of the first capacitance C1
Shown in node A) and bottom crown (node A i.e. shown in Fig. 3) voltage of the second capacitance C2 increased with the supply voltage,
And when the supply voltage be more than PMOS tube threshold voltage and NMOS tube threshold voltage maximum value (i.e. VDD >=MAX (Vthn, |
Vthp |) when, it is opened by the DC channel that the 0th PMOS tube PM0, the zero resistance R0 and the 0th NMOS tube NM0 are constituted,
The portion of electrical current of the 0th PMOS tube PM0 charges to the zero capacitance C0 by T1, the top crown of the zero capacitance C0
(node B i.e. shown in Fig. 3) voltage increases, and the output end voltage of the 0th phase inverter INV0 is set low.Then, the described 4th is anti-
The output end voltage of phase device INV4 sets height, and after time T2, to the 4th capacitance C4 chargings.In this way, the 4th capacitance C4
Top crown voltage set height, the second NMOS tube NM2 conductings, so that the bottom crown voltage of the second capacitance C2 reduces.Together
The input terminal voltage of the second phase inverters of Shi Suoshu INV2 is set low.Then, output end (i.e. Fig. 3 institutes of the second phase inverter INV2
The node E shown) voltage sets height, after time T3, charges to the third capacitance C3.The output end of the NAND gate simultaneously
(node F i.e. shown in Fig. 3) voltage is set low.At this point, the output end voltage of the 7th phase inverter INV7 sets height, the 0th RS
The S terminal voltages of trigger RSFF0 set height.Since the S terminal voltages of the 0th rest-set flip-flop RSFF0 set height, R terminal voltages are set low,
So that the output VPOR of the power-on and power-off reset signal generating circuit 100 is increased as the supply voltage increases.Obviously, on
When electric, VPOR maintains low effective time TPRAbout T1+T2+T3.After the output end voltage of the NAND gate is set low, described or door
Output end voltage set low, the S terminal voltages of the first rest-set flip-flop RSFF1 are set low.Due to the first rest-set flip-flop RSFF1
S terminal voltages set low, R terminal voltages set height so that the input terminal (node H i.e. shown in Fig. 3) of the first phase inverter INV1 electricity
Pressed height, so that the first NMOS tube NM1 is connected, the bottom crown (node A i.e. shown in Fig. 3) of the first capacitance C1
Voltage pull-down, the 0th NMOS tube NM0 shutdowns, to realize without DC power.
In power up, if assuming Vthn=| Vthp | when=Vth, VDD >=Vth, flow through the 0th PMOS tube PM0
Electric current with the 0th NMOS tube NM0 is respectively IPA、INA, the charging current of the zero capacitance C0 is ICA.When the described 0th
Top crown (node B i.e. shown in Fig. 3) voltage V of capacitance C0BRise to the threshold value electricity of NMOS tube in the 0th phase inverter INV0
When pressing Vth, output switching activity, therefore in VBIn 0~Vth of variation range, there is Δ=VSG-Vth=for the 0th PMOS tube PM0
VDD-Vth≤VDD-VB, i.e., the described 0th PMOS tube PM0 is operated in saturation region.The size of the zero resistance R0 is set so that
The overdrive voltage for playing the 0th NMOS tube NM0 of on-off action meets Δ=VGS-Vth=VDD-Vth>VB-INAR0, i.e.,
The 0th NMOS tube NM0 is allowed to be operated in linear zone.
Top crown (node C i.e. shown in Fig. 3) voltage V of the 4th capacitance C4CWith the upper pole of the third capacitance C3
Plate (node E i.e. shown in Fig. 3) voltage VEOverturning from low to high respectively passes through the 4th phase inverter INV4 and described
The 4th capacitance C4 of PMOS tube pair and third capacitance C3 in two phase inverter INV2 charge and complete.Herein, it is arranged all anti-
PMOS tube equivalent resistance in phase device (such as the first phase inverter INV1, second phase inverter INV2 etc.) is RP, ignore gate circuit
Delay, to sum up then has
In power up, when the zero capacitance C0 top crown (node B i.e. shown in Fig. 3) voltage, the described 4th
Top crown (the node C i.e. shown in Fig. 3) voltage of capacitance C4 and the top crown (node i.e. shown in Fig. 3 of the third capacitance C3
E) voltage rises to NMOS tube, the second NMOS tube NM2 and second buffer in the 0th phase inverter INV0 respectively
The threshold voltage vt h of NMOS tube, i.e. V in BUF2B=VC=VEWhen=Vth, the power-on and power-off reset signal generating circuit 100
Output voltage overturning is height so that electrification reset terminates, and is simultaneously stopped transmission power-on reset signal.Therefore it powers on VPOR and maintains low to have
The time T of effectPRFor
In fact, above-mentioned TPRHave ignored time when supply voltage VDD is power-up to Vth, i.e., the described 0th PMOS tube PM0 and
The 0th NMOS tube NM0 is by initial cutoff to the time of conducting.It is tan α (0 that setting supply voltage VDD, which powers on slope,<α<π/
2), then powering on VPOR maintains the low effective time to be adjusted to T 'PR=TPR+ Vth/tan α power on threshold voltage VTR=T 'PRtanα。
With continued reference to Fig. 3, when instantly electric, after the supply voltage is down to respective threshold, the leakage of the first PMOS tube PM1
Points of common connection (node N i.e. shown in Fig. 3) voltage pull-down of the drain electrode of pole and the 6th NMOS tube NM6, the third
The grid voltage of NMOS tube NM3 sets height.Then, the input terminal voltage of the second buffer BUF2 is set low, the described 0th with it is non-
The output end voltage of door NAND0 sets height, and the S terminal voltages of the first rest-set flip-flop RSFF1 set height.Since the first RS is triggered
The S terminal voltages of device RSFF1 set height, and R terminal voltages are set low, so that the input terminal of the first phase inverter INV1 is (i.e. shown in Fig. 3
Node H) voltage sets low.Then, the output end voltage of the first phase inverter INV1 sets height.Meanwhile the 0th NMOS tube
NM0 is connected, and after time T4, the zero capacitance C0 discharges via the zero resistance R0.At the same time, the described 0th is anti-
The input terminal voltage of phase device INV0 is set low.In this way, the R terminal voltages of the 0th rest-set flip-flop RSFF0 set height.Due to the described 0th
The R terminal voltages of rest-set flip-flop RSFF0 set height, and S terminal voltages are set low, therefore so that the power-on and power-off reset signal generating circuit 100
Output reduced as the supply voltage reduces, i.e., by VPOR output voltages pressure set low.
At the end of powering on, node B point voltages V shown in Fig. 3BRise to the supply voltage VDD1 after stablizing, and VDD≤
When VDD1-2Vth, the reset makes energy control module 10 come into force.Therefore, it is VDD from VDD1 that VPOR, which maintains high time, when lower electricity
Time when being down to VDD1-2Vth adds T4.As Vth≤VDD≤VDD1-2Vth and Vth≤VBWhen≤VDD, the 0th electricity
Hold C0 to discharge via the zero resistance R0, until node B point voltages VBIt is down to the turnover voltage of the 0th phase inverter INV0
Vth.In this period, there is Δ=VSG-Vth=VDD-Vth for the 0th PMOS tube PM0>VDD-VB, i.e., the described 0th
PMOS tube PM0 is operated in linear zone.The electric current that the 0th PMOS tube PM0 and the 0th NMOS tube NM0 is arranged is respectively IPB、
INB, the discharge current of the zero capacitance C0 is ICB, then have
In lower electric process, when the top crown voltage of the zero capacitance C0 is down to NMOS in the 0th phase inverter INV0
When the threshold voltage of pipe, the output voltage of the power-on and power-off reset signal generating circuit 100 overturns to be low so that lower reset
Start, until stopping sending lower reset signal at the end of lower electric process.Then, then have
It is tan β (pi/2s that electric slope under supply voltage VDD, which is arranged,<β<π), the lower electric time will be T5, then lower electricity VPOR remains low
The effective time is TPF=T5-T4- 2Vth/ | tan β |, lower electricity threshold voltage VTF=VDD1-TPF|tanβ|。
Under the conditions of power-on and power-off repeatedly, node B point voltage pull-downs shown in Fig. 3 when electricity lower due to first time, so that described the
The output end voltage overturning of zero phase inverter INV0 is height.The point voltage of node C shown in Fig. 3 is via the 4th capacitance C4 electric discharge post-tensionings
Low, the second NMOS tube NM2 shutdowns, the top crown voltage of the third capacitance C3 is in the capacitance control of discharge module 20
Become low under effect.At this point, output end (node F i.e. shown in Fig. 3) voltage of the 0th NAND gate NAND0 sets height, it is described
The S terminal voltages of 0th rest-set flip-flop RSFF0 are set low, so that it is guaranteed that the lasting progress of lower electric process.Under the second capacitance C2
Pole plate (node D shown in Fig. 3) voltage follow supply voltage VDD eventually becomes low.Each node voltage shown in Fig. 3 restores to initial
State under power-up conditions can be carried out effectively to power on for the second time.
SMIC0.13 μm can be used for the implementation method of power-on and power-off reset signal generating circuit 100 described above
CMOS technology, at Corner (TT, SS, FF), temperature (- 40 DEG C, 27 DEG C, 125 DEG C), VDD (1.5V, 5.0V, 6.0V), to upper
Lower reset signal threshold value voltage and quiescent dissipation are emulated, and the Monte of power-on and power-off repeatedly is under representative condition
Carlo is analyzed, respectively as shown in table 1 and Fig. 5.According to table 1, clearly show that the DC power under various supply voltages is equal
For 0 μ A, repeatedly when power-on and power-off, it is enable to respond quickly mains voltage variations and with good stability.Obviously, the power-on and power-off
Reset signal generating circuit 100 has certain advantage in the application of low-voltage and low-power dissipation system.
Threshold voltage under the conditions of table 1. is various and power consumption simulation result
Shown in Figure 6, another aspect according to the present invention, the present invention can also provide a kind of power-on and power-off reset chip 1,
It includes above-mentioned power-on and power-off reset signal generating circuit 100, and threshold is converted using metal-oxide-semiconductor cut-in voltage as circuit state to realize
Value, and disconnect DC channel after upper and lower reset comes into force.
To sum up, by using simple logic feedback control mechanism, power-on and power-off reset signal generating circuit of the present invention
100 are enable to respond quickly the variation of supply voltage in power-on and power-off repeatedly and within the operating voltage range of 1.5V~6V, and
And it is with good stability.And after reset comes into force, DC channel is disconnected, so that not consumed DC current, low to meet
That forces down power consumption system applies needs.Furthermore due to inside power-on and power-off reset signal generating circuit 100 with metal-oxide-semiconductor threshold voltage
It is converted as state, therefore, it is possible to save the reference circuit and comparator circuit in conventional reset circuit, and then saves chip face
Product.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (10)
1. a kind of zero quiescent dissipation power-on and power-off reset signal generating circuit, which is characterized in that including one reset make energy control module,
One capacitance control of discharge module, about one reset control module and an output latch module；
It is described reset make energy control module with it is described up and down reset control module be electrically connected, to provide enable control signal to
The reset control module up and down；
The capacitance control of discharge module is electrically connected with the reset control module up and down, to the reset control up and down
Molding node capacitor in the block carries out charge and discharge control；
It is described up and down reset control module in power up and lower electric process in carry out respectively electrification reset control, under
Reset controls and zero quiescent dissipation control；
The output latch module is electrically connected with the reset control module up and down, the reset up and down is controlled mould
Output after the output signal caching latch of block as power-on and power-off reset signal generating circuit；
Wherein, the reset makes energy control module and the capacitance control of discharge module to self-test slowdown monitoring switch.
2. power-on and power-off reset signal generating circuit according to claim 1, which is characterized in that described to reset enabled control mould
Block includes：One first PMOS tube, one the 6th NMOS tube, one the 7th NMOS tube, a hex inverter, one the 6th capacitance and one first
Resistance；The source electrode of first PMOS tube connects power supply, and the drain electrode of first PMOS tube is respectively electrically connected to the 6th reverse phase
The grid of the drain electrode of the input terminal of device and the 6th NMOS tube, first PMOS tube is electrically connected to the one of the first resistor
End；The source electrode of 6th NMOS tube is respectively electrically connected to the drain electrode of the bottom crown, the 7th NMOS tube of the 6th capacitance
With the grid of the 7th NMOS tube；The top crown of 6th capacitance is electrically connected to power supply；The grid of 6th NMOS tube
It is grounded respectively with the source electrode of the 7th NMOS tube；The output end of the hex inverter is electrically connected to the reset control up and down
Molding block；The other end of the first resistor is grounded.
3. power-on and power-off reset signal generating circuit according to claim 2, which is characterized in that the capacitance control of discharge mould
Block includes：One second resistance, one the 5th NMOS tube, one the 5th capacitance, one second PMOS tube, one the 4th NMOS tube and one the 8th
NMOS tube；One end of the second resistance is electrically connected to power supply, and the other end of the second resistance is respectively electrically connected to described
The draining of five NMOS tubes, the grid of the 5th NMOS tube, the grid of second PMOS tube, the grid of the 4th NMOS tube and institute
State the drain electrode of the 8th NMOS tube；The source electrode of 5th NMOS tube is respectively electrically connected to the source electrode of second PMOS tube and described
The top crown of 5th capacitance, the grid of the 5th NMOS tube are respectively electrically connected to the draining of the 8th NMOS tube, described
The draining of five NMOS tubes, the grid of the grid of second PMOS tube and the 4th NMOS tube；The lower pole of 5th capacitance
Plate earthing；The drain electrode of second PMOS tube is respectively electrically connected to reset control module, the 8th NMOS tube up and down
Grid and the 4th NMOS tube drain electrode, the grid of second PMOS tube is respectively electrically connected to the 4th NMOS tube
The drain electrode of grid and the 8th NMOS tube；The drain electrode of 4th NMOS tube is respectively electrically connected to the reset control up and down
The grid of the grid of module and the 8th NMOS tube, the 4th NMOS tube is electrically connected to the drain electrode of the 8th NMOS tube,
The source electrode of 4th NMOS tube is grounded；The bottom crown of 5th capacitance is grounded；The grid of 8th NMOS tube is electrically connected
To the reset control module up and down, the source electrode ground connection of the 8th NMOS tube.
4. power-on and power-off reset signal generating circuit according to claim 3, which is characterized in that the reset control up and down
Module includes：One the 0th PMOS tube, a zero resistance, a zero capacitance, one the 0th NMOS tube, one first capacitance, one first
NMOS tube, one first phase inverter, one first rest-set flip-flop, one the 0th or door, one the 0th NAND gate, one the 5th phase inverter, one
Two buffers, one second phase inverter, a third phase inverter, a third NMOS tube, a third capacitance, one second capacitance, one second
NMOS tube, one the 4th capacitance, one the 4th phase inverter and one the 0th phase inverter；The source electrode of 0th PMOS tube is electrically connected to electricity
The grid in source, the 0th PMOS tube is respectively electrically connected to grid and the institute of first PMOS tube for resetting and making energy control module
One end of first resistor is stated, the drain electrode of the 0th PMOS tube is respectively electrically connected to one end of the zero resistance, the described 0th
The input terminal of the top crown of capacitance and the 0th phase inverter；The top crown of the zero capacitance is respectively electrically connected to the described 0th
The input terminal of one end of resistance and the 0th phase inverter, the bottom crown ground connection of the zero capacitance；The zero resistance it is another
One end is electrically connected to the drain electrode of the 0th NMOS tube；The grid of 0th NMOS tube is respectively electrically connected to first capacitance
Bottom crown, first phase inverter output end and first NMOS tube drain electrode, the source electrode of the 0th NMOS tube connects
Ground；The top crown of first capacitance is electrically connected to power supply；The source electrode of first NMOS tube is grounded, first NMOS tube
Grid is respectively electrically connected to the output end of the input terminal and first rest-set flip-flop of first phase inverterDescribed first is anti-
The output end of phase device is electrically connected to the bottom crown of first capacitance, and the input terminal of first phase inverter is electrically connected to described
The output end of one rest-set flip-flopThe ends S of first rest-set flip-flop are electrically connected to the output end of the described 0th or door, and described
The ends R of one rest-set flip-flop are respectively electrically connected to the grid of second NMOS tube, the top crown of the 4th capacitance and described
The output end of four phase inverters；Described 0th or the first input end of door be electrically connected to described reset and make the 6th anti-of energy control module
The output end of phase device, the described 0th or the second input terminal of door be respectively electrically connected to the output end of the 0th NAND gate and described
Export latch module；The first input end of 0th NAND gate is electrically connected to the output end of second buffer, and described
Second input terminal of zero NAND gate is electrically connected to the output end of the 5th phase inverter；The input terminal of second buffer is distinguished
It is electrically connected to the draining of the third NMOS tube, the top crown of the third capacitance, the input terminal of the third phase inverter and institute
State the output end of the second phase inverter；The grid of the third NMOS tube is electrically connected to the 4th of the capacitance control of discharge module
The drain electrode of NMOS tube, the source electrode ground connection of the third NMOS tube；The bottom crown of the third capacitance is grounded；The third phase inverter
Output end be respectively electrically connected to the input terminal of second phase inverter, the input terminal of the 5th phase inverter, described second
The drain electrode of NMOS tube and the bottom crown of second capacitance；The input terminal of second phase inverter is respectively electrically connected to the described 5th
The input terminal of phase inverter, second capacitance bottom crown and second NMOS tube drain electrode；5th phase inverter it is defeated
Enter the drain electrode that end is respectively electrically connected to the bottom crown and second NMOS tube of second capacitance；The upper pole of second capacitance
Plate is electrically connected to power supply, and the bottom crown of second capacitance is electrically connected to the drain electrode of second NMOS tube；2nd NMOS
The source electrode of pipe is grounded, and the grid of second NMOS tube is respectively electrically connected to the top crown and the described 4th of the 4th capacitance instead
The output end of phase device；The bottom crown of 4th capacitance is grounded；The input terminal of 4th phase inverter is respectively electrically connected to described
The output end of 0th phase inverter and the output latch module；The input terminal of 0th phase inverter is electrically connected to the 0th electricity
One end of resistance.
5. power-on and power-off reset signal generating circuit according to claim 4, which is characterized in that the output latch module packet
It includes：One Z-buffer, one the 7th phase inverter, one the 0th rest-set flip-flop and one first buffer；The Z-buffer it is defeated
Enter the input terminal and the 0th phase inverter for holding the 4th phase inverter for being respectively electrically connected to the upper and lower reset control module
Output end, the output end of the Z-buffer are electrically connected to the ends R of the 0th rest-set flip-flop；7th phase inverter it is defeated
Enter end be respectively electrically connected to the 0th NAND gate output end and the described 0th or door the second input terminal, the 7th reverse phase
The output end of device is electrically connected to the ends S of the 0th rest-set flip-flop；The output end Q of 0th rest-set flip-flop is electrically connected to described
The input terminal of first buffer；The output end of first buffer is electrically connected the defeated of the power-on and power-off reset signal generating circuit
Go out.
6. power-on and power-off reset signal generating circuit according to claim 5, which is characterized in that upon power-up, the power supply
After voltage rises to respective threshold, the points of common connection voltage of the drain electrode of first PMOS tube and the drain electrode of the 6th NMOS tube
Height is set, the grid voltage of third NMOS tube drags down, the bottom crown voltage of the bottom crown of first capacitance and second capacitance
It is increased with the supply voltage, and when the supply voltage is more than the maximum value of PMOS tube threshold voltage and NMOS tube threshold voltage
When, the 0th PMOS tube charges to the zero capacitance, and the zero capacitance top crown voltage increases, the 0th phase inverter
Output end voltage set low, the output end voltage of the 4th phase inverter set it is high and to the 4th capacitor charging, while described second
The input terminal voltage of phase inverter is set low；Then, the output end voltage of second phase inverter is set high and is filled to the third capacitance
Electricity, while the output end voltage of the NAND gate is set low, and the output end voltage of the 7th phase inverter sets height, the 0th RS
The S terminal voltages of trigger are set high so that the output of the power-on and power-off reset signal generating circuit is as the supply voltage increases
And increase, at the same time, described or door output end voltage is set low, and the S terminal voltages of first rest-set flip-flop set low and make
The input terminal voltage of first phase inverter sets height, so that the bottom crown voltage pull-down of first capacitance, the described 0th
NMOS tube turns off, to realize without DC power.
7. power-on and power-off reset signal generating circuit according to claim 5, which is characterized in that in power up, work as institute
State the top crown voltage difference of the top crown voltage of zero capacitance, the top crown voltage of the 4th capacitance and the third capacitance
Rise to the threshold voltage of NMOS tube in NMOS tube, second NMOS tube and second buffer in the 0th phase inverter
When, the output voltage of the power-on and power-off reset signal generating circuit overturns makes electrification reset terminate for height, is simultaneously stopped hair
Send power-on reset signal.
8. power-on and power-off reset signal generating circuit according to claim 5, which is characterized in that when instantly electric, the power supply
After voltage is down to respective threshold, the points of common connection voltage of the drain electrode of first PMOS tube and the drain electrode of the 6th NMOS tube
It drags down, the grid voltage of the third NMOS tube sets height；Then, the input terminal voltage of second buffer is set low, and described
The output end voltage of zero NAND gate sets height, and the S terminal voltages of first rest-set flip-flop set high and make first phase inverter
Input terminal voltage is set low, and then the output end voltage of first phase inverter sets height, while the 0th NMOS tube is connected and makes
The zero capacitance is obtained to discharge to the zero resistance；At the same time, the input terminal voltage of the 0th phase inverter is set low, in turn
The R terminal voltages of 0th rest-set flip-flop are set high so that the output of the power-on and power-off reset signal generating circuit is with the electricity
Source voltage is reduced and is reduced.
9. power-on and power-off reset signal generating circuit according to claim 5, which is characterized in that instantly in electric process, work as institute
When stating the top crown voltage of zero capacitance and being down to the threshold voltage of NMOS tube in the 0th phase inverter, the reset letter up and down
The output voltage of number generation circuit overturns to be low so that lower reset starts, until stopping sending at the end of lower electric process lower electric
Reset signal.
10. a kind of power-on and power-off reset chip, which is characterized in that including the reset up and down described in any one of claim 1 to 9
Signal generating circuit, to realize using metal-oxide-semiconductor cut-in voltage as circuit state switching threshold, and after upper and lower reset comes into force
Disconnect DC channel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511029175.6A CN105406848B (en) | 2015-12-31 | 2015-12-31 | Zero quiescent dissipation power-on and power-off reset signal generating circuit and power-on and power-off reset chip |
Applications Claiming Priority (1)
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110794942A (en) * | 2018-08-03 | 2020-02-14 | 圣邦微电子（北京）股份有限公司 | Reset chip circuit |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106843437B (en) * | 2017-02-08 | 2019-06-21 | 深圳市爱普特微电子有限公司 | A kind of zero quiescent dissipation electrification reset circuit can be used for voltage detecting |
| CN109347464B (en) * | 2018-11-30 | 2020-08-28 | 中国科学院上海微系统与信息技术研究所 | Power-on reset/power-off detection circuit with zero static power consumption and implementation method thereof |
| CN109975600A (en) * | 2019-04-29 | 2019-07-05 | 南京芯耐特半导体有限公司 | A kind of undervoltage detection circuit of zero quiescent dissipation |
| CN111224648B (en) * | 2020-04-23 | 2020-09-04 | 深圳市泛海三江电子股份有限公司 | Power-on and power-off reset control circuit without static power consumption |
| CN111490762B (en) * | 2020-06-23 | 2020-09-29 | 深圳市芯天下技术有限公司 | Novel power-on and power-off reset circuit |
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| CN110794942A (en) * | 2018-08-03 | 2020-02-14 | 圣邦微电子（北京）股份有限公司 | Reset chip circuit |
| CN110794942B (en) * | 2018-08-03 | 2021-07-09 | 圣邦微电子（北京）股份有限公司 | Reset chip circuit |
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