CN105404351A - Current bias circuit - Google Patents
Current bias circuit Download PDFInfo
- Publication number
- CN105404351A CN105404351A CN201510925790.9A CN201510925790A CN105404351A CN 105404351 A CN105404351 A CN 105404351A CN 201510925790 A CN201510925790 A CN 201510925790A CN 105404351 A CN105404351 A CN 105404351A
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- nmos tube
- pmos
- current
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- grid
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- 238000005516 engineering process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Amplifiers (AREA)
- Control Of Electrical Variables (AREA)
Abstract
The invention discloses a current bias circuit comprising a first current mirror, a second current mirror and a bias path. The first current mirror comprises a first PMOS pipe and a second PMOS pipe working as a mirror image to each other; the second current mirror comprises a first NMOS pipe and a second NMOS pipe working as a mirror image to each other; drain currents of the first PMOS pipe are connected with drain currents of the third PMOS pipe and the first PMOS pipe to form a first current path; drain currents of the second PMOS pipe are connected with drain currents of a third NMOS pipe and the second NMOS pipe to form a second current path; the first PMOS pipe and the third PMOS pipe form a first co-source co-grid structure; the second NMOS pipe and the third NMOS pipe form a second co-source co-grid structure; a bias path provides grids from the first bias voltage to the third PMOS pipe; and a current output end of the bias path is grounded via a first resistor. By the use of the current bias circuit, resistance area can be reduced and cost can be lowered.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit), particularly relate to a kind of current biasing circuit.
Background technology
Current biasing circuit is widely used in integrated circuits, as shown in Figure 1, is existing the first current biasing circuit figure; PMOS MP1 and MP2 mirror image composition top current mirror each other in Fig. 1, NMOS tube MN1 and MN2 is mirror image composition bottom current mirror each other, the PMOS of top current mirror and bottom current mirror and NMOS tube are connected to form 2 current paths respectively, the wherein source ground of contact resistance R1, NMOS tube MN1 between the source electrode of NMOS tube MN2 and ground; The drain and gate of NMOS tube MN1 connects the grid of NMOS tube MN2, and tie point is node NBIAS.The grid of PMOS MP1 connects grid and the drain electrode of PMOS MP2, and tie point is that the source electrode of node PBIAS, PMOS MP1 and MP2 is connected supply voltage VDDA.
Loop is formed by PMOS MP1 and MP2 and NMOS tube MN1 and MN2, loop is described as follows: if disconnected from the grid of node PBIAS disconnection and PMOS MP2 with drain electrode, if the grid of PMOS MP1 is input, the drain electrode of the MN2 of PMOS MP2 and NMOS tube is for exporting, then path: be input to PMOS MP1 to NMOS tube MN1 to NMOS tube MN2 and resistance R1 and form positive feedback to output (i.e. In_MP1_MN1_ (MN2+R1) _ out), and path: be input to PMOS MP2 to output (i.e. In_MP2_out) and form negative feedback; Loop be totally positive feedback or negative feedback, determined by above-mentioned two paths, loop will realize stable output, then require that loop is negative feedback, and this needs the ratio of the breadth length ratio by regulating NMOS tube MN1 and NMOS tube MN2 raceway groove and the value of 1:K and resistance R1 to realize.
After supply voltage VDDA powers on, the electric current of the current path be made up of PMOS PM1 and NMOS tube MN1 and the current in proportion of current path be made up of PMOS PM2 and NMOS tube MN2, and the gate source voltage of NMOS tube MN1 and the gate source voltage of NMOS tube MN2 unequal, utilize proportional electric current and gate source voltage difference that the electric current of the current path be made up of PMOS PM1 and NMOS tube MN1 and supply voltage can be made to have nothing to do, also namely form reference current, the electric current of the current path be made up of PMOS PM2 and NMOS tube MN2 because mirror is known also has nothing to do with supply voltage.
The shortcoming of the first current biasing circuit existing is as shown in Figure 1, the electric current of the current path be made up of PMOS PM1 and NMOS tube MN1 and the electric current of current path be made up of PMOS PM2 and NMOS tube MN2 are not very stable, and also namely actual value has larger deviation relative to the value that will set.In order to improve the stability of the electric current in two current paths, existing the second current biasing circuit is as shown in Figure 2 have employed in prior art, on the basis of Fig. 1, the second current biasing circuit adds PMOS MP4 on the path of PMOS MP1 and NMOS tube MN1, and on the path of PMOS MP2 and NMOS tube MN2, add NMOS tube MN4, cascode structure (Cascode) is formed by PMOS MP1 and MP4, wherein the grid of PMOS MP4 and the bias voltage of node PB2 are provided by bias path, bias path is in series by PMOS MP3 and NMOS tube MN3, form cascode structure by NMOS tube MN2 and NMOS tube MN4, wherein NMOS tube MN4 directly selects nativeNMOS to manage, nativeNMOS manages the NMOS tube be directly formed in epitaxial loayer, do not need to make well region, therefore the threshold voltage of nativeNMOS pipe is zero or negative value, also be that nativeNMOS is in the just energy conducting of the grid bias close to 0, so after selecting nativeNMOS pipe, NMOS tube MN4 does not need to arrange bias path separately, is directly connected with the grid of NMOS tube MN1 by the grid of NMOS tube MN4.As shown in Figure 2, the cascode structure of PMOS MP1 and MP4 composition can make the drain voltage of PMOS MP1 stablize, reason is the source voltage that the drain voltage of PMOS MP1 equals PMOS MP4, and the source voltage of PMOS MP4 approximates grid voltage (differing a threshold voltage), and the grid voltage of PMOS MP4 directly connects more constant bias voltage, therefore the drain voltage of PMOS MP1 finally can be made to stablize; In like manner, the cascode structure of NMOS tube MN2 and MN4 composition can make the drain voltage of NMOS tube MN2 stablize.The drain voltage of PMOS MP1 and the drain voltage stabilization energy of NMOS tube MN2 improve the stability of two current paths, finally make the output current consistance of actual output current and setting good.
In Fig. 2 by PMOS MP3 and NMOS tube MN3 form obtain bias path be connected directly between supply voltage and ground GNDA between.The resistance R1 wherein adopted is larger, and the R1 of large resistance can consume the area of circuit, increases cost.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of current biasing circuit, can save resistor area, reduce costs.
For solving the problems of the technologies described above, current biasing circuit provided by the invention comprises: the first current mirror, the second current mirror and bias path.
Described first current mirror comprises the first PMOS and second PMOS of mirror image each other.
Described second current mirror comprises the first NMOS tube and second NMOS tube of mirror image each other.
The drain current of described first PMOS is connected to form the first current path by the drain current of the 3rd PMOS and described first NMOS tube.
The drain current of described second PMOS is connected to form the second current path by the drain current of the 3rd NMOS tube and described second NMOS tube.
The source ground of described first NMOS tube, is connected with the first resistance between the source electrode of described second NMOS tube and ground; The drain and gate of described first NMOS tube all connects the grid of described second NMOS tube.
The source electrode of described first PMOS and the source electrode of described second PMOS all connect supply voltage, and the grid of described first PMOS connects grid and the drain electrode of described second PMOS.
The source electrode of described 3rd PMOS connects the drain electrode of described first PMOS, and the drain electrode of described 3rd PMOS connects the drain current of described first NMOS tube, and the grid of described 3rd PMOS connects the first bias voltage.
The source electrode of described 3rd NMOS tube connects the drain electrode of described second NMOS tube, and the drain electrode of described 3rd NMOS tube connects the drain current of described second PMOS, and the grid of described 3rd NMOS tube connects the second bias voltage.
Described first resistance makes the gate source voltage of the gate source voltage of described first NMOS tube and described second NMOS tube unequal, utilizes the relation of current in proportion of the difference of the gate source voltage between described first NMOS tube and described second NMOS tube and described first current path and described second current path to make described first current mirror and described second current mirror form a stable feedback loop and exports and reference current that supply voltage has nothing to do.
Described first PMOS and described 3rd PMOS form the first cascode structure, and described first cascode structure makes the drain voltage of described first PMOS stablize; Described second NMOS tube and described 3rd NMOS tube form the second cascode structure, and described second cascode structure makes the drain voltage of described second NMOS tube stablize; The current stability of described first current path and described second current path is improved by making the drain voltage of the drain voltage of described first PMOS and described second NMOS tube stablize.
Described bias path provides described first bias voltage to the grid of described 3rd PMOS, the current output terminal of described bias path is by described first resistance eutral grounding, in order to increase the electric current that described first resistance passes through, thus described first resistance is got, and gate source voltage that less value just can obtain between described first NMOS tube needed for described reference current and described second NMOS tube is poor.
Further improvement is, described 3rd NMOS tube selects nativeNMOS to manage, and the grid of described 3rd NMOS tube directly connects the grid of described first NMOS tube.
Further improvement is, described bias path comprises the 4th PMOS and the 4th NMOS tube, the source electrode of described 4th PMOS connects supply voltage, and the grid of described 4th PMOS and drain electrode, the grid of described 3rd PMOS and the drain electrode of described 4th NMOS tube link together; The source electrode of described 4th NMOS tube connects the source electrode of described second NMOS tube, and the grid of described 4th NMOS tube connects the grid of described first NMOS tube.
The present invention has on the basis of the current path of cascade by existing the second, by the electric current of bias path is passed through the first resistance eutral grounding, relative in by direct for the electric current of bias path ground connection, invention increases the electric current of the first resistance, value in order to first resistance required when the first resistance two ends acquisition equivalent voltage can be diminished, diminishing of first resistance can make resistor area saved, so the present invention can save resistor area, reduces costs.
Meanwhile, the electric current of bias path can realize saving resistor area by the first resistance eutral grounding by the present invention, can not produce any impact, so can not increase extra power consumption to two current paths of composition loop.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing the first current biasing circuit figure;
Fig. 2 is existing the second current biasing circuit figure;
Fig. 3 is embodiment of the present invention current biasing circuit figure.
Embodiment
As shown in Figure 3, be embodiment of the present invention current biasing circuit figure.Embodiment of the present invention current biasing circuit comprises: the first current mirror, the second current mirror and bias path.
Described first current mirror comprises the first PMOS MP1 and the second PMOS MP2 of mirror image each other.
Described second current mirror comprises the first NMOS tube MN1 and the second NMOS tube MN2 of mirror image each other.
The drain current of described first PMOS MP1 is connected to form the first current path by the drain current of the 3rd PMOS MP4 and described first NMOS tube MN1.
The drain current of described second PMOS MP2 is connected to form the second current path by the drain current of the 3rd NMOS tube MN4 and described second NMOS tube MN2.
The source ground of described first NMOS tube MN1, is connected with the first resistance R1 between the source electrode of described second NMOS tube MN2 and ground; The drain and gate of described first NMOS tube MN1 all connects the grid of described second NMOS tube MN2.
The source electrode of described first PMOS MP1 and the source electrode of described second PMOS MP2 all meet supply voltage VDDA, and the grid of described first PMOS MP1 connects grid and the drain electrode of described second PMOS MP2.
The source electrode of described 3rd PMOS MP4 connects the drain electrode of described first PMOS MP1, and the drain electrode of described 3rd PMOS MP4 connects the drain current of described first NMOS tube MN1, and the grid of described 3rd PMOS MP4 connects the first bias voltage.
The source electrode of described 3rd NMOS tube MN4 connects the drain electrode of described second NMOS tube MN2, and the drain electrode of described 3rd NMOS tube MN4 connects the drain current of described second PMOS MP2, and the grid of described 3rd NMOS tube MN4 connects the second bias voltage.
Described first resistance R1 makes the gate source voltage of the gate source voltage of described first NMOS tube MN1 and described second NMOS tube MN2 unequal, utilizes the relation of current in proportion of the difference of the gate source voltage between described first NMOS tube MN1 and described second NMOS tube MN2 and described first current path and described second current path to make described first current mirror and described second current mirror form a stable feedback loop and exports and reference current that supply voltage VDDA has nothing to do.
Described first PMOS MP1 and described 3rd PMOS MP4 forms the first cascode structure, and described first cascode structure makes the drain voltage of described first PMOS MP1 stablize; Described second NMOS tube MN2 and described 3rd NMOS tube MN4 forms the second cascode structure, and described second cascode structure makes the drain voltage of described second NMOS tube MN2 stablize; The current stability of described first current path and described second current path is improved by making the drain voltage of the drain voltage of described first PMOS MP1 and described second NMOS tube MN2 stablize.
Described bias path provides described first bias voltage to the grid of described 3rd PMOS MP4, the current output terminal of described bias path is by described first resistance R1 ground connection, in order to increase the electric current that described first resistance R1 passes through, thus described first resistance R1 is got, and gate source voltage that less value just can obtain between described first NMOS tube MN1 needed for described reference current and described second NMOS tube MN2 is poor.
In the embodiment of the present invention, described 3rd NMOS tube MN4 selects nativeNMOS to manage, and the grid of described 3rd NMOS tube MN4 directly connects the grid of described first NMOS tube MN1.
Described bias path comprises the 4th PMOS MP3 and the 4th NMOS tube MN3, the source electrode of described 4th PMOS MP3 connects supply voltage VDDA, and the grid of described 4th PMOS MP3 and drain electrode, the grid of described 3rd PMOS MP4 and the drain electrode of described 4th NMOS tube MN3 link together; The source electrode of described 4th NMOS tube MN3 connects the source electrode of described second NMOS tube MN2, and the grid of described 4th NMOS tube MN3 connects the grid of described first NMOS tube MN1.
Comparison diagram 2 and Fig. 3 known, the embodiment of the present invention is by passing through the first resistance R1 ground connection by the electric current of bias path, make being increased by electric current of the first resistance R1, like this when needing to produce identical voltage at the two ends of the first resistance R1, the value of the first resistance R1 of the embodiment of the present invention can be less, so can save the area of the first resistance R1.In addition, source electrode due to the 4th NMOS tube MN3 is connected to the source electrode of the second NMOS tube MN3, if the electric current of the bias path of the embodiment of the present invention is identical with the value of Fig. 2, because the gate source voltage of the 4th NMOS tube MN3 of the embodiment of the present invention diminishes, at this moment need the width of raceway groove of increase the 4th NMOS tube MN3 and the ratio of length to make the embodiment of the present invention identical with the electric current of the bias path of Fig. 2.Assuming that the electric current of two current paths in Fig. 2 is equal with the electric current of bias path, now the width of the raceway groove of NMOS tube MN1 and MN2 and MN3 and the ratio of length are 1:K:1; If when then needing too in the embodiment of the present invention to make the electric current of the electric current of two current paths and bias path equal, now the width of the raceway groove of NMOS tube MN1 and MN2 and MN3 and the ratio of length need to change to 1:K:K.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (3)
1. a current biasing circuit, is characterized in that, comprising: the first current mirror, the second current mirror and bias path;
Described first current mirror comprises the first PMOS and second PMOS of mirror image each other;
Described second current mirror comprises the first NMOS tube and second NMOS tube of mirror image each other;
The drain current of described first PMOS is connected to form the first current path by the drain current of the 3rd PMOS and described first NMOS tube;
The drain current of described second PMOS is connected to form the second current path by the drain current of the 3rd NMOS tube and described second NMOS tube;
The source ground of described first NMOS tube, is connected with the first resistance between the source electrode of described second NMOS tube and ground; The drain and gate of described first NMOS tube all connects the grid of described second NMOS tube;
The source electrode of described first PMOS and the source electrode of described second PMOS all connect supply voltage, and the grid of described first PMOS connects grid and the drain electrode of described second PMOS;
The source electrode of described 3rd PMOS connects the drain electrode of described first PMOS, and the drain electrode of described 3rd PMOS connects the drain current of described first NMOS tube, and the grid of described 3rd PMOS connects the first bias voltage;
The source electrode of described 3rd NMOS tube connects the drain electrode of described second NMOS tube, and the drain electrode of described 3rd NMOS tube connects the drain current of described second PMOS, and the grid of described 3rd NMOS tube connects the second bias voltage;
Described first resistance makes the gate source voltage of the gate source voltage of described first NMOS tube and described second NMOS tube unequal, utilizes the relation of current in proportion of the difference of the gate source voltage between described first NMOS tube and described second NMOS tube and described first current path and described second current path to make described first current mirror and described second current mirror form a stable feedback loop and exports and reference current that supply voltage has nothing to do;
Described first PMOS and described 3rd PMOS form the first cascode structure, and described first cascode structure makes the drain voltage of described first PMOS stablize; Described second NMOS tube and described 3rd NMOS tube form the second cascode structure, and described second cascode structure makes the drain voltage of described second NMOS tube stablize; The current stability of described first current path and described second current path is improved by making the drain voltage of the drain voltage of described first PMOS and described second NMOS tube stablize;
Described bias path provides described first bias voltage to the grid of described 3rd PMOS, the current output terminal of described bias path is by described first resistance eutral grounding, in order to increase the electric current that described first resistance passes through, thus described first resistance is got, and gate source voltage that less value just can obtain between described first NMOS tube needed for described reference current and described second NMOS tube is poor.
2. current biasing circuit as claimed in claim 1, it is characterized in that: described 3rd NMOS tube selects nativeNMOS to manage, the grid of described 3rd NMOS tube directly connects the grid of described first NMOS tube.
3. current biasing circuit as claimed in claim 1, it is characterized in that: described bias path comprises the 4th PMOS and the 4th NMOS tube, the source electrode of described 4th PMOS connects supply voltage, and the grid of described 4th PMOS and drain electrode, the grid of described 3rd PMOS and the drain electrode of described 4th NMOS tube link together; The source electrode of described 4th NMOS tube connects the source electrode of described second NMOS tube, and the grid of described 4th NMOS tube connects the grid of described first NMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510925790.9A CN105404351B (en) | 2015-12-14 | 2015-12-14 | Current biasing circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510925790.9A CN105404351B (en) | 2015-12-14 | 2015-12-14 | Current biasing circuit |
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| CN105404351A true CN105404351A (en) | 2016-03-16 |
| CN105404351B CN105404351B (en) | 2017-09-22 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105786081A (en) * | 2016-03-30 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN106774593A (en) * | 2016-12-29 | 2017-05-31 | 北京兆易创新科技股份有限公司 | A kind of current source |
| CN106909193A (en) * | 2017-03-16 | 2017-06-30 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN106953610A (en) * | 2017-03-23 | 2017-07-14 | 哈尔滨理工大学 | A Rail-to-Rail Operational Amplifier Introducing Negative Resistance Input Tube Structure |
| CN107820031A (en) * | 2017-11-16 | 2018-03-20 | 上海易密值半导体技术有限公司 | A kind of cmos image image element circuit |
| CN107831816A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | Internal electric source generation circuit in reference current generating circuit |
| CN109274353A (en) * | 2018-09-29 | 2019-01-25 | 上海华虹宏力半导体制造有限公司 | Ring oscillator |
| CN110336558A (en) * | 2019-07-10 | 2019-10-15 | 深圳市锐能微科技有限公司 | Oscillating circuit and integrated circuit |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US11791804B2 (en) | 2022-03-11 | 2023-10-17 | Changxin Memory Technologies, Inc. | Circuit for generating bias signal and clock input circuit |
| US12217818B2 (en) | 2022-03-11 | 2025-02-04 | Changxin Memory Technologies, Inc. | Bias generation circuit and memory circuit |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105786081A (en) * | 2016-03-30 | 2016-07-20 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
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| CN106774593A (en) * | 2016-12-29 | 2017-05-31 | 北京兆易创新科技股份有限公司 | A kind of current source |
| CN106909193A (en) * | 2017-03-16 | 2017-06-30 | 上海华虹宏力半导体制造有限公司 | Reference voltage source circuit |
| CN106953610A (en) * | 2017-03-23 | 2017-07-14 | 哈尔滨理工大学 | A Rail-to-Rail Operational Amplifier Introducing Negative Resistance Input Tube Structure |
| CN107831816A (en) * | 2017-09-29 | 2018-03-23 | 上海华虹宏力半导体制造有限公司 | Internal electric source generation circuit in reference current generating circuit |
| CN107820031A (en) * | 2017-11-16 | 2018-03-20 | 上海易密值半导体技术有限公司 | A kind of cmos image image element circuit |
| CN109274353A (en) * | 2018-09-29 | 2019-01-25 | 上海华虹宏力半导体制造有限公司 | Ring oscillator |
| CN110336558A (en) * | 2019-07-10 | 2019-10-15 | 深圳市锐能微科技有限公司 | Oscillating circuit and integrated circuit |
| CN110336558B (en) * | 2019-07-10 | 2024-02-13 | 深圳市锐能微科技有限公司 | Oscillator circuit and integrated circuit |
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| Publication number | Publication date |
|---|---|
| CN105404351B (en) | 2017-09-22 |
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