CN105391670B - Apparatus and method for performing non-orthogonal multiplexing - Google Patents

Abstract

The present disclosure relates to an apparatus and method for performing non-orthogonal multiplexing. An apparatus is disclosed that includes circuitry configured to spread one or more symbols into a spread signal having a predetermined number of bits using one or more orthogonal codes. The amplitude of the extension signal is modified by one or more layer coefficients and the extension signal is multiplexed into the layered transmission signal.

Description

Apparatus and method for performing non-orthogonal multiplexing

Cross reference to related patent applications

This application claims benefit of a prior filing date of U.S. provisional application 62/040,671, having a common list of inventors with this application and filed at the U.S. patent and trademark office on 8/22/2014, which is incorporated herein by reference in its entirety. Further, this application incorporates by reference the entire contents of U.S. provisional application 62/052,291, having the same column name inventor as this application and filed at the U.S. patent and trademark office on 9/18 2014 and claiming the benefit of the prior filing date thereof.

Technical Field

The present disclosure relates to communication utilizing Orthogonal Frequency Division Multiplexing (OFDM) for communication, and more particularly, to a multiplexing method.

Background

Recently, other wireless communication devices have been developed in addition to existing mobile phones. It is estimated that by 2020, the demand for wireless communication resources will be thousands of times greater than current wireless communication demands, which results in a demand for new wireless communication resources, which is limited by the limitations in existing wireless communication technologies. In the 3GPP international standards for wireless communication, a fifth generation (5G) standard has been developed, which further improves frequency utilization efficiency to meet the increasing demand for wireless communication systems.

In the current LTE/LTE-a, Orthogonal Frequency Division Multiplexing (OFDM) is employed, and multiplexing is performed with orthogonality in the frequency domain. Further, carrier aggregation is used to increase wireless capacity by widening a bandwidth, but does not solve the problem of radio wave resource exhaustion.

In some cases, the modulation order per subcarrier in OFDM is increased in order to increase the total number of multiplexed symbols. For example, LTE uses 16QAM (quadrature amplitude modulation) and LTE-a uses 256 QAM. In the case of LTE-a, the total number of bits transmitted per subcarrier increases to eight, but the distance between symbols decreases, thus requiring a higher energy per bit to noise power spectral density ratio (E)_b/N₀) To maintain a predetermined physical layer bit error rate (PHY BER).

Other multiplexing methods have been introduced to address the problems arising from increasing the number of bits modulated per subcarrier, including exploiting the orthogonality relationship between modulation symbols, including frequency, time and code. For example, OFDM is associated with orthogonal frequencies and CDMA is associated with orthogonal codes. In LTE, now considered to be the fifth generation (5G), a filter bank multi-carrier (FBMC) modulation method is used, which employs wavelet OFDM. FBMC modulation makes a Cyclic Prefix (CP) unnecessary by using time orthogonality and frequency orthogonality together. Furthermore, a guard band is not necessary, since the radiation out of the band is very low. FBMC modulation allows a greater number of User Equipments (UEs) to use the same bandwidth; however, the amount of increase obtained by eliminating CP and guard band is at most ten percent, which is insufficient to accommodate the growing demand for wireless communication systems.

In addition, non-orthogonal multiple access (NOMA) is also considered to solve the problems due to the increased demand of wireless communication systems. NOMA allows the multiplexed signal to be separated at the receiver based on differences in signal-to-noise ratio (SNIR) and the transmitted signal to be multiplexed based on amplitude. For example, two signals may be multiplexed into a first layer and a second layer, and the transmission power of the multiplexed signal is determined based on SNIRs that implement the first layer and the second layer at a receiver that meets an expected BER. At the receiver, the multiplexed layers are sequentially recovered by subtracting the demodulated signal from the received signal. NOMA allows a larger amount of multiplexing, but the lower signal layer causes interference with higher layers, which results in an overall increase in transmission power, which may cause difficulties for terminal devices with limited transmission power. For example, two to three multiplex layers are considered to be actual at this time.

In addition, NOMA uses a so-called adaptive modulation method to keep the transmission power in a cell or terminal equipment constant. For example, adaptive modulation allows the modulation amount to be changed based on the SNIR at the receiver. However, the communication speed may be very slow with adaptive modulation depending on the modulation type used, and the frequency utilization efficiency may become even worse.

Disclosure of Invention

In an exemplary embodiment, an apparatus includes circuitry configured to spread one or more symbols into a spread signal having a predetermined number of bits using one or more orthogonal codes. The amplitude of the extension signal is modified by one or more layer coefficients and the extension signal is multiplexed into the layered transmission signal.

In another exemplary embodiment, a method includes spreading one or more symbols into a spread signal having a predetermined number of bits using one or more orthogonal codes; modifying the amplitude of the expanded signal by one or more layer coefficients; multiplexing the spread signal into a layered transmission signal; and recovers the received signal layer by despreading the received signal with one or more orthogonal codes.

In another exemplary embodiment, an apparatus includes circuitry configured to: the highest received signal layer is recovered by despreading the received signal with one or more orthogonal codes, despreading the highest received signal layer with one or more orthogonal codes and multiplying the corresponding spread signal by the associated layer coefficients, and subtracting the despread signal from the received signal to recover one or more lower received signal layers.

The foregoing general description of illustrative embodiments, and the following detailed description thereof, are merely exemplary aspects of the teachings of the present disclosure and are not intended to be limiting.

Drawings

A more complete appreciation of the present disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings.

FIG. 1A is an exemplary block diagram of a transmitter according to some embodiments;

FIG. 1B is an exemplary flow chart of a transmitter modulation process according to some embodiments;

FIG. 2A is an exemplary block diagram of a receiver according to some embodiments;

fig. 2B is an exemplary flow chart of a receiver demodulation process according to some embodiments;

FIG. 3A is an exemplary diagram of multiplexed layers according to some embodiments;

FIG. 3B is an exemplary diagram of multiplexed layers according to some embodiments;

FIG. 4A is an exemplary graph of bit error rate of a physical layer according to some embodiments;

FIG. 4B is an exemplary graph of bit error rate of a physical layer according to some embodiments;

FIG. 5 is an exemplary block diagram of an apparatus according to some embodiments;

FIG. 6 is an exemplary schematic diagram of a data processing system according to some embodiments; and

FIG. 7 is an exemplary diagram of a processor according to some embodiments.

Detailed Description

In the drawings, like numerals designate identical or corresponding parts throughout the several views. Also, as used herein, words that are not limited by numerals generally have the meaning of "one or more" unless otherwise specified. Furthermore, the terms "approximately," "approximately," and similar terms generally refer to a range including values identified within a margin of 20%, 10%, or 5%, as well as any values therebetween.

Aspects of the present disclosure are directed to multiplexing methods for increasing the number of multiplexed symbols for a modulated transmit signal while maintaining a predetermined bit error rate criterion. Embodiments describe applying code division multiplexing with orthogonal codes using non-orthogonal multiple access (NOMA) techniques to increase the total number of multiplexed symbols and frequency utilization efficiency while limiting increases in transmit power.

Fig. 1A is an exemplary block diagram of a transmitter 100 according to some embodiments. The transmitter 100 includes an IFFT block 102 that computes an IFFT for a signal that includes one or more subcarriers. A Cyclic Prefix (CP) is added to the signal at the CP module 104, and a Radio Frequency (RF) front end 106 converts the signal to a radio frequency to be transmitted by an antenna 108.

Fig. 1A also shows a diagram of how the signal structure is constructed and transmitted by the transmitter 100. In some implementations, transmitter 100 includes a transmitter configured to transmit data by utilizing a signal having L_COrthogonal code of bit length converts symbols to have L_CAnd a circuit for correlating the bit-length spread signal. Since the symbols are spread by the orthogonal code, the amplitude of the spread symbols is equal to 1/L of the amplitude of the original symbols_C. In one implementation, the orthogonal codes used to spread the symbols are Walsh codes. Due to the L_CThe orthogonal code of bits comprises L_COne orthogonal code cd₀To cd (L)_C-1), thus by passing through L_COne orthogonal code cd₀To cd (L)_C-1) extension L_CEach of which symbols and adds together the resulting spread symbols to perform the multiplexing. The multiplexed symbols are then multiplied by a first layer coefficient cg0, which results in a symbol having L_CA first layer signal of one symbol.

Next, a second layer signal is obtained by: warp having L_CThe orthogonal code of bits multiplexes the new symbols into the spread symbols, adds the resulting spread symbols together, and multiplies the spread symbols by a second layer coefficient cg1 to modify the amplitude of the symbols, which results in a symbol having L_CA layer two signal of one symbol. The second layer signal is then multiplexed onto the first layer signal and totals (L)_CX M) symbols are multiplexed by repeatedly performing the processes of spreading, amplitude modification, and multiplexing onto the previous layer up to the M-th layer.

According to one implementation, each of the M layers is spread with the same orthogonal code and one or the M layers may not be orthogonal with respect to the other layers. To be able to separate the M layers at the receiver, the amplitude of the layers is modified, which is called non-orthogonal multiple access (NOMA). In the present disclosure, the layer system numbers cg0 through cg (L)_C-1) is used to modify the amplitude value of each other M layers. Details regarding determining layer coefficients will be discussed further herein.

Once the layer 1 to M signals are multiplexed, the signals are allocated to subcarriers. Since each signal up to the Mth layer has passed through L_CBit extension, thus L_CEach of the bits is allocated to a corresponding subcarrier of the OFDM, which results in (L)_Cx M) symbols are multiplexed to L_COn the subcarriers. Additional M-layer signals are allocated to the subcarriers until all subcarriers of the transmitter 100 are allocated. In one implementationIn, the total number of subcarriers is N_subAnd the total number of symbols that can be transmitted by one IFFT of the transmitter 100 is represented by the following equation:

for example, the total number of transmission symbols may be increased by increasing the number of layers of the layered transmission signal and/or increasing the number of subcarriers.

The total number of bits included in a symbol, N, that can be transmitted by one IFFT of the transmitter 100_bCan be expressed as follows:

fig. 1B is an exemplary flow diagram of a transmitter modulation process 120 according to some embodiments. In one example, the number of subcarriers N that can be processed by the IFFT block 102 of the transmitter 100_subEqual to 2048. Furthermore, the total number of layers M associated with the symbols to be multiplexed is equal to 4.

In step S122, the current tier value is initialized to a value of one. In step S124, L is utilized_CBit-length orthogonal codes are used to spread the symbols to be transmitted. In one implementation, the orthogonal code used to modulate the transmitted symbols is of length L of 4 bits_CAnd the orthogonal codes can be described as follows:

cd0＝(1，1，-1，-1) (3.1)

cd1＝(1，-1，-1，1) (3.2)

cd2＝(1，-1，1，-1) (3.3)

cd3＝(1，1，1，1) (3.4)

once the orthogonal code is applied to the symbols, the resulting symbols are added together. For example, as shown in fig. 1A, data0, data1, data2, and data3 represent spreading symbols multiplexed by orthogonal codes cd0, cd1, cd2, and cd 3.

In step S126, the spread symbol is multiplied by the first layer coefficient cg0, which results in a symbol having L_CA first layer signal of one symbol. In one implementation, the layer system numbers cg0 through cg (L)_C-1) is used to modify the amplitude value of each other M layers. For example, since the layers are non-orthogonal with respect to each other, to separate the M layers of the transmitted signal at the receiver, each of the layers is multiplied by a value cg0 to cg (L) that distinguishes the layers from each other_C-1). To reduce interference between M layers, the cg value for each of these layers is determined relative to the following equation such that the highest layer coefficient is greater than the sum of one or more remaining lower layer coefficients:

cg(M-1)＞cg(M-2)+…+cg0 (4)

for example, according to the example shown in fig. 1A, the values of cg0 through cg3 are determined as follows:

cg0＝1 (5.1)

cg1＝(1+dlt) (5.2)

cg2＝(1+dlt)*2 (5.3)

cg3＝(1+dlt)*4 (5.4)

the coefficient cg0 corresponds to a coefficient applied to a first layer symbol, cg1 is applied to a second layer symbol, cg2 is applied to a third layer symbol, and cg3 is applied to a fourth layer symbol. The optimum value dlt of the coefficient difference factor is determined based on the Bit Error Rate (BER). For example, the interference between any two symbols may be reduced by increasing the value of the coefficient difference factor, dlt. Furthermore, the value of dlt is less than 1(dlt < 1).

The determination of the amplitude values of the symbols described by equations (5.1) to (5.4) can be explained more generally by way of example of a Downlink (DL) from the base station to the terminal. For example, the total number of multiplexed layers is equal to N, N is an integer and greater than two, and the amplitude of the first layer is referred to as S1, and the amplitude of each of the layers up to the nth layer can be expressed by the following equation:

a first layer: s1 ═ S1 (6.1)

A second layer: s2 ═ S1+ dlt (6.2)

Third to nth layers: SM 2^N-2(S1+dlt) (6.3)

Therefore, the amplitude of the signal resulting from multiplexing all layers can be represented by:

thus, equations (5.1) to (5.4) describing the values of the layer system illustrate an exemplary implementation of equations (6.1) to (6.3), where S1 equals 1.

In step S127, the current layer is multiplexed onto the previous layer. For example, the second layer is multiplexed onto the first layer, the third layer is multiplexed onto the first two layers, and the fourth layer is multiplexed onto the first three layers. If the current layer is equal to one, step S127 is skipped and the process proceeds to step S128.

In one implementation, based on equation (7) and the above relationship, the total amplitude produced by all multiplexed layers is 8 × (S1+ dlt), which is about eight times greater than the signal amplitude produced when multiplexing is not performed. The increased amplitude means that the transmit power used to transmit the layered, multiplexed signal also increases. According to some implementations, the transmit power is increased by a factor of N when performing N multiplexing iterations as compared to implementations in which multiplexing has not been performed.

According to embodiments described herein, the amplitude added by the multiplex layer may be mitigated due to the amplitude reduction that occurs when the signal is expanded at step S122. For example, when a signal is extended to L having a total number of bits as many as the total number of transmitted signals_CMultiple bits, each of which has an amplitude of 1/L of the amplitude of each signal_C. Therefore, equation (7) can be rewritten as follows:

due to the amplitude of the signal being 1/L during the signal expansion of step S122_CFor the factor reduction, the total amplitude of the transmitted signal is therefore also 1/L_CIs a factor reduction. Thus, the transmitter circuit may be configured to modify the total transmit power based on at least one of modifying the sum of the layer coefficients or the predetermined number of bits of the extension signal. SNIR of signal at receiver independent of amplitudeReduced influence because of L accumulation as inverse expansion is performed_CThe bits form one symbol. For example, if the extension is by a length L_CAs performed by the 4 code and based on equation (8) it is determined that the total transmit power is equal to 4, then there is no increase in transmit power due to multiplexing the signal layers together.

In step S128, it is determined whether the current layer value is equal to the total number of M layers. If the current layer value is not equal to M, resulting in "No" at step S128, step S132 is performed. At step S132, the current tier value is incremented by one, and the process returns to step S124 to repeat steps S124, S126, S127, and S128 for the subsequent tier. As shown in fig. 1A, this process repeats until the fourth layer has been multiplexed onto the previous three layers by adding each bit of the extension signal from the fourth layer including data12, data13, data14, and data15 to the bits from the previous three layers. Otherwise, if the current tier value is equal to M, resulting in "YES" at step S128, step S130 is performed.

In step S130, the multi-layered multiplexed signal is allocated to one or more subcarriers. For example, four bits including data from the first to fourth layers are allocated to the 0 th to 3 rd subcarriers, which results in sixteen symbols being multiplexed onto the four subcarriers. Transmitter modulation process 120 is repeated for 512(═ 2048/4) groups of subcarriers, which results in an Inverse Fast Fourier Transform (IFFT) multiplexing of 8192 symbols for transmitter 100 according to equation (1)

In an implementation where Quadrature Phase Shift Keying (QPSK) is performed on one symbol, the number of bits N in one symbol_bEqual to two. Thus, eight bits are multiplexed per subcarrier, which is equal to the number of transmit bits used for 256 quadrature amplitude modulation orthogonal frequency division multiplexing (QAM-OFDM).

Fig. 2A is an exemplary block diagram of a receiver 200 according to some embodiments. The receiver 200 includes an antenna 202 that receives the signal, an RF front end 204 that converts the incoming RF signal to baseband, and a CP removal module 206 that removes the CP from the incoming signal. The received signal is then returned to the frequency domain at a Fast Fourier Transform (FFT) block 208. In one implementation, the resulting frequency domain signal is represented by Rx M.

Fig. 2A also shows a diagram illustrating how the layered, multiplexed signal is received and recovered by the receiver 100. In some implementations, receiver 200 includes circuitry configured to perform a demodulation process that includes despreading a received signal to recover transmitted symbols. Using orthogonal codes cd0 to cd (L)_C-1) for each group L_CThe subcarriers perform despreading, which recovers L from the Mth layer_CThe received symbols. And then uses orthogonal codes cd 0-cd (L)_C-1) re-spread the received symbols and the resulting spread signal is multiplied by a factor cgM. After multiplication, the resulting signal is subtracted from the original signal Rx M and a signal Rx (M-1) is obtained. Next, a despreading process using orthogonal codes cd0 through cd (M-1) is again applied to signal Rx (M-1) and another set L for the (M-1) th layer is obtained_CA symbol. The demodulation process is then repeated until layer 1 is reached and all transmitted symbols are demodulated. Receiver 200 then repeats the demodulation process to recover the transmitted symbols assigned to each subcarrier.

Fig. 2B is an exemplary flow diagram of a receiver demodulation process 220 according to some embodiments. In one example, the number of subcarriers N that may be processed by FFT block 208 of receiver 200_subEqual to 2048. Furthermore, the total number M of layers associated with the symbols to be recovered is equal to 4.

At step S222, the current tier value is initialized to a value M, which in one example is 4. In step S224, L is started_CThe received signals Rx M associated with subcarriers SC0 through SC3 are despread by orthogonal codes cd0, cd1, cd2, and cd3 to recover the spread symbols associated with the highest layer of the transmitted signal. As shown in fig. 2A, data (n +12), data (n +13), data (n +14), and data (n +15) are recovered by performing inverse spreading on a reception signal Rx 4, where the reception signal Rx 4 is a spread data signal allocated to the fourth or highest layer of the transmission signal.

In step S226, the recovered signal is again spread with orthogonal codes cd0, cd1, cd2, and cd3 and multiplied by a coefficient cg 3. As discussed previously, the receive signal Rx M comprises a signal spread over layer 1 to layer M by using the same orthogonal code as the signal was spread, which means that the layers are non-orthogonal with respect to each other. By modifying the amplitude, each layer can be recovered at the receiver by applying the corresponding coefficients used by the transmitter 100. As previously discussed, when the mth layer is inversely extended to reduce interference between the mth layer and the 1 st to (M-1) th layers, the layer coefficients are determined based on equation (4). The resulting highest received signal layer multiplied by cg3 is then subtracted from the Rx 4 signal to obtain the Rx 3 signal comprising the remaining lower signal layers. For example, the Rx 3 signal includes extension signals associated with the first, second, and third layers.

In step S228, it is determined whether the current tier value is equal to one. If the current layer value is not equal to one, resulting in "no" at step S228, step S230 is performed. At step S230, the current layer value is decremented by one, and the process returns to step S224 to repeat steps S224, S226, and S228 in order to recover the received symbol associated with the next lowest layer. As shown in fig. 2A, the process repeats until the transmitted symbols of the third, second, and first layers are all recovered. Otherwise, if the current tier value is equal to 1, resulting in "yes" at step S228, the process terminates. The receiver demodulation process 400 is performed on all subcarriers to recover all transmitted data, which for the example described herein includes 512 groups of four subcarriers.

Fig. 3A and 3B are exemplary diagrams of multiplexed layers resulting from a transmitter modulation process 120, according to some embodiments. Fig. 3A illustrates an implementation in which the first and second layers employ QPSK multiplexed with the same phase. In fig. 3B, the second layer is added to the first layer at a 45 degree offset. In some embodiments, the offset is added to each layer of the multiplexed signal every other layer. For example, the fourth and sixth layers are also offset by 45 degrees. For layers to which offset is applied, the layer coefficient cg is complex, resulting in a reduction in the total amplitude of the offset layer and a reduction in the transmission power when compared to a multiplexed signal to which offset is not applied.

FIG. 4A is an article according to some embodimentsExemplary plots of bit error rate ber (phy ber) for physical layers. The graph shows the ratio of the energy per bit to the noise power spectral density (E) of the transmitter 100 and receiver 200 described herein_b/N₀) And include theoretical values for QPSK and 256QAM systems. Further, for the BER curve shown in fig. 4A, the length L is used_C4 Walsh codes and the total number of multiplexing layers equals 4. Furthermore, OFDM with 2048 subcarriers is assumed according to one implementation, and all subcarriers are QPSK modulated. BER curves are illustrated for cases where dlt is equal to 0.2, 0.3, 0.4, and 0.5, showing that BER is improved as the value of dlt increases. When dlt is equal to 0.4, the resulting BER is approximately equal to the BER of QPSK. The graph also includes a BER of 0.5 for dlt, which shows that for values of dlt greater than 0.4, the BER improvement decreases due to saturation. Since the subcarriers are QPSK modulated, the physical layer BER does not decrease to less than the QPSK BER.

Fig. 4B is another exemplary graph of BER of the physical layer according to some embodiments. Fig. 4B also includes theoretical values for QPSK and 256QAM systems and at length L_CBER curves for the transmitter 100 and the receiver 200 in the case of 4 Walsh codes, four multiplex layers, and values of dlt of 0.2, 0.3, and 0.4. Further, OFDM with 2048 subcarriers is assumed, and all subcarriers are QPSK modulated. Fig. 4B also includes an implemented offset BER curve where dlt is equal to 0.3 and a 45 degree offset is added to the spacer layers (such as the second and fourth layers) and the four layers are multiplexed together according to the previously described process. The offset BER curve is approximately equal to the theoretical QPSKBER curve, but the amplitude of the offset multiplexed signal is 0.2 times less than the amplitude of the multiplexed signal without the offset.

Both fig. 4A and 4B show that the communication capacity corresponding to the capacity of 256QAM can be at E for QPSK_b/N₀Corresponding E_b/N₀And (4) at the value. For example, using 256QAM-OFDM, to implement 10^-3PHYBER, Environment E_b/N₀Approximately equal to 18 dB. However, according to the embodiments described herein, 10^-3BER can be in the environment of about 7dBE_b/N₀And (4) performing the following steps. According to some implementations, the urban environment has an E of 10 to 15dB_b/N₀Value, which means that 256QAM may not be used. However, as the embodiments described herein ensure that an E of about 7dB can be maintained_b/N₀While achieving a transmission rate corresponding to 256QAM, the frequency utilization efficiency can be quadrupled and be increased to have E of 10 to 15dB_b/N₀The signal may be successfully transmitted in urban areas of value.

Further, the receiver 200 performs inverse spreading and subtraction on the multiplexed layers of the received signal, and based on the determination of the layering coefficient cg described earlier, interference between the layers is reduced. Further, since signal information may be contained only in the phase, PSK modulation may be used for each layer higher than or equal to the second layer. For example, QPSK corresponds to 4 PSK. By using Phase Shift Keying (PSK) for the second and higher layers, the multi-level modulation does not interfere with the first layer.

Employing PSK for one or more layers of the multiplexed signal allows a greater total number of symbols to be communicated through one IFFT at transmitter 100 and one FFT at receiver 200. For example, in the case where M is equal to four layers, QPSK is applied to each of the second to fourth layers and 16QAM is applied to the first layer, resulting in transmission of 13 bits per subcarrier, which corresponds to 8192 QAM. The PHY BER associated with a multiplexed signal having 13 bits per subcarrier is greater than the PHY BER for QPSK, but also less than the BER for QAM signals.

According to some embodiments, the multiplexing is performed simultaneously with increasing the amplitude of each signal layer, resulting in an increase in peak-to-average power ratio (PAPR). The increased PAPR of the multiplexed signal may make more important the linearity of a transmit Power Amplifier (PA) in the transmitter 100. For example, when there is no offset to a single multiplexed signal with OFDM, the PAPR is 8.8 dB. For the case where four layers are multiplexed together according to the process described herein, the PAPR is about 9.8dB, resulting in a PAPR increase of 1 dB. The increase in PAPR due to the four multiplexing layers does not cause the base station transmitting the Downlink (DL) signal to exceed the maximum transmit power, but the terminal device (such as a cellular phone or other mobile device) may not be able to accommodate the increased PAPR. In some implementations, problems at the terminal due to PAPR increase may be mitigated by increasing the maximum transmit power at the terminal device, applying SC-OFDM, further applying distortion compensation, and so on.

According to some embodiments, in which an Uplink (UL) signal is transmitted from a terminal device to a base station, multiple terminal devices use the same subcarrier, which causes the transmitter on the terminal device to control the transmit power so that the signal received at the base station maintains a relationship according to equation (8). By performing the procedures described herein, the transmitter 100 on the terminal device may reduce the total number of subcarriers when transmitting the multiplexed signal so that the terminal device may not need to perform power control operations. For example, in LTE, the minimum transmission size includes a set of 12 subcarriers per Resource Block (RB). When the subcarrier modulation is performed with QPSK, 24 bits may be transmitted, and when the subcarrier modulation is performed with 16QAM, 48 bits may be transmitted.

In contrast, according to embodiments described herein, transmitter 100 may transmit 32 bits when four subcarriers are allocated to each terminal device and four iterations of transmitter modulation process 120 are performed with QPSK and 8 bits per subcarrier to multiplex the four layers together. Also, 52 bits may be transmitted when the modulation scheme includes 16QAM for the first layer and 8PSK for the second to fourth layers and has 13 bits per subcarrier. In this example, three terminal devices may be allocated to one resource block, which triples the total capacity of the resource block, since each terminal device uses only four subcarriers of the 12 subcarrier resource block. Thus, by performing the hierarchical multiplexing process described herein to reduce the subcarrier allocation to each terminal device, a greater number of signals can be multiplexed and transmitted by the terminal devices without having to limit the transmit power.

According to the embodiments described herein, frequency utilization efficiency can be improved by sequentially multiplexing signals generated by orthogonal multiplexing using orthogonal codes while modifying the amplitude of the signals. By performing the procedures described herein, a transmission rate corresponding to 256QAM can be achieved while maintaining a PHY BER value corresponding to a PHY BER value for QPSK. Quadrupling the frequency utilization efficiency allows the wireless communication system to accommodate future increases in wireless communication traffic.

A hardware description of an exemplary device 500 for performing one or more embodiments described herein is described with reference to fig. 5. For example, the hardware depicted by FIG. 5 may apply to a cellular base station and/or a terminal device, which may include any type of mobile device that communicates via at least one wireless network. When device 500 is programmed to perform the process-related signal modulation and demodulation described herein, device 500 becomes a dedicated device.

The device 500 includes an RF transceiver 526, the RF transceiver 526 including the components and circuitry of the transmitter 100 and receiver 200 previously described. The transceiver 526 may include a transmit antenna and a receive antenna, or the transmitter 100 and receiver 200 may share a common antenna with associated isolation components, such as a full duplexer. In other implementations, the device 500 may include only the transmitter 100 or only the receiver 200.

The device 500 includes a CPU 500 that performs the processes described herein. Process data and instructions may be stored in memory 502. These processes and instructions may also be stored on a storage media disk 504, such as a Hard Disk Drive (HDD) or portable storage media, or may be stored remotely. Furthermore, the claimed advancements are not limited by the form of computer readable media on which the instructions of the inventive process are stored. For example, the instructions may be stored on a CD, DVD, flash memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk, or any other information processing device in communication with device 500, such as a terminal device and/or a base station.

Moreover, the claimed advancements may be provided as a utility, a background daemon, or a component of an operating system, or a combination thereof, that executes in conjunction with the CPU 500 and an operating system (such as Microsoft Windows, UNIX, Solaris, LINUX, Apple MAC-OS and others known to those skilled in the art).

The CPU 500 may be a Xeron or Core processor from Intel, USA, or an Opteron processor from AMD, USA, or may be other processor types as would be recognized by one of ordinary skill in the art. Alternatively, CPU 500 may be implemented on an FPGA, ASIC, PLD or using discrete logic circuitry as would be recognized by one of ordinary skill in the art. Further, CPU 500 may be implemented as multiple processors working in conjunction in parallel to execute the instructions of the inventive process described above.

The device 500 in fig. 5 also includes a network controller 506, such as an intel ethernet PRO network interface card from intel corporation of america, for interfacing with the network 528. As can be appreciated, the network 528 can be a public network such as the internet or a private network such as a LAN or WAN network or any combination thereof, and can also include PSTN or ISDN sub-networks. The network 528 may also be wired (such as an ethernet network) or may be wireless (such as a cellular network including EDGE, 3G, and 4G wireless cellular systems). The wireless network may also be Wi-Fi, Bluetooth, or any other form of wireless communication known.

The device 500 also includes a display controller 508, such as an LCD monitor, for interfacing with a display 510 of the device 500. A general purpose I/O interface 512 at the device 500 interfaces with a keyboard and/or mouse 514 and a touch screen panel 516 on or separate from the display 510. The general purpose I/O interface 512 also connects to various peripheral devices 518, including printers and scanners.

A general purpose storage controller 524 connects the storage media disk 504 to a communication bus 526 (which may be ISA, EISA, VESA, PCI, etc.) for interconnecting all of the components of the device 500. For the sake of brevity, descriptions of the general features and functions of the display 510, keyboard and/or mouse 514, and the display controller 508, storage controller 524, network controller 506, sound controller 520, and general purpose I/O interface 512 are omitted herein, as these features are well known.

The example circuit elements described in the context of this disclosure may be replaced with other elements and may differ in structure from the examples provided herein. Further, circuitry configured to perform the features described herein may be implemented in multiple circuit units (e.g., chips), or the features may be combined in circuitry on a single chipset, as shown in fig. 6.

Fig. 6 shows a schematic diagram of a data processing system for performing a transmitter modulation process 120 and/or a receiver demodulation process 220, in accordance with some embodiments. The data processing system is an example of a computer in which code or instructions implementing the processes of the illustrative embodiments may be located.

In FIG. 6, data processing system 600 employs a hub architecture including north bridge and memory controller hub (NB/MCH)625 and south bridge and input/output (I/O) controller hub (SB/ICH) 620. The central processing unit 630 is connected to the NB/MCH 625. NB/MCH 625 is also connected to memory 645 via a memory bus and to graphics processor 650 via an Accelerated Graphics Port (AGP). NB/MCH 625 is also connected to SB/ICH620 via an internal bus (e.g., a unified media interface or a direct media interface). CPU processing unit 630 may contain one or more processors and may even be implemented with one or more heterogeneous processor systems.

For example, FIG. 7 illustrates one implementation of CPU 630. In one implementation, instruction register 738 retrieves instructions from cache 740. At least a portion of these instructions are fetched from the instruction register 738 by the control logic 736 and interpreted according to the instruction set architecture of the CPU 630. Some of these instructions may also be directed to register 732. In one implementation, the instructions are decoded in a hardwired approach, and in another implementation, the instructions are decoded in a microprogram that translates the instructions into sets of CPU configuration signals that are applied sequentially on multiple clock pulses. After fetching and decoding the instructions, the instructions are executed using an Arithmetic Logic Unit (ALU)734, which loads values from registers 732 and performs logical and mathematical operations on the loaded values as per the instructions. The results of these operations may be fed back into registers and/or stored in flash memory 740. According to some implementations, the instruction set architecture of the CPU 630 may use a reduced instruction set architecture, a complex instruction set architecture, a vector processor architecture, a very large instruction word architecture. Further, CPU 630 may be based on a Von neumann (Von Neuman) model or Harvard (Harvard) model. The CPU 630 may be a digital signal processor, FPGA, ASIC, PLA, PLD or CPLD. In addition, the CPU 630 may be an Intel or AMD x86 processor; ARM processors, such as IBM's Power architecture processor; a processor of the SPARC architecture of Sun Microsystems or Oracle; or other known CPU architecture.

Referring again to FIG. 6, data processing system 600 may include SB/ICH620 coupled to I/O bus via system bus, Read Only Memory (ROM)656, Universal Serial Bus (USB) port 664, flash binary input/output system (BIOS)668, and graphics controller 658. PCI/PCIe devices may also be coupled to the SB/ICH YYYY through PCI bus 662.

PCI devices may include, for example, Ethernet adapters, add-in cards, and PC cards for notebook computers. Hard disk drive 660 and CD-ROM 666 may use, for example, an Integrated Drive Electronics (IDE) or Serial Advanced Technology Attachment (SATA) interface. In one implementation, the I/O bus may include super I/O (SIO) devices.

In addition, a Hard Disk Drive (HDD)660 and an optical drive 666 may also be coupled to SB/ICH620 via the system bus. In one implementation, keyboard 670, mouse 672, parallel port 678, and serial port 676 can be connected to the system bus by an I/O bus. Other peripherals and devices that may be connected to SB/ICH620 utilize mass storage controllers such as SATA or PATA, Ethernet ports, ISA buses, LPC bridges, SMBus, DMA controllers, and audio codecs.

Furthermore, the present disclosure is not limited to the specific circuit elements described herein, nor is the present disclosure limited to specific sizes and classifications of these elements. For example, the skilled artisan will appreciate that the circuitry described herein may be adjusted based on changes in battery size and chemistry, or based on anticipated requirements of the backup load to be powered.

The functions and features described herein may also be performed by various distributed components of the system. For example, one or more processors may perform these system functions, where the processors are distributed across multiple components communicating in a network. The distributed components may include one or more client and server machines that may share processing in addition to various human interface and communication devices (e.g., display monitors, smart phones, tablet computers, Personal Digital Assistants (PDAs)). The network may be a private network such as a LAN or WAN, or may be a public network such as the internet. Input to the system may be received via direct user input and received in real-time or remotely as a batch process. Further, some implementations may be performed on modules or hardware not identical to those described. Accordingly, other implementations are within the scope of what may be claimed.

The above hardware description is a non-limiting example of corresponding structures for performing the functions described herein. In other alternative embodiments, the processing features according to the present disclosure may be implemented and commercialized as hardware, software solutions, or a combination thereof. Also, instructions corresponding to the transmitter modulation process 120 and/or the receiver demodulation process 220 according to the present disclosure may be stored in a thumb drive (thumb drive) that houses the safety process.

Several implementations have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, more desirable results may be achieved if the steps of the disclosed techniques were performed in a different order, if components in the disclosed systems were combined in a different manner, or if components were replaced or supplemented by other components. The functions, processes, and algorithms described herein may be performed in hardware or software executed by hardware, including a computer processor and/or programmable circuitry configured to execute program code and/or computer instructions to perform the functions, processes, and algorithms described herein. Alternatively, implementations may be performed on modules or hardware not identical to those described. Accordingly, other implementations are within the scope of what may be claimed.

The above disclosure also includes the embodiments listed below.

(1) An apparatus comprising circuitry configured to: the method includes spreading one or more symbols into a spread signal having a predetermined number of bits using one or more orthogonal codes, modifying an amplitude of the spread signal by one or more layer coefficients, and multiplexing the spread signal into a layered transmission signal.

(2) The apparatus of (1), wherein the circuitry is further configured to allocate the layered transmission signal to a predetermined number of subcarriers.

(3) The apparatus of (1) or (2), wherein the predetermined number of subcarriers corresponds to a predetermined number of bits of the extension signal.

(4) The apparatus of any one of (1) to (3), wherein the one or more orthogonal codes are Walsh codes.

(5) The apparatus of any of (1) to (4), wherein the circuitry is further configured to determine the layer coefficients based on a coefficient difference factor of less than one.

(6) The apparatus of any of (1) through (5), wherein the circuitry is further configured to determine a highest layer coefficient to be greater than a sum of one or more remaining lower layer coefficients.

(7) The apparatus of any of (1) to (6), wherein the circuitry is further configured to reduce a physical layer error rate by increasing a coefficient difference factor.

(8) The apparatus of any of (1) to (7), wherein the circuitry is further configured to modify the total transmit power by modifying at least one of a sum of layer coefficients or a predetermined number of bits of the extension signal.

(9) The apparatus of any of (1) to (8), wherein the circuitry is further configured to reduce the total transmit power of the layered transmit signal by adding an offset to at least one of the one or more layer coefficients.

(10) The device of any of (1) to (9), wherein the circuitry is further configured to add an offset to a spacer layer of the layered transmit signal.

(11) The apparatus of any of (1) to (10), wherein the offset is equal to 45 degrees.

(12) The apparatus of any of (1) to (11), wherein the layered transmission signal comprises one or more non-orthogonal signal layers.

(13) The apparatus of any of (1) to (12), wherein the circuitry is further configured to reduce interference between one or more non-orthogonal signal layers by modifying an amplitude of the spread signal with one or more layer coefficients.

(14) The apparatus of any of (1) to (13), wherein the circuitry is further configured to implement quadrature amplitude modulation for a first layer and phase shift keying modulation for a second layer and higher layers of the layered transmit signal.

(15) The apparatus of any of (1) to (14), wherein the circuitry is further configured to allocate signals from one terminal device to four subcarriers of a twelve subcarrier resource block.

(16) The apparatus of any of (1) to (15), wherein the circuitry is further configured to recover a highest received signal layer by despreading the received signal with one or more orthogonal codes.

(17) The apparatus of any of (1) to (16), wherein the circuitry is further configured to re-spread the highest received signal layer with one or more orthogonal codes and multiply the corresponding spread signal by the associated layer coefficient.

(18) The apparatus of any of (1) to (17), wherein the circuitry is further configured to subtract the re-spread signal from the received signal to recover one or more lower received signal layers.

(19) A method, comprising: spreading one or more symbols into a spread signal having a predetermined number of bits using one or more orthogonal codes; modifying the amplitude of the expanded signal by one or more layer coefficients; and multiplexing the spread signal into the layered transmission signal.

(20) An apparatus comprising circuitry configured to: the method includes recovering a highest received signal layer by despreading the received signal with one or more orthogonal codes, despreading the highest received signal layer with one or more orthogonal codes and multiplying the corresponding spread signal by associated layer coefficients, and subtracting the despread signal from the received signal to recover one or more lower received signal layers.

Claims (17)

1. An apparatus for performing non-orthogonal multiplexing comprising:

a circuit configured to

One or more symbols are spread into a spread signal having a predetermined number of bits using one or more orthogonal codes,

modifying the amplitude of the expanded signal by means of one or more layer coefficients, an

The amplitude modified spread signal is multiplexed into the layered transmit signal,

wherein the circuitry is further configured to determine each layer coefficient to be greater than a sum of remaining lower layer coefficients, and

the circuitry is further configured to allocate the layered transmit signal to a predetermined number of subcarriers.

2. The apparatus of claim 1, wherein the predetermined number of subcarriers corresponds to a predetermined number of bits of the extension signal.

3. The apparatus of claim 1, wherein the circuitry is further configured to determine layer coefficients based on a coefficient difference factor that is less than one.

4. The apparatus of claim 3, wherein the circuitry is further configured to reduce a physical layer error rate by increasing a coefficient difference factor.

5. The apparatus of claim 1, wherein the circuitry is further configured to modify the total transmit power by modifying at least one of a sum of layer coefficients or a predetermined number of bits of the extension signal.

6. The apparatus of claim 1, wherein the circuitry is further configured to reduce the total transmit power of the layered transmit signal by adding a phase offset to at least one of the one or more layer coefficients.

7. The apparatus of claim 6, wherein the circuitry is further configured to add a phase offset to alternating layers of the layered transmit signal.

8. The apparatus of claim 7, wherein the phase offset is equal to 45 degrees.

9. The apparatus of claim 1, wherein the layered transmit signal comprises one or more non-orthogonal signal layers.

10. The apparatus of claim 9, wherein the circuitry is further configured to reduce interference between the one or more non-orthogonal signal layers by modifying an amplitude of the spread signal with the one or more layer coefficients.

11. The apparatus of claim 1, wherein the circuitry is further configured to implement quadrature amplitude modulation for a first layer of the layered transmit signal and phase shift keying modulation for a second layer and higher layers of the layered transmit signal.

12. The apparatus of claim 1, wherein the circuitry is further configured to allocate signals from one terminal device to four subcarriers of a twelve subcarrier resource block.

13. The apparatus of claim 1, wherein the circuitry is further configured to recover a highest received signal layer by despreading the received signal.

14. The apparatus of claim 13, wherein the circuitry is further configured to re-spread the highest received signal layer and multiply the corresponding spread signal by the associated layer coefficients to obtain a re-spread signal.

15. The apparatus of claim 14, wherein the circuitry is further configured to subtract the re-spread signal from a received signal to recover one or more lower received signal layers.

16. A method for performing non-orthogonal multiplexing comprising:

spreading one or more symbols into a spread signal having a predetermined number of bits using one or more orthogonal codes;

modifying the amplitude of the expanded signal by one or more layer coefficients; and

the amplitude modified spread signal is multiplexed into the layered transmit signal,

wherein the method further comprises determining each layer coefficient to be larger than the sum of the remaining lower layer coefficients, and

the layered transmission signals are allocated to a predetermined number of subcarriers.

17. An apparatus for performing non-orthogonal multiplexed signal reception comprising:

a circuit configured to

The highest received signal layer is recovered by despreading the received non-orthogonal multiplexed signal with one or more orthogonal codes,

re-spreading the highest received signal layer using one or more orthogonal codes and multiplying the corresponding spread signal by the associated layer coefficients to obtain a re-spread signal, an

Subtracting the re-spread signal from the received non-orthogonally multiplexed signal to recover one or more lower received signal layers,

wherein each layer is larger than the sum of the coefficients of the remaining lower layers.

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