[go: up one dir, main page]

CN105374774A - Semiconductor device and manufacturing method thereof, and electronic device - Google Patents

Semiconductor device and manufacturing method thereof, and electronic device Download PDF

Info

Publication number
CN105374774A
CN105374774A CN201410438573.2A CN201410438573A CN105374774A CN 105374774 A CN105374774 A CN 105374774A CN 201410438573 A CN201410438573 A CN 201410438573A CN 105374774 A CN105374774 A CN 105374774A
Authority
CN
China
Prior art keywords
wafer
interlayer dielectric
barrier layer
bond pad
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410438573.2A
Other languages
Chinese (zh)
Inventor
陈福成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201410438573.2A priority Critical patent/CN105374774A/en
Publication of CN105374774A publication Critical patent/CN105374774A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/03452—Chemical vapour deposition [CVD], e.g. laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/03848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05546—Dual damascene structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05547—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08148—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area protruding from the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/802—Applying energy for connecting
    • H01L2224/80201—Compression bonding
    • H01L2224/80203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and an electronic device. The manufacturing method includes: a first wafer and a second wafer are provided, the first wafer and the second wafer both comprise a substrate, an interlayer dielectric layer positioned on the substrate, and a bonding pad positioned in the interlayer dielectric layer, a barrier layer is formed between the bonding pad and the interlayer dielectric layer, and the barrier layer of the first wafer and/or the second wafer extend(s) to a part of the surface of the interlayer dielectric layer; and the bonding technology is performed so that the first wafer and the second wafer are bonded. According to the manufacturing method, the barrier layer extending to the surface of the interlayer dielectric layer is employed to replace a part of the bonding pad, after the bonding of the wafers, when the position deviation in the horizontal planes of the two wafers changes, the extending length of copper metal can be reduced, the generation of the phenomenon of copper diffusion can be prevented, and the bonding quality and reliability of the device are improved.

Description

A kind of semiconductor device and preparation method thereof and electronic installation
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor device and preparation method thereof and electronic installation.
Background technology
Due to some good characteristics that development and the cmos image sensor (CIS) of large scale integrated circuit have itself, CIS is the study hotspot in technical field of semiconductors always, from adopting the imageing sensor of illumination (FSI) technology above to the imageing sensor adopting backside illumination (BSI) technology, pixel (Pixel) size is more and more less, and photosensitive property is become better and better.3DCIS technology is in current CIS technical foundation, by the technology of two panels wafer bonding, a wafer is manufactured with CIS chip, another wafer is manufactured with data processing chip, then by two panels wafer bonding together, forms 3DCIS chip.The advantage of this production method is chip, and not only Pixel Dimensions is less, and data processing is faster.
But there are some problems as Cu-Cu bonding (WaferlevelCu-Cubonding) technology in the wafer level of the key technology of in 3DIC at present, as shown in Figure 1, after bonding, have a little finedraw at bonded interface, cause two wafer interface can not Direct Bonding together.In theory, when bonding skew (bondingshift) is in certain prescribed limit, upper and lower two panels wafer bonding can reach good effect, as shown in Figure 1.But actual conditions are, due to the inhomogeneities of copper post height, and the skew planar of upper and lower two wafer, cause copper post and copper post when the bonding of high temperature hot pressing, have certain extension phenomenon, even if the bonding skew of upper and lower two wafer is in prescribed limit, Cu is once extend out, copper will be caused to spread, thus make component failure, as shown in Figure 2.
At present, as shown in Figure 3, in the design of copper post (Cupillar), a general consideration copper post is little, and another copper post is large, main because consider that bonding offsets the impact of (shift).But said method can not solve prior art Problems existing completely.
Therefore, the present invention proposes a kind of new manufacture method, to solve problems of the prior art.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range attempting to determine technical scheme required for protection.
In order to overcome current Problems existing, the embodiment of the present invention one provides a kind of manufacture method of semiconductor device, comprising:
First wafer and the second wafer are provided, described first wafer and the second wafer include substrate, be positioned at described suprabasil interlayer dielectric layer and the bond pad being positioned at described interlayer dielectric layer, be formed with barrier layer between described bond pad and interlayer dielectric layer, the described barrier layer of wherein said first wafer and/or described second wafer extends on the surface of the described interlayer dielectric layer of part;
Carry out bonding technology, described first wafer and described second wafer to be engaged.
Further, the method forming described bond pad and barrier layer comprises the following steps:
Step one, form interlayer dielectric layer on the substrate, interlayer dielectric layer described in patterning, to form barrier layer groove in described interlayer dielectric layer, the width of described barrier layer groove is greater than the width of the predetermined bond pad groove formed;
Step 2, etch the described interlayer dielectric layer of described barrier layer bottom portion of groove, to form described bond pad groove;
Step 3, on the sidewall of described barrier layer groove and bond pad groove and formation barrier layer, bottom;
Step 4, employing bond pad material layer fill described bond pad groove;
Step 5, carry out flatening process, stop on the barrier layer surface of described barrier layer bottom portion of groove, to form bond pad.
Further, after described step 5, also comprise interlayer dielectric layer described in etch-back part, make the end face of described interlayer dielectric layer lower than the step of the end face on described barrier layer.
Further, after described step 3 and before step 4, the step of deposited seed layer on described barrier layer is also included in.
Further, the material on described barrier layer is selected from one or more in TaN, Ta, TiN, Ti.
Further, the method selecting electrochemistry to plate forms described bond pad material layer.
Further, the material of described bond pad is metallic copper.
Further, described bonding technology is the Cu-Cu bonding technology between described bond pad.
Further, after described bonding technology, also comprise the step performing annealing.
The embodiment of the present invention two provides a kind of semiconductor device, it is characterized in that, comprising:
First wafer and the second wafer be positioned at above described first wafer, described first wafer and the second wafer include substrate, be positioned at described suprabasil interlayer dielectric layer and the bond pad being positioned at described interlayer dielectric layer, be formed with barrier layer between described bond pad and described interlayer dielectric layer, the described barrier layer of wherein said first wafer and/or described second wafer extends on the surface of the described interlayer dielectric layer of part;
The bond pad phase bonding of described first wafer and described second wafer.
Further, the material of described bond pad is metallic copper.
Further, the material on described barrier layer is selected from one or more in TaN, Ta, TiN, Ti.
The embodiment of the present invention three provides a kind of electronic installation, comprises above-mentioned semiconductor device
In sum, according to manufacture method of the present invention, the barrier layer extended on interlayer dielectric layer surface is used to instead of part bond pad, after wafer bonding, when position offset variation in two panels wafer level face, the length of copper cold draw can be reduced, the generation of copper diffusion phenomena can be stoped simultaneously, and then improve bonding quality and the reliability of device.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the SEM figure of bonded interface under Cu-Cu bonding quality good situations;
Fig. 2 is the SEM figure that Cu extension section occurs after Cu-Cu bonding;
Fig. 3 is the partial structurtes schematic diagram that prior art two wafer engages;
Fig. 4 is the process chart implemented successively according to the method for the embodiment of the present invention one;
Fig. 5 A-5G by implement successively according to the method for the embodiment of the present invention one the generalized section of acquisition device;
Fig. 6 is the generalized section of the semiconductor device according to the embodiment of the present invention two.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, in order to clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or layer time, its can directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or the element that can exist between two parties or layer.On the contrary, when element be called as " directly exist ... on ", " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer time, then there is not element between two parties or layer.Although it should be understood that and term first, second, third, etc. can be used to describe various element, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms be only used for differentiation element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term such as " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., here can be used thus the relation of the element of shown in description figure or feature and other element or feature for convenience of description.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprises the different orientation of the device in using and operating.Such as, if the device upset in accompanying drawing, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " upper and lower two orientations can be comprised.Device can additionally orientation (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, by following description, detailed structure and step are proposed, to explain the technical scheme of the present invention's proposition.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
The method of the Cu-Cu bonding (WaferlevelCu-Cubonding) in prior art in wafer level, as shown in Figure 3, first first wafer 30a and the second wafer 30b is provided, wherein the first wafer 30a and the second wafer 30b includes bonding welding pad 302 and interlayer dielectric layer 301, wherein said bonding welding pad 302 is embedded in interlayer dielectric layer 301, diffusion impervious layer 303 is also formed between described bonding welding pad 302 and interlayer dielectric layer, first wafer 30a and the second wafer 30b, by bonding between respective bonding welding pad, realizes wafer face opposite stacking.In the design of bond pad (copper post), a general consideration copper post is little, and another copper post is large, main because consider the impact that bonding offsets.Due to the inhomogeneities of copper post height, and the skew planar of upper and lower two wafer, cause copper post and copper post when the bonding of high temperature hot pressing, have certain extension phenomenon, even if the bonding skew of upper and lower two wafer is in prescribed limit, Cu, once extend out, will cause copper to spread, thus make component failure.
Therefore need to be improved further, to eliminate the problems referred to above the manufacture method of current described semiconductor device.
Embodiment one
The present invention, in order to solve Problems existing in wafer current bonding process, provides a kind of manufacture method of semiconductor device, is further described described method below in conjunction with accompanying drawing 4 and Fig. 5 A-5G.
Wherein, Fig. 4 shows the process chart of two wafer bondings in the embodiment of the present invention; The method that Fig. 5 A-5G shows the embodiment of the present invention implements the generalized section of obtained device successively.
First, first wafer and the second wafer are provided, described first wafer and the second wafer include substrate, be positioned at described suprabasil interlayer dielectric layer and the bond pad being positioned at described interlayer dielectric layer, be formed with barrier layer between bond pad and interlayer dielectric layer, the described barrier layer of wherein said first wafer and/or described second wafer extends on the surface of the described interlayer dielectric layer of part.In bonding process afterwards, during the offset variation of two wafer bond pads in crystal column surface, reduce the length that bond pad extends, the generation of metal diffusion phenomena can be stoped simultaneously.
Particularly, described substrate at least comprises substrate, and described substrate can at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Alternatively, components and parts and interconnection structure can also be formed with on the substrate.Different according to the device of predetermined formation, different components and parts can be formed, such as, form 3DCIS device if predetermined, then substrate can form CIS chip or data processing chip.
In one example, the method forming described bond pad and barrier layer comprises the following steps:
Step one, with reference to figure 5A, described substrate 500 forms interlayer dielectric layer 501, and interlayer dielectric layer 501 described in patterning, to form barrier layer groove 502 in described interlayer dielectric layer 501.
Particularly, interlevel dielectric deposition 501 in described substrate 500, wherein said interlayer dielectric layer 501 can select conventional dielectric material, in of the present invention one particularly execution mode, be chosen as SiO 2.
One in low-pressure chemical vapor deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG) that the deposition process of described interlayer dielectric layer 501 can select chemical vapour deposition (CVD) (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc. to be formed.Optional chemical vapour deposition (CVD) (CVD) method in the present invention.
Then interlayer dielectric layer 501 described in patterning, to form barrier layer groove 502 in described interlayer dielectric layer 501, the width of described barrier layer groove 502 is greater than the width of the predetermined bond pad groove formed.
Particularly, first on described interlayer dielectric layer 501, form the photoresist layer of patterning or organic distribution layer (Organicdistributionlayer, ODL), siliceous bottom antireflective coating (Si-BARC) and be positioned at the photoresist layer (not shown) of patterning at top, pattern definition on the wherein said photoresist pattern of described barrier layer groove 502, wherein, described barrier layer groove 502 is positioned at the predetermined region forming bond pad, the pattern width of described barrier layer groove 502 is greater than the width of the predetermined bond pad groove formed, the degree of depth of described barrier layer groove 502 is less than the degree of depth of the predetermined bond pad groove formed, exemplarily, the degree of depth of described barrier layer groove 502 equals the thickness on the predetermined barrier layer formed.Then with described photoresist layer for mask layer etching described organic distribution layer, bottom antireflective coating, to form the pattern of barrier layer groove 502, then with described organic distribution layer, bottom antireflective coating for mask, etch described interlayer dielectric layer 501, to form described barrier layer groove 502.
Step 2, with reference to figure 5B, etches the interlayer dielectric layer 501 bottom described barrier layer groove 502, to form bond pad groove 503.
Further, described bond pad groove 503 can select common shape, the generic grooves that the critical size of such as upper and lower opening is the same, or can also select groove wide at the top and narrow at the bottom, is not limited to a certain shape, can arranges as required.The number of described bond pad groove, is also not limited to a certain number range.
Exemplarily, interlayer dielectric layer 501 forms the mask layer that definition has bond pad groove 503 pattern, such as photoresist layer, continue the described interlayer dielectric layer 501 of etching with described mask layer for mask, form bond pad groove 503.
Particularly, select dry etching or wet etching in this step, select C-F etchant to etch described interlayer dielectric layer 501 in the present invention, described C-F etchant is CF 4, CHF 3, C 4f 8and C 5f 8in one or more.
In this embodiment, described dry etching can select CF 4, CHF 3, add N in addition 2, CO 2in one as etching atmosphere, wherein gas flow is CF 410-200sccm, CHF 310-200sccm, N 2or CO 2or O 210-400sccm, described etching pressure is 30-150mTorr, and etching period is 5-120s, is chosen as 5-60s, is chosen as 5-30s.
In one example, step one and step 2 can also exchange, and namely first etch interlayer dielectric layer 501 and form bond pad groove 503, then form described barrier layer groove 502.
Step 3, as shown in Figure 5 C, on sidewall and the formation barrier layer, bottom 504 of described barrier layer groove 502 and bond pad groove 503.
Particularly, described barrier layer 504 is copper diffusion barrier layer, the formation method on described barrier layer 504 can for mainly to select physical vaporous deposition and chemical vapour deposition technique, particularly, evaporation, electron beam evaporation, plasma spray deposition and sputtering can be selected, select plasma spray deposition and sputtering method to form described copper diffusion barrier layer in the present invention.The thickness on described barrier layer 504 is not limited in a certain numerical value or scope, can adjust as required.Further, described barrier layer can also extend on all surfaces of interlayer dielectric layer 501.
Alternatively, described barrier layer 504 material can one or more for being selected from TaN, Ta, TiN, Ti, reduce the RC delay time because dead resistance and parasitic capacitance cause.Alternatively, in of the present invention one particularly execution mode, TaN and/or Ta is selected.
Then the Seed Layer (not shown) of plated metal copper on described barrier layer 504, the deposition process of described Seed Layer can select chemical vapour deposition (CVD) (CVD) method, physical vapour deposition (PVD) (PVD) method or ald (ALD) method etc.
Step 4, with reference to figure 5D, adopts bond pad material layer 505a to fill described bond pad groove.
Alternatively, described bond pad material 505a is copper metal.In of the present invention one particularly execution mode, form Ni metal by the method for Cu electroplating, in described barrier layer groove 502 and bond pad groove 503 He on interlayer dielectric layer 501, form metal copper layer.
In one example, the method selecting electrochemistry to plate (ECP) forms described metallic copper, alternatively, additive can also be used when electroplating, described additive is smooth dose (LEVELER), accelerator (ACCELERATORE) and inhibitor (SUPPRESSOR).
Alternatively, can also comprise the step of annealing after described metallic copper is formed further, annealing can carry out 2-4 hour at 80-160 DEG C, to impel copper crystallization again, crystal grain of growing up, reduces resistance and improves stability.
Step 5, as shown in fig. 5e, carries out flatening process, stops at barrier layer 504 bottom described barrier layer groove 502 on the surface, to form bond pad 505.
Flattening method conventional in field of semiconductor manufacture can be used to realize the planarization on surface.The limiting examples of this flattening method comprises mechanical planarization method and chemico-mechanical polishing flattening method.Chemico-mechanical polishing flattening method is more conventional.Barrier layer 504 on interlayer dielectric layer 501 surface, barrier layer groove 502 both sides can be removed by the process of planarization, and stop at barrier layer 504 bottom barrier layer groove 502 on the surface, retain this partial barrier and carry out Substitute For Partial bond pad, the Seed Layer be simultaneously positioned on the surface, barrier layer 504 bottom barrier layer groove 502 is entirely removed.
Step 6, as illustrated in figure 5f, interlayer dielectric layer 501 described in etch-back part, makes the end face of described interlayer dielectric layer 501 lower than the end face of described barrier layer 504 and bond pad 505.
Particularly, optionally interlayer dielectric layer 501 described in etch-back in this step, to remove the described interlayer dielectric layer 501 of part, reduces the height of interlayer dielectric layer 501, makes its end face lower than the end face of barrier layer 504 and bond pad 505.
Select dry etching or wet etching in this step, alternatively, in described dry etching, select SiCoNi processing procedure to etch described interlayer dielectric layer 501, described SiCoNi processing procedure has larger etching selection ratio to described interlayer dielectric layer 501 and described bond pad 505 and copper diffusion barrier layer 504, design parameter in described SiCoNi processing procedure, those skilled in the art can need to select according to technique, are not limited to a certain numerical value.
Alternatively, when selecting wet etching, selecting hydrofluoric acid HF or dilute hydrofluoric acid DHF to etch, wherein consisting of HF:H 2o=1:2-1:10, to remove the described interlayer dielectric layer 501 of part, described etching temperature is 20-25 DEG C.
It should be noted that, the method that above-mentioned wet method or dry method remove the described interlayer dielectric layer of part 501 is exemplary, is not limited to described method, as long as this area additive method can realize described object, all can be applied to the present invention, repeat them here
The processing procedure of barrier layer and bond pad is completed after above-mentioned steps.
In the present embodiment, only can perform step one to any one wafer in the first wafer and the second wafer, to form the barrier layer of extension on the interlayer dielectric layer 501 of bond pad both sides, also all step one can be performed to the first wafer and the second wafer, to form the barrier layer extended on the surface of interlayer dielectric layer 501, and then with the bond pad of barrier layer Substitute For Partial.
Before bonding first wafer and the second wafer, clean is carried out to the first wafer and the second wafer, makes the particle of wafer surface attachment, impurity, chemical pollutant etc., can remove as far as possible, to obtain preferably pure bonded interface, meet the rigors of bonding conditions effects on surface.Described cleaning step adopts deionized water (DIwater) to carry out infiltration cleaning to device wafers, is then spin-dried for.As an example, described spinning step, rotating speed is 1000 ~ 3500rpm, and the time is 1 ~ 5min.
As depicted in fig. 5g, carry out bonding technology, with by the first wafer 50a and the second wafer 50b bonding.
Exemplarily, when the material of bond pad 505 is copper metal, carry out the Cu-Cu bonding between bond pad, alternatively, described bonding pressure is 20kN ~ 50kN, and be preferably 30kN ~ 40kN, bonding temperature is 300 ~ 450 DEG C, and bonding time is 20 ~ 60 minutes.Because the barrier layer 504 extended on interlayer dielectric layer 501 surface instead of part bond pad, after wafer bonding, when position offset variation in two panels wafer level face, the length of copper cold draw can be reduced, the generation of copper diffusion phenomena can be stoped simultaneously.
Finally perform annealing steps, the temperature of described annealing steps is 300-400 DEG C, and the time is 40-80 minute.Rapid thermal annealing can be selected in the present invention, particularly, the one in following several mode can be selected: furnace anneal, pulse laser short annealing, pulsed electron beam short annealing, ion beam short annealing, continuous wave laser short annealing and non-coherent broad band light source (as halogen lamp, arc lamp, graphite heating) short annealing etc.The wafer completing bonding is annealed, is improved to make the bonding quality between bond pad.
The present invention is in order to solve problems of the prior art, provide a kind of manufacture method of semiconductor device, described method uses the barrier layer extended on interlayer dielectric layer surface to instead of part bond pad, after wafer bonding, when position offset variation in two panels wafer level face, the length of copper cold draw can be reduced, the generation of copper diffusion phenomena can be stoped simultaneously, and then improve bonding quality and the reliability of device.
Embodiment two
As described in Figure 6, the invention provides a kind of semiconductor device, comprising:
First wafer 60a and the second wafer 60b be positioned at above described first wafer 60a, described first wafer 60a and the second wafer 60b includes substrate 600, is positioned at the interlayer dielectric layer 601 in described substrate 600 and the bond pad 603 being positioned at described interlayer dielectric layer 601.
Particularly, described substrate 600 at least comprises substrate, and described substrate can at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
Alternatively, described substrate 600 can also be formed with components and parts and interconnection structure.Different according to the device of predetermined formation, different components and parts can be formed, such as, form 3DCIS device if predetermined, then substrate 600 can form CIS chip or data processing chip.
Wherein said interlayer dielectric layer 601 can select conventional dielectric material, in of the present invention one particularly execution mode, be chosen as SiO 2.
Exemplarily, the material of described bond pad 603 is metallic copper.
Be formed with barrier layer 602 between bond pad 603 and described interlayer dielectric layer 601, the described barrier layer 602 of wherein said first wafer 60a and/or described second wafer 60b extends on the surface of the described interlayer dielectric layer 601 of part.
Alternatively, the material on described barrier layer 602 is selected from one or more in TaN, Ta, TiN, Ti.
Further, the surface extending to the described barrier layer 602 on the surface of the described interlayer dielectric layer of part 601 flushes with the surface of described bond pad 603, and higher than the end face that described interlayer dielectric layer 601 exposes.
The bond pad 603 phase bonding of described first wafer 60a and described second wafer 60b.Exemplarily, described bonding is the Cu-Cu bonding between described bond pad.
Although illustrate only the situation that the first wafer and the second wafer all have the barrier layer of extension in Fig. 6, but it is worth mentioning that, the present invention the arbitrary wafer only in the first wafer or the second wafer can also be formed with the barrier layer of extension, also can realize beneficial effect of the present invention.
Alternatively, described semiconductor device is 3DCIS device.
Semiconductor device of the present invention, owing to having the barrier layer of extension, can reduce the length of copper cold draw, can stop the generation of copper diffusion phenomena, and then this device has high bonding quality and reliability simultaneously.
Embodiment three
Present invention also offers a kind of electronic installation, comprise the semiconductor device described in embodiment two.Or the semiconductor device that the manufacture method according to embodiment one obtains.
The electronic installation of the present embodiment, can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, also can be any intermediate products comprising described semiconductor device.The electronic installation of the embodiment of the present invention, owing to employing above-mentioned semiconductor device, thus has better performance.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims (13)

1. a manufacture method for semiconductor device, comprising:
First wafer and the second wafer are provided, described first wafer and the second wafer include substrate, be positioned at described suprabasil interlayer dielectric layer and the bond pad being positioned at described interlayer dielectric layer, be formed with barrier layer between described bond pad and interlayer dielectric layer, the described barrier layer of wherein said first wafer and/or described second wafer extends on the surface of the described interlayer dielectric layer of part;
Carry out bonding technology, described first wafer and described second wafer to be engaged.
2. manufacture method according to claim 1, is characterized in that, the method forming described bond pad and barrier layer comprises the following steps:
Step one, form interlayer dielectric layer on the substrate, interlayer dielectric layer described in patterning, to form barrier layer groove in described interlayer dielectric layer, the width of described barrier layer groove is greater than the width of the predetermined bond pad groove formed;
Step 2, etch the described interlayer dielectric layer of described barrier layer bottom portion of groove, to form described bond pad groove;
Step 3, on the sidewall of described barrier layer groove and bond pad groove and formation barrier layer, bottom;
Step 4, employing bond pad material layer fill described bond pad groove;
Step 5, carry out flatening process, stop on the barrier layer surface of described barrier layer bottom portion of groove, to form bond pad.
3. manufacture method according to claim 2, is characterized in that, after described step 5, also comprise interlayer dielectric layer described in etch-back part, makes the end face of described interlayer dielectric layer lower than the step of the end face on described barrier layer.
4. manufacture method according to claim 2, is characterized in that, after described step 3 and before step 4, is also included in the step of deposited seed layer on described barrier layer.
5. manufacture method according to claim 2, is characterized in that, the material on described barrier layer be selected from TaN, Ta, TiN, Ti one or more.
6. manufacture method according to claim 2, is characterized in that, the method selecting electrochemistry to plate forms described bond pad material layer.
7. manufacture method according to claim 1, is characterized in that, the material of described bond pad is metallic copper.
8. manufacture method according to claim 1, is characterized in that, described bonding technology is the Cu-Cu bonding technology between described bond pad.
9. manufacture method according to claim 1, is characterized in that, after described bonding technology, also comprises the step performing annealing.
10. a semiconductor device, is characterized in that, comprising:
First wafer and the second wafer be positioned at above described first wafer, described first wafer and the second wafer include substrate, be positioned at described suprabasil interlayer dielectric layer and the bond pad being positioned at described interlayer dielectric layer, be formed with barrier layer between described bond pad and described interlayer dielectric layer, the described barrier layer of wherein said first wafer and/or described second wafer extends on the surface of the described interlayer dielectric layer of part;
The bond pad phase bonding of described first wafer and described second wafer.
11. semiconductor device according to claim 10, is characterized in that, the material of described bond pad is metallic copper.
12. semiconductor device according to claim 10, is characterized in that, the material on described barrier layer be selected from TaN, Ta, TiN, Ti one or more.
13. 1 kinds of electronic installations, is characterized in that, comprise the semiconductor device as described in any one of claim 10-12.
CN201410438573.2A 2014-08-29 2014-08-29 Semiconductor device and manufacturing method thereof, and electronic device Pending CN105374774A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410438573.2A CN105374774A (en) 2014-08-29 2014-08-29 Semiconductor device and manufacturing method thereof, and electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410438573.2A CN105374774A (en) 2014-08-29 2014-08-29 Semiconductor device and manufacturing method thereof, and electronic device

Publications (1)

Publication Number Publication Date
CN105374774A true CN105374774A (en) 2016-03-02

Family

ID=55376829

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410438573.2A Pending CN105374774A (en) 2014-08-29 2014-08-29 Semiconductor device and manufacturing method thereof, and electronic device

Country Status (1)

Country Link
CN (1) CN105374774A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107316855A (en) * 2016-04-27 2017-11-03 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method and electronic installation
CN108520858A (en) * 2018-06-07 2018-09-11 长江存储科技有限责任公司 Metal connecting structure and forming method thereof
CN109148417A (en) * 2018-09-03 2019-01-04 长江存储科技有限责任公司 A kind of hybrid bonded structure and method of wafer
CN109755142A (en) * 2019-01-02 2019-05-14 长江存储科技有限责任公司 Bonding structure and forming method thereof
WO2020258493A1 (en) * 2019-06-26 2020-12-30 上海微电子装备（集团）股份有限公司 Chip encapsulation method
CN113035729A (en) * 2021-03-10 2021-06-25 联合微电子中心有限责任公司 Hybrid bonding method and substrate for bonding
WO2021138792A1 (en) * 2020-01-07 2021-07-15 Yangtze Memory Technologies Co., Ltd. Metal-dielectric bonding method and structure
CN115117101A (en) * 2021-03-23 2022-09-27 芯恩（青岛）集成电路有限公司 CMOS image sensor and manufacturing method thereof
WO2023207551A1 (en) * 2022-04-29 2023-11-02 华为技术有限公司 Integrated circuit, preparation method therefor, three-dimensional integrated circuit and electronic apparatus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080138961A1 (en) * 2006-12-11 2008-06-12 Min Hyung Lee Wafer Bonding Method of System in Package
US20130140697A1 (en) * 2011-12-02 2013-06-06 Samsung Electronics Co., Ltd. Electrode Connecting Structures Containing Copper
CN103794584A (en) * 2012-10-31 2014-05-14 台湾积体电路制造股份有限公司 Hybrid bonding mechanisms for semiconductor wafers

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080138961A1 (en) * 2006-12-11 2008-06-12 Min Hyung Lee Wafer Bonding Method of System in Package
US20130140697A1 (en) * 2011-12-02 2013-06-06 Samsung Electronics Co., Ltd. Electrode Connecting Structures Containing Copper
CN103794584A (en) * 2012-10-31 2014-05-14 台湾积体电路制造股份有限公司 Hybrid bonding mechanisms for semiconductor wafers

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107316855A (en) * 2016-04-27 2017-11-03 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method and electronic installation
CN108520858A (en) * 2018-06-07 2018-09-11 长江存储科技有限责任公司 Metal connecting structure and forming method thereof
CN109148417A (en) * 2018-09-03 2019-01-04 长江存储科技有限责任公司 A kind of hybrid bonded structure and method of wafer
CN109755142A (en) * 2019-01-02 2019-05-14 长江存储科技有限责任公司 Bonding structure and forming method thereof
WO2020258493A1 (en) * 2019-06-26 2020-12-30 上海微电子装备（集团）股份有限公司 Chip encapsulation method
WO2021138792A1 (en) * 2020-01-07 2021-07-15 Yangtze Memory Technologies Co., Ltd. Metal-dielectric bonding method and structure
US11495569B2 (en) 2020-01-07 2022-11-08 Yangtze Memory Technologies Co., Ltd. Metal-dielectric bonding method and structure
US11798913B2 (en) 2020-01-07 2023-10-24 Yangtze Memory Technologies Co., Ltd. Metal-dielectric bonding method and structure
US11978719B2 (en) 2020-01-07 2024-05-07 Yangtze Memory Technologies Co., Ltd. Metal-dielectric bonding method and structure
CN113035729A (en) * 2021-03-10 2021-06-25 联合微电子中心有限责任公司 Hybrid bonding method and substrate for bonding
CN115117101A (en) * 2021-03-23 2022-09-27 芯恩（青岛）集成电路有限公司 CMOS image sensor and manufacturing method thereof
WO2023207551A1 (en) * 2022-04-29 2023-11-02 华为技术有限公司 Integrated circuit, preparation method therefor, three-dimensional integrated circuit and electronic apparatus

Similar Documents

Publication Publication Date Title
CN105374774A (en) Semiconductor device and manufacturing method thereof, and electronic device
TWI345288B (en) Semiconductor devices and fabrication method thereof
TW201616607A (en) Semiconductor device and method for manufacturing the same
US8906781B2 (en) Method for electrically connecting wafers using butting contact structure and semiconductor device fabricated through the same
CN102332425A (en) A method of improving electromigration resistance in copper interconnect technology
CN102683274A (en) Air-gap process applied to copper interconnection
CN105575930A (en) Semiconductor device, preparation method and packaging method thereof
US9224691B2 (en) Semiconductor device contact structures
CN105097777A (en) Semiconductor device and preparation method thereof
US9343435B2 (en) Semiconductor device and related manufacturing method
CN104752324A (en) Preparation method of semiconductor device
CN102237295B (en) Method for manufacturing semiconductor structure
CN114664974B (en) Infrared focal plane device chip and preparation method, readout circuit and preparation method thereof
CN104752322A (en) Semiconductor device and manufacturing method thereof
CN104900543A (en) Semiconductor device and preparation method thereof
CN104952827A (en) Pad structure and manufacturing method thereof
CN105448750A (en) Semiconductor device and manufacturing method thereof, and electronic device
CN107481929A (en) A kind of semiconductor device and its manufacturing method, electronic device
CN103165436B (en) Make the method for semiconductor device
US20130224949A1 (en) Fabrication method for improving surface planarity after tungsten chemical mechanical polishing
CN104051419B (en) For the interconnection structure of stack device
CN108122933B (en) A kind of semiconductor device and preparation method, electronic device
CN102290370A (en) Manufacturing method of conductive plug
CN108091640B (en) Integrated capacitor and method of forming the same
CN105460883A (en) Semiconductor device, manufacturing method thereof and electronic device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160302