CN105374773A - MCSP power semiconductor device and manufacturing method - Google Patents
MCSP power semiconductor device and manufacturing method Download PDFInfo
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- CN105374773A CN105374773A CN201410421700.8A CN201410421700A CN105374773A CN 105374773 A CN105374773 A CN 105374773A CN 201410421700 A CN201410421700 A CN 201410421700A CN 105374773 A CN105374773 A CN 105374773A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention mainly relates to the field of power semiconductor devices, and particularly provides a power semiconductor device in an MCSP packaging form and a corresponding manufacturing method on the premise of realizing a chip scale packaging form. A conductive bonding layer is arranged on the back surface of a wafer; a metal foil layer is laminated on the back surface of the wafer and the conductive bonding layer is used for lamination and bonding; a composite adhesive tape is bonded on the metal foil layer; and a laminated layer between adjacent chips is cut, and the laminated layer comprises a plastic packaging layer, the wafer, the conductive bonding layer, the metal foil layer and the composite adhesive tape.
Description
Technical field
The present invention relates to power semiconductor field, particularly relate to and realizing under wafer-level package mode prerequisite, propose a kind of power semiconductor of MCSP packing forms and corresponding preparation method.
Background technology
Leak two MOSFET power device altogether and be mainly used in notebook computer, battery charging and discharging that is dull and stereotyped or mobile phone manages, and because recent trend is that the charging interval is shorter and shorter, so the corresponding increasing of charging and discharging currents, therefore wishes that the conducting resistance of device is more and more less.And dull and stereotyped, the design of mobile phone ultrathin also needs the size of device more and more less.
Accompanying drawing 1A ~ 1C lists the encapsulation of a kind of novel power MOSFET tube, lead frame 101 is make use of in the vertical view of Figure 1A, the chip 102 that front is provided with several soldered ball is pasted onto on lead frame 101, and carry out plastic packaging after solidification, then grinding device front makes soldered ball expose.The lead frame 101 introduced is except cost is high,, too increase the height/thickness of device, to reducing, device size is unfavorable because the clamping pressure will standing mould is general also thicker for this, otherwise easily deformed damaged under larger clamping pressure, this is unfavorable to reduction device size.In addition, in the encapsulation of Figure 1A, an independent plastic packaging operation is also at least needed to come plastic package lead frame and chip, and the chip 102 on lead frame 101 is pasted by the paster technique of standard, therefore this encapsulation is not the wafer-level package in complete meaning, and corresponding cost burden also significantly can increase because employing more operation.
Lead frame has been abandoned in the profile of Figure 1B ~ 1C, but directly at the backside deposition layer of metal layer 121 of chip 122, it is emphasized that, the similar metal exposed like this at metal level 121 makes the more difficult also easy wears of label, and too thin metal level 121 (generally only having several micron) is unfavorable for the dead resistance reducing conducting resistance or other types.Fig. 1 C also defines a plastic packaging layer 123 on metal level 121, although plastic packaging layer 123 can be printed or etch label, but many times, in order to realize wafer-level package, also usually need to grind thinning plastic packaging layer 123, but thing followed problem is, the plane that plastic packaging layer 123 is ground is observed from microcosmic, be not very perfect burnishing surface but with the matsurface of pit, so the inconvenience making label also can be brought out.
Therefore, the wafer-level package in complete meaning should be obtained, device is made to have lower conducting resistance, device can compatible all packaging process (such as at least meet can print apparent label swimmingly) very smoothly again, and this just requires a kind of new method for packing to take into account these thorny difficult problems.
Summary of the invention
A kind ofly prepare in the method for power semiconductor of the present invention, comprise the following steps: provide front with the wafer of a plastic packaging layer; In a kind of selection mode, a conductive adhesive is set at wafer rear, or in another kind of selection mode, plates the conductive adhesive such as such as Sn in a face of the metal foil layer being bonded to wafer rear in advance; This metal foil layer of lamination is to wafer rear and utilize described conductive adhesive to carry out pressing gluing; Paste on a compound adhesive tape to described metal foil layer; Lamination between cutting adjacent chips, described lamination comprises plastic packaging layer, wafer, conductive adhesive, metal foil layer and compound adhesive tape, forms many independently power semiconductors.
Said method, before cutting described lamination, first prints and forms identifier on described compound adhesive tape.
Said method, in the step of laminated metallic layers of foil, synchronously also applies metal foil layer with pressure wafer heats simultaneously, so that closely pressing metal foil layer is to wafer rear; Or after the stickup of compound adhesive tape completes, then wafer heats is also applied compound adhesive tape and metal foil layer with pressure simultaneously, so that closely pressing metal foil layer is to wafer rear.
Said method, before laminated metallic layers of foil to wafer rear, first plates metal coating in the one side of metal foil layer, is then laminated to wafer rear with its one side with metal coating.
In one alternate embodiment, said method comprises: before forming plastic packaging layer, first corresponding arrangement metal coupling on the liner of each chip front side; Then in being coated in wafer frontside and by each metal coupling with a plastic packaging layer plastic packaging; Grind thinning plastic packaging layer again until the top of metal coupling is exposed by partly grinding, take this top end face forming each metal coupling planarization, and exposed from the end face of plastic packaging layer, this grinding steps needs to complete before wafer rear arranges this one deck conductive adhesive.
In one alternate embodiment, said method comprises, before wafer rear arranges conductive adhesive, first an illusory wafer and described wafer are carried out bonding, and be bonded in the end face of plastic packaging layer, after the gluing steps completing compound adhesive tape, implement described cutting step before more illusory wafer is peeled off.
In one alternate embodiment, said method comprises: before forming plastic packaging layer, first corresponding arrangement metal coupling on the liner of each chip front side; Then in being coated in wafer frontside and by each metal coupling with plastic packaging layer plastic packaging; After completing the gluing steps of compound adhesive tape and before the described lamination of cutting, grind thinning plastic packaging layer until the top of metal coupling is exposed by partly grinding, take this top end face forming each metal coupling planarization, and the top end face of these metal couplings is exposed from the end face of plastic packaging layer.
In a kind of power semiconductor of the present invention, comprise; A chip; A top plastic packaging layer covering chip front side, the liner of wherein chip front side is provided with metal coupling, and described top plastic packaging layer is centered around metal coupling lateral wall circumference, and the top end face of each metal coupling planarization all exposes from the end face of top plastic packaging layer; A bottom metal layers of foil being laminated to chip back, and utilize conductive adhesive that bottom metal foils lamination is closed gluing at chip back; One is pasted on the bottom compound adhesive belt in described bottom metal layers of foil.
Above-mentioned power semiconductor, described integrated chip has a pair common drain metal oxide semiconductor field effect tube, described bottom metal layers of foil forms the public drain electrode electrode of this pair common drain metal oxide semiconductor field effect tube, and power semiconductor has the multiple metal couplings contacting this pair common drain metal oxide semiconductor field effect tube gate liner separately, source pad respectively.
Above-mentioned power semiconductor, the one side that bottom metal foils lamination is combined in chip back is coated with noble coatings.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention:
Figure 1A ~ 1C is the embodiment of background technology;
Fig. 2 A ~ 2E is the schematic flow sheet implementing plastic packaging and thinned wafer in wafer frontside;
Fig. 3 A ~ 3G is the schematic flow sheet that the present invention realizes wafer-level package;
But Fig. 4 A ~ 4B is step based on Fig. 3 A ~ 3G additionally introduces the schematic diagram of an illusory wafer;
Fig. 5 A ~ 5C is step based on Fig. 3 A ~ 3G but changes the thinning opportunity of the plastic packaging layer of wafer frontside;
Fig. 6 A ~ 6B is the embodiment being applied in the two MOSFET pipe of common drain of the present invention.
Fig. 7 A ~ 7C is the embodiment of application LCTape.
Fig. 8 A ~ 8C is the zinc-plated embodiment as adhesion coating.
Embodiment
In fig. 2, wafer 300 contains casts the chip linked together in a large number mutually, and chip defines border each other with the transverse direction that wafer is preset or the dicing lane of longitudinal direction.Each chip front side is all provided with several liner 201 as electrode terminal, as shown in Figure 2 B, metal coupling is planted in the front of wafer, such as a metal coupling 205 to be settled or is welded on a liner 201 accordingly, metal coupling 205 has multiple choices, as typical solder ball, golden projection Goldbump etc.In fig. 2 c, perform a plastic packaging operation, utilize the capsulation material of such as epoxy resin to form a plastic packaging layer 206 in the front of wafer 300, can require that plastic packaging layer 206 has default thickness, so that by all coated for all metal couplings 205 being sealed in.Then as shown in Figure 2 D, use the increase of the mechanical strength that plastic packaging layer 206 brings, the not easily broken or warped of wafer 300 can be ensured, so can from the opposite back side grinding thinned wafer of wafer 300.Anticipate out although not shown in the figures, in fact can also select to carry out wet etching in the side, the thinning back side of wafer, discharge through grinding stress residual overleaf and repair lattice damage, and carry out thereafter heavily doped ion implantation again in side, wafer 300 back side and deposit layer of metal layer at thinning back spatter, thus, the heavily doped region that metal layer just can inject with wafer rear forms ohmic contact.Subsequently, as shown in Figure 2 E, grind thinning plastic packaging layer 206, until the script of metal coupling 205 is convex or is partly ground away for the top of concave plane, thus all metal couplings 205 are all exposed from thinning plastic packaging layer 206, simultaneously each metal coupling 205 has nationality by the top end face of planarization grinding acquisition, and these top end faces are all exposed from the end face of thinning plastic packaging layer 206.
In figure 3 a, the thinning back side of one deck conductive adhesive 306 to wafer 300 is set, if the thinning back side of wafer 300 is provided with the metal layer 305 multiple choices modes such as (such as) Ti/Ni/Ag or Ti/Ni//Au illustrated, then conductive adhesive 306 is paste to be arranged on metal layer 305 in fact.Wherein, the mechanism forming conductive adhesive 306 at wafer rear has multiple choices form, if it is solder(ing) paste, conductive silver paste etc. and so on conductive materials that conductive adhesive 306 is selected, can realize in the mode directly applied, if conductive adhesive 306 is selected to be the conductive film with gluing function, then it directly can be bonded to wafer 300 back side.In certain embodiments, the preparation of conductive adhesive 306 can directly adopt wafer rear coating technology (Waferbacksidecoating) to realize.In figure 3b, metal foil layer 307 is laminated to the back side of wafer 300, period utilizes conductive adhesive 306 to carry out pressing gluing, metal foil layer 307 is laminated closely and is fitted on wafer 300 back side or metal layer 305, wafer rear effective metal thickness is evenly increased at the back side of whole wafer, makes thickness homogenization.Notice that metal foil layer 307 has the thickness quite accurately controlled, the dead resistance that back metal effective thickness is beneficial to reduction conducting resistance or other types can be improved to reach, requirement simultaneously can be prevented in background technology the doubt that cannot effectively reduce thickness of detector or size that lead frame originally brings, such as metal foil layer 307 can have the thickness of 0.5 ~ 3mil, to keep flexibility and the toughness of metal foil layer.For the ease of understanding and distinguishing, this metal foil layer 307 can store stand-by or transport in the mode being rolled up cylinder, and Fig. 3 B shows and to extract metal foil layer 307 and tiling launches and is laminated to the action at wafer 300 back side from metal foil layer 307 cylinder rolled, can imagine, the hardness that lead frame is stronger and thicker thickness, cause lead frame self cannot be in turn laminated on wafer 300 back side, and can only be that the mode of pickup will separate one single chip from wafer and is placed into one by one on lead frame, this embodies the present invention and prior art forms the obvious characteristic distinguished.Metal foil layer 307 has multiple choices, and typical and cost-effective a kind of material is such as Copper Foil.
In some embodiment, the stronger metal coating of electric conductivity can be plated on the one side of wafer rear of metal foil layer 307, the noble coatings such as such as gold, silver, the effect of noble coatings strengthens the connection with conductive adhesive 306, makes connection more reliable.Plating coating to metal foil layer 307 can profit realize in various manners, plating or the various mode such as chemical plating or other sputtering sedimentations all applicable.Wherein, metal foil layer 307 is coated with the one side of metal coating for contacting conductive adhesive 306, and this one side is in turn laminated to wafer 300 back side.In some embodiment, in the lamination step of metal foil layer 307, need additionally to heat the wafer 300 with plastic packaging layer 206, so that by heat conduction to conductive adhesive 306, if conductive adhesive 306 is electric conducting materials of solder(ing) paste class, it is under melted by heating state condition, the gluing effect of wafer 300 back side and metal foil layer 307 can be promoted, make metal foil layer 307 more firm and be in turn laminated on wafer 300 closely, meanwhile, pressure can also be applied equably on metal foil layer 307 region of whole laminating, make each fit area all force balances of whole metal foil layer 307, so that tight pressing metal foil layer 307 to wafer rear further.If in this heating period, the planarization top end face of metal coupling 205 is out exposed from plastic packaging layer 206, as Fig. 3 B, necessarily require the fusing point of metal coupling 205 a little less than the fusing point of conductive adhesive 306 toward contact, melt excessive losing to avoid metal coupling 205.
In fig. 3 c, then paste on one deck compound adhesive tape 308 to metal foil layer 307, sticking placement here, except simple laminating, also can apply external pressure to compound adhesive tape 308 simultaneously and adopt the mode of lamination to reinforce degree of adhesion.Compound adhesive tape 308 at least should comprise an adhesive layer and a protector rete (preferably black); what adhesive layer was firmly bonded in metal foil layer 307 deviates from a face of wafer; and protector rete is except physical protection wafer or chip; also need for follow-up prints labels, this can introduce in detail in subsequent content.Compound adhesive tape 308 such as can adopt Japanese LCTAPE, or adopts the composite bed of an an adhesive layer adhesive and common polyimides PI layer (PI layer is as protector rete).In addition, as can selection mode but not restrictive condition, after the aforementioned step heated wafer 300 can also move on to the stickup of compound adhesive tape 308, that is, heating is implemented without the need to the stage at laminated metallic layers of foil 307 to wafer rear, but after completing the stickup of compound adhesive tape 308, then the wafer whole implementation with plastic packaging layer and compound adhesive tape is heated, as shown in Figure 3 D.Because the compound adhesive tape 308 of the selected classification of part with adhesive layer can solidify after being heated in fact, its provisional viscosity takes this to change permanent cementability into, and now conductive adhesive 306 also just needs melted by heat, thus bring better effect and lower cost.In this heating period, on the adhesion area of whole compound adhesive tape 308, can also apply pressure equably, this pressure can pass to metal foil layer 307 naturally, promotes and strengthen to fit tightly degree between metal foil layer 307 and wafer 300.
Be easy to learn, the mode of compound adhesive tape 308 is adopted to be different from the operation forming plastic packaging layer at wafer rear, if intend to perform plastic package process (such as attempting to obtain the plastic packaging layer 123 of chip back in background technology Fig. 1 C) at wafer rear, then at least to use plastic packaging equipment, also can relate to grinding and thinningly be coated on the very not accurate plastic packaging layer of wafer rear, thickness, this will suffer from the various problems that background technology displays.Obviously, wafer rear is without the need to adopting any plastic packaging operation and preparing plastic packaging layer, and this is that the present invention and prior art form another obvious characteristic distinguished.
In fig. 3e, the operation (Marking) of the prints labels of implementation criteria, although directly application to printed can realize, but in order to ensure that mark can continue the more permanent time, utilize laser ablation to carry out lettering time more, thus lettering forms identifier 325 on the back side of the exposed side of compound adhesive tape 308, essence is printed on the protector rete of compound adhesive tape 308, this identifier 325 covers the various attribute informations of product usually, as manufacturer, model, the information such as specification, compound adhesive tape 308 region overlapping with each chip can be printed with an identifier 325.The thickness of compound adhesive tape 308 is default, foregoing description is illustrated, and compound adhesive tape 308 is not plastic packaging layer, has abandoned a plastic packaging operation, do not need extra thinning, so the difficult problems being difficult to lettering that background technology is mentioned has not existed during this period completely yet.In Fig. 3 F ~ 3G, along Cutting Road so that the wafer cutting step of operative norm, thus wafer 300 cutting and separating can go out multiple independent chip 300'.Mainly cut the lamination between adjacent chips 300', lamination includes plastic packaging layer 206, wafer 300, conductive adhesive 306, metal foil layer 307 and compound adhesive tape 308, and metal layer 305, thus forms many independently power semiconductors 500.In power semiconductor 500, include the top plastic packaging layer 206' that the nationality that covers chip 300' front is cut by plastic packaging layer 206, and the liner 201 in chip 300' front is provided with metal coupling 205, top plastic packaging layer 206' is centered around around metal coupling 205 sidewall, and the top end face of each metal coupling 205 planarization is all exposed from the end face of top plastic packaging layer 206'.Wafer 300 back side disconnects with metal layer 305 is also cut the back metallization layer being formed and be arranged at each chip 300' back side, semiconductor device 500 also comprises the bottom metal layers of foil 307' being laminated to the nationality on the chip 300' back side or back face metalization layer 305 and being cut by metal foil layer 307, and utilizes conductive adhesive 306 by firm for bottom metal layers of foil 307' pressing gluing at the chip 300' back side.Semiconductor device 500 also comprises a bottom compound adhesive belt 308' being pasted on the nationality on bottom metal layers of foil 307' and being cut by compound adhesive tape 308, is printed on lettering on compound adhesive tape 308 or identifier 325 is transferred on the compound adhesive belt 308' of bottom thereupon before.Power semiconductor 500 is relative to prior art, although chip 300' front is coated with top plastic packaging layer 206', think that it remains plastic sealed wafer-level package MCSP (MoldedChipScalePackage), but side, the chip 300' back side is not enveloped by any plastic-sealed body, that instead play sealing function is bottom compound adhesive belt 308'.
Optional but in the non-embodiment be construed as limiting at one, as in Fig. 4 A ~ 4B, than the flow process of Fig. 3 A ~ 3G, only difference is: in view of the transport of thinner wafer 300 or in each operational phase, wafer 300 still has frangible potential hazard, so also additionally introduce a bearing substrate or illusory wafer (dummywafer) 350, illusory wafer 350 is bonded in thinning after circle 300 on, the thinning end face of an end face of wafer 350 or bottom surface and the plastic packaging layer 206 after being polished is pasted and is combined, and then according to the flow process of Fig. 3 A ~ 3G, form the conductive adhesive 306 at the thinning back side of wafer 300 successively, metal foil layer 307, compound adhesive tape 308.In Fig. 4 A ~ 4B, after compound adhesive tape 308 to be formed just peelable fall illusory wafer 350, it should be noted that, the opportunity of peeling off can be after Fig. 3 C obtains the step of compound adhesive tape 308, also can be after Fig. 3 D implements heating steps, or even after the lettering step of Fig. 3 E, but usually before the cutting step of Fig. 3 F.Illusory wafer 350 is supplied to the mechanical strength of wafer 300, except in transport and traditional manipulative steps, the better advantage displayed is, due to metal foil layer 307 and/or compound adhesive tape 308 be set among the step that need suffer lamination, period must apply external force, this external force is directly transmitted and is applied to thinner wafer 300 and can brings certain frangible risk, and illusory wafer 350 can to a certain degree be evaded and eliminate these risks.
In another optional but non-embodiment be construed as limiting, as in Fig. 5 A ~ 5C, than the flow process of Fig. 3 A ~ 3G, difference is: skipped the step that Fig. 2 E grinds plastic packaging layer 206, after the step of Fig. 2 D, directly implement the flow process of Fig. 3 A ~ 3G, that is, the original thickness of plastic packaging layer 206 is retained, at least before the compound adhesive tape 308 forming wafer rear, plastic packaging layer 206 is polished not thinning.As Fig. 5 A ~ 5B, retain the original thickness of plastic packaging layer 206, and then according to the flow process of Fig. 3 A ~ 3G, form conductive adhesive 306, metal foil layer 307, compound adhesive tape 308 successively at the thinning back side of wafer 300.In figure 5 c, just thinning plastic packaging layer 206 can be ground after compound adhesive tape 308 to be formed, it should be noted that, the opportunity of grinding plastic packaging layer 206 can be after Fig. 3 C obtains the step of compound adhesive tape 308, also can be after Fig. 3 D implements heating steps, or even after the lettering step of Fig. 3 E, but usually before the cutting step of Fig. 3 F.Have in the embodiment of advantage at some, if retain the thickness of plastic packaging layer 206 and not thinning in the step of Fig. 3 B or 3C, then metal coupling 205 can be covered by plastic packaging layer 206 and not expose, fusing point height now between metal coupling 205 and conductive adhesive 306 requires just no longer so harsh, can not lose because metal coupling 205 is wrapped by because fusing is excessive.In the embodiment of Fig. 5 A ~ 5C, plastic packaging layer 206 be polished thinning before, plastic packaging layer 206 is supplied to the mechanical strength of wafer 300, equally, lamination external force is directly transmitted and is applied to thinner wafer 300 and can brings certain frangible risk, and plastic packaging layer 206 then can to a certain degree be evaded and eliminate these risks.
Fig. 6 B is the schematic perspective view of device to identifier 325 MCSP power semiconductor 500 down of flipchart 3G, based on each layer of detail display chip back structure and for explaining explanation, the thickness of each layer in the back side is incomplete to be drawn with the thickness proportion relation of chip according in actual products.In an optional embodiment, such as packing forms of the present invention can be applied in the chip of the two MOSFET (CommondraindualMOSFET) of common drain of widely used battery charge-discharge circuit.The chip 300' of Fig. 6 B is integrated with the power MOSFET pipe M1 shown in Fig. 6 A, M2, wherein the drain D 1 of M1 links together with the drain D 2 of M2, the grid G 1 of M1 and the control of the closure or openness of the grid G 2 of M2 by electric power management circuit, based on reducing the M1 be connected in series, the resistance of M2 or Rss (source S 1 is to the resistance of source S 2), consider that the original metal layer 305 of chip back is thinner and cannot effectively achieve this end, the bottom metal layers of foil 307' that additional layer shown in Fig. 6 B of the present invention is depressed into the chip 300' back side forms M1 integrated in chip 300', the public drain electrode electrode of M2.In device 500, the metal coupling 205S1 with planarization top end face contacts and is welded in the liner 201 that of this common drain MOSFETM1 is presented as M1 source pad, and the metal coupling 205G1 with planarization top end face contacts and be welded in the liner 201 that of this common drain MOSFETM1 is presented as M1 gate liner.The metal coupling 205S2 with planarization top end face contacts and is welded in the liner 201 that of this common drain MOSFETM2 is presented as M2 source pad, and the metal coupling 205G2 with planarization top end face contacts and be welded in the liner 201 that of this common drain MOSFETM2 is presented as M2 gate liner.Top plastic packaging layer 206' is covered in chip 300' front, top plastic packaging layer 206' is centered around metal coupling 205S1,205S2,205G1,205G2 separately around sidewall, and the top end face of each metal coupling planarization all exposes from the end face of top plastic packaging layer 206' China and foreign countries.Utilize conductive adhesive 306 by bottom metal layers of foil 307' pressing gluing at the chip 300' back side, bottom compound adhesive belt 308' is then bonded in or is laminated on bottom metal layers of foil 307', in addition, can also select to plate noble coatings on the one side that bottom metal layers of foil 307' is pressed together on the chip 300' back side.
In the alternative of Fig. 7 A ~ 7C, especially illustrate the lamination step that compound adhesive tape 308 adopts particular B acksideCoatingTAPE (such as LCTAPE) in Fig. 7 B ~ 7C.Fig. 7 A is that nationality is obtained by the step of Fig. 2 A ~ 2E, and via plastic packaging, wafer is thinning and sputter the operations such as back metallization layer, and this has had detailed introduction in the preceding article, so the present embodiment repeats no longer one by one.Leading brushing conductive adhesive 306 is on metal layer 305, and utilize conductive adhesive 306 to press on the metal layer 305 at wafer 300 back side by this metal foil layer 307, emphasis part is: in figure 7b, the exemplary step giving lamination LCTAPE on the metal foil layer 307 at wafer 300 back side, Fig. 7 C then corresponds to Fig. 7 B, has intercepted a part of fragment of the concrete structure of wafer 300 and each layer of plastic packaging layer 206 and back exemplarily.Other subsequent steps after Fig. 7 C are substantially identical with Fig. 3 C ~ 3G.In this embodiment, eliminate necessary or optional step of some illustrating complete above, and other such as to need on LCTAPE laser printing label, implement cutting, carry out the normal process of the encapsulation industries such as testing package and here also repeat no longer one by one.
LCTAPE can comprise thermosetting component, binder polymer composition, energy-curable composition etc.For the doubt avoiding LCTAPE may be considered to " not general term ", spy quotes some compositions that Japanese LintecCorporation company discloses: thermosetting component comprises epoxy resin, phenol resin, melamine resin, urea resin, mylar, polyurethane resin, acrylic resin, polyimide ester resin, benzoxazine colophony and their mixture.In addition, there is provided suitable viscosity to compound adhesive tape and improve machinability, need to use binder polymer composition, useful binder polymer such as has acrylic polymer, mylar, polyurethane resin, organic siliconresin and rubber polymer, more preferably acrylic polymer.The component of energy ray-curable comprises a kind of by the compound of emittance ray as ultraviolet and electron beam polymerization/solidification.In addition, compound adhesive tape can be painted, and form layer to compound adhesive tape carry out painted by adding pigment or dyestuff wherein, such as the black of the compound adhesive tape after painted can improve the outward appearance of final chip.
In the embodiment of 8A ~ 8C, the material of conductive adhesive 306 and the laminar manner of correspondence embodiment relatively above can be changed slightly.As shown in Figure 8 B, before on the metal layer 305 attempting metal foil layer 307 lamination to be combined in Fig. 8 A, also need in advance at one of metal foil layer 307 zinc-plated Sn on the composition surface of carrying out lamination bonding with wafer rear, this tin coating just serves as the different conductive adhesive 306 with conductive silver paste.If be also additionally coated with some noble metal coatings such as Ag or Au before this composition surface, then tin coating should be plated on noble metal coating.Thereafter, in order to the effect allowing this tin coating play preferably gluing in lamination step, as option, the lamination dynamics of about 100 ~ 2500 gram forces (gf) can be applied to metal foil layer 307, and select to implement this step under about 200 ~ 400 centigrade ambient temperature conditions, thus the metal foil layer 307 with tin coating is laminated on the metal layer 305 of wafer rear.In addition, the execution mode of Fig. 8 C is not zinc-plated on a face of metal foil layer 307, but directly tin is plated in wafer rear, as being plated on the metal layer 305 of Fig. 8 A, and then laminated metallic layers of foil 307 to wafer rear, and utilize tin layers to carry out pressing gluing as conductive adhesive 306, thus metal foil layer 307 is laminated to wafer rear with tin coating metal layer 305 on.
Above, by illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment, foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (10)
1. prepare a method for power semiconductor, it is characterized in that, comprise the following steps:
There is provided front with the wafer of a plastic packaging layer;
In the one side of wafer rear or a metal foil layer, one conductive adhesive is set;
Metal foil layer described in lamination is to wafer rear and utilize described conductive adhesive to carry out pressing gluing;
Paste on a compound adhesive tape to described metal foil layer;
Lamination between cutting adjacent chips, described lamination comprises plastic packaging layer, wafer, conductive adhesive, metal foil layer and compound adhesive tape, forms many independently power semiconductors.
2. the method for claim 1, is characterized in that, before cutting described lamination, first prints on described compound adhesive tape and forms identifier.
3. the method for claim 1, is characterized in that, in the step of laminated metallic layers of foil, synchronously also applies metal foil layer with pressure wafer heats simultaneously; Or
After the gluing steps completing compound adhesive tape, wafer heats is also applied compound adhesive tape and metal foil layer with pressure simultaneously, so that closely pressing metal foil layer is to wafer rear.
4. the method for claim 1, is characterized in that, before laminated metallic layers of foil, first plates noble coatings in the one side of metal foil layer, is then laminated to wafer rear with its one side with noble coatings.
5. the method for claim 1, is characterized in that, comprising:
Before forming plastic packaging layer, first corresponding arrangement metal coupling on the liner of each chip front side;
Then in being coated in wafer frontside and by each metal coupling with a plastic packaging layer plastic packaging;
Grinding thinning plastic packaging layer again until the top of metal coupling is exposed by partly grinding, taking this top end face forming each metal coupling planarization, and being exposed from the end face of plastic packaging layer.
6. the method for claim 1, it is characterized in that, before wafer rear arranges conductive adhesive, first an illusory wafer and described wafer are carried out bonding, and be bonded in the end face of plastic packaging layer, more illusory wafer is peeled off after the gluing steps completing compound adhesive tape.
7. the method for claim 1, is characterized in that, comprising:
Before forming plastic packaging layer, first corresponding arrangement metal coupling on the liner of each chip front side;
Then in being coated in wafer frontside and by each metal coupling with plastic packaging layer plastic packaging;
After completing the gluing steps of compound adhesive tape but cutting described lamination before, grinding thinning plastic packaging layer until the top of metal coupling is exposed by partly grinding, taking this top end face forming each metal coupling planarization, and being exposed from the end face of plastic packaging layer.
8. a power semiconductor, is characterized in that, comprises;
One chip;
The one top plastic packaging layer covering chip front side, the liner of wherein chip front side is provided with metal coupling, and described top plastic packaging layer is centered around metal coupling lateral wall circumference, the top end face of each metal coupling planarization all exposes from the end face of top plastic packaging layer;
The one bottom metal layers of foil being laminated to chip back, and utilize conductive adhesive that bottom metal foils lamination is closed gluing at chip back;
One is pasted on the bottom compound adhesive belt in described bottom metal layers of foil.
9. power semiconductor as claimed in claim 8, it is characterized in that, described integrated chip has a pair common drain metal oxide semiconductor field effect tube, described bottom metal layers of foil forms the public drain electrode electrode of this pair common drain metal oxide semiconductor field effect tube, and power semiconductor has the multiple metal couplings contacting this pair common drain metal oxide semiconductor field effect tube gate liner separately, source pad respectively.
10. power semiconductor as claimed in claim 8, it is characterized in that, the one side that bottom metal foils lamination is combined in chip back is coated with noble coatings.
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| CN201410421700.8A CN105374773A (en) | 2014-08-25 | 2014-08-25 | MCSP power semiconductor device and manufacturing method |
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| CN111653528A (en) * | 2020-07-22 | 2020-09-11 | 江苏长晶科技有限公司 | Chip packaging structure, method and semiconductor device |
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Application publication date: 20160302 |