CN105374753B - A kind of manufacturing method of memory - Google Patents
A kind of manufacturing method of memory Download PDFInfo
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- CN105374753B CN105374753B CN201410321309.0A CN201410321309A CN105374753B CN 105374753 B CN105374753 B CN 105374753B CN 201410321309 A CN201410321309 A CN 201410321309A CN 105374753 B CN105374753 B CN 105374753B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 230000002093 peripheral effect Effects 0.000 claims abstract description 89
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 73
- 229920005591 polysilicon Polymers 0.000 claims abstract description 72
- 230000001413 cellular effect Effects 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 47
- 229910052751 metal Inorganic materials 0.000 claims abstract description 47
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 25
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000001039 wet etching Methods 0.000 claims abstract description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- 238000002347 injection Methods 0.000 claims description 20
- 239000007924 injection Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 claims description 5
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 210000004483 pasc Anatomy 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000000137 annealing Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 65
- 238000005530 etching Methods 0.000 description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 22
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- 230000000717 retained effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 210000004027 cell Anatomy 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
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- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a kind of manufacturing methods of memory.This method can reduce wet etching amount and be affected to avoid peripheral components structure, while simplify manufacturing process, reduce cost.This method comprises: cellular zone multilayered structure and peripheral components area multilayered structure is formed on the substrate；Peripheral components area multilayered structure is handled to form polysilicon gate and polysilicon gate side wall；The multilayered structure of the cellular zone is etched to form control gate；Side wall layer is deposited on the cellular zone and the peripheral components area；Remove the side wall layer on the polysilicon gate and source/drain region in the peripheral components area；In peripheral components area polysilicon gate and source/drain region on form metal silicide.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to the manufacturing methods of memory.
Background technique
In nonvolatile memory (NVM), floating grid (FG) is for storing electronics to realize " 1 " or " 0 ".Floating grid is logical
Often it is formed by polysilicon.As the size of flash memory constantly reduces, floating gate length and active area (AA) width also constantly reduce.Cause
The size and shape of this floating grid and active area have a significant impact for the characteristic tool of flash memory.
Nonvolatile memory (NVM) generally includes cellular zone and peripheral components area.For with autoregistration floating grid
Nonvolatile memory (NVM), when reducing unit size, since unit size is very small, depth-width ratio (aspect
Ratio) relatively high, the deposit introduced by subsequent technique, such as oxide etc. are often remained in cellular zone.Therefore it needs a large amount of
Etch amount with the deposit in clearing cell region.
Problem of the prior art is: (1) since film is unstable and standoff effects, completely removing the deposition in unit area
Object is highly difficult, and if not completely removing these deposits, the contact stop-layer silicon nitride of contact hole will in subsequent technique
It can be deposited on these remaining deposits, this will lead to the problem of contact hole is open.(2) if to ensure in unit area
Deposit is completely removed, then needs to increase etch amount, but a large amount of wet etching amount will will affect the side wall knot of peripheral components
Structure, and also will affect relevant device parameters.
To solve this problem it is necessary to provide a kind of improved semiconductor technology.
Summary of the invention
The object of the present invention is to provide a kind of improved semiconductor making method, this method can reduce wet etching amount to keep away
Exempt from peripheral components structure to be affected, while simplifying manufacturing process, reduces cost.
According to an aspect of the present invention, a kind of manufacturing method of memory is provided, comprising: cellular zone is formed on the substrate
Multilayered structure and peripheral components area multilayered structure；Peripheral components area multilayered structure is handled with formed polysilicon gate and
Polysilicon gate side wall；The multilayered structure of the cellular zone is etched to form control gate；In the cellular zone and the peripheral components
Side wall layer is deposited in area；Remove the side wall layer on the polysilicon gate and source/drain region in the peripheral components area；In peripheral components area
In polysilicon gate and source/drain region on form metal silicide.
According to an aspect of the present invention, in preceding method, the processing to peripheral components area multilayered structure further includes following
At least one of step: after forming polysilicon gate, peripheral region is carried out injection is lightly doped；Forming polysilicon gate side wall
Afterwards, the source/drain region injection of peripheral region is carried out to form the source/drain region of peripheral region.
According to an aspect of the present invention, in preceding method, after forming control gate in cellular zone, cellular zone is carried out light
Doping injection.
According to an aspect of the present invention, in preceding method, after forming the side wall layer, the cellular zone is carried out
Source/drain region injection.
According to an aspect of the present invention, in preceding method, the cellular zone multilayered structure includes with one layer in lower layer
Or multilayer: tunnel oxide, doped polysilicon layer, silicon oxide/silicon nitride/silicon oxide layer, doped polysilicon layer and silicon nitride
Layer.
According to an aspect of the present invention, in preceding method, peripheral components area multilayered structure includes in lower layer
One or more layers: tunnel oxide, doped polysilicon layer, doped polysilicon layer, silicon nitride layer.
According to an aspect of the present invention, in preceding method, the polysilicon gate and source/drain in the peripheral components area are removed
Side wall layer in area at least one of includes the following steps: forming protection structure on cellular zone, carries out to peripheral components area
The thickness of side wall layer on top surface is etched specific thicknesses by anisotropic dry etching；Protection structure in removal unit area, into
Row wet etching removes remaining side wall layer on top surface.
According to an aspect of the present invention, in preceding method, the specific thicknesses are 10 to 70 angstroms.
According to an aspect of the present invention, in preceding method, in peripheral components area polysilicon gate and source/drain region on shape
At least one of include the following steps at metal silicide: one layer of metal is deposited on a surface of a wafer；Remove the metal.
According to an aspect of the present invention, in preceding method, the metal is nickel.
Compared with prior art, the invention has the advantages that
According to the solution of the present invention, the gate polysilicon etching for carrying out peripheral components area first, then carries out control gate etching,
Cellular zone side wall directly serves as metal silicide barrier oxide, to simplify technique.Moreover, because in peripheral components area
After side wall etching, the peripheral components side wall oxide on cellular zone is completely removed, therefore does not need a large amount of wet etching.By
In reducing wet etching amount, the side wall side wall and silicon substrate of peripheral components are unaffected, and relevant device performance is not yet
It will receive influence.
In addition, carrying out control gate etching first, gate polysilicon etching is then carried out, is filled in peripheral components oxide side wall
There is voiding problem, this will lead to contact openings problem during cellular zone.And etching process shown in the present invention, then this is not present
One problem.
Detailed description of the invention
For the above and other advantages and features for each embodiment that the present invention is furture elucidated, will be presented with reference to attached drawing
The more specific description of various embodiments of the present invention.It is appreciated that these attached drawings only describe exemplary embodiments of the invention, therefore
It is not to be regarded as being restriction on its scope.In the accompanying drawings, in order to cheer and bright, it is exaggerated the thickness of layer and region.It is identical or
Corresponding component will be indicated with same or similar label.
Figure 1A to Fig. 1 N shows the diagrammatic cross-section for being used to form control gate and gate polysilicon etching process.
Fig. 2A to Fig. 2 M shows the section of control gate and gate polysilicon etching process according to an embodiment of the invention
Schematic diagram.
Fig. 3 shows the flow chart of control gate and gate polysilicon etching process according to an embodiment of the invention.
Specific embodiment
In the following description, with reference to each embodiment, present invention is described.However, those skilled in the art will recognize
Know can in the case where none or multiple specific details or with other replacements and/or addition method, material or component
Implement each embodiment together.In other situations, well known structure, material or operation are not shown or are not described in detail in order to avoid making this
The aspects of each embodiment of invention is obscure.Similarly, for purposes of explanation, specific quantity, material and configuration are elaborated, with
Comprehensive understanding to the embodiment of the present invention is just provided.However, the present invention can be implemented in the case where no specific detail.This
Outside, it should be understood that each embodiment shown in the accompanying drawings is illustrative expression and is not drawn necessarily to scale.
Figure 1A to Fig. 1 N shows the diagrammatic cross-section for being used to form control gate and gate polysilicon etching process.Note that in order to
Simplify explanation, in Figure 1A to Fig. 1 N, left part is cellular zone, and right part is peripheral components area.
As shown in Figure 1A, multilayered structure is formed on substrate 100 first, wherein the multilayered structure of cellular zone is followed successively by tunnel
Oxide skin(coating) 101, doped polysilicon layer 102, silicon oxide/silicon nitride/silicon oxide layer (ONO) 103, doped polysilicon layer 104, nitrogen
SiClx layer 105, mask layer 106；The multilayered structure in peripheral components area is followed successively by tunnel oxide 101, doped polysilicon layer
102, doped polysilicon layer 104, silicon nitride layer 105, mask layer 106.
Then, which is etched, to form control gate 107 in cellular zone, and removes exposure mask
Layer 106, forms structure as shown in Figure 1B.
Cellular zone is carried out injection is lightly doped, to form lightly doped district 108, as shown in Figure 1 C.
Then, cellular zone side wall (spacer) deposition is carried out, thus conformal deposited side wall layer 109 on a surface of a wafer, such as
Shown in Fig. 1 D.In one embodiment, side wall layer 109 is silica and silicon nitride double-layer structure.
Then, the source/drain region injection of cellular zone is carried out, to form source/drain region 110 in cellular zone, as referring to figure 1E.
Next, forming protection structure 111, on cellular zone so as to the protection location area during the processing of peripheral components area
Structure is not affected.In one embodiment, photoresist can be formed on cellular zone by photoetching process as this protection structure.
Peripheral components area is etched, to remove the side wall layer 109 and silicon nitride layer 105 on external zones, as shown in fig. 1F.
Then, gate polysilicon etching is successively carried out in peripheral components area, injection is lightly doped, to form 112 He of polysilicon gate
Lightly doped district 113, as shown in Fig. 1 G to Fig. 1 H.
Protection structure 111 in removal unit area carries out the side wall deposition and etching process in peripheral components area, in periphery
Side wall 114 is formed on the polysilicon gate side wall of device region, as shown in Figure 1 I.When depositing the side wall oxide in peripheral components area,
Oxide can be also filled into the gap between the control gate of cellular zone.
Next, the source/drain region injection for carrying out peripheral components area is such as schemed with forming the source/drain region 115 in peripheral components area
Shown in 1J.
For the oxide between the control gate in removal unit area, the conformal deposited silicon heavy doping oxide first on chip
Layer 116, as shown in figure iK.
Then, photoetching and etch process are carried out, only to remove in peripheral components area on polysilicon gate 112 and source/drain region 115
Heavy doping oxide skin(coating) 116, as can be seen in 1L.
Then, wet etch process is carried out, to remove the oxide between the control gate of cellular zone, as depicted in figure iM.
Finally, one layer of metal of conformal deposited, the metal can occur with the silicon in polysilicon or silicon substrate on a surface of a wafer
Reaction form metal silicide, without with silicon nitride or oxidation pasc reaction.In one embodiment, which is nickel.Again into
The step of row removal metal, since, there are silicon nitride barrier, metal fails to react with polysilicon or silicon substrate in cellular zone
Metal silicide is generated, therefore the metal in this step of cellular zone is removed, and polysilicon gate and silicon lining in peripheral components area
The metal silicide formed on bottom is retained to form metal silicide layer 116, as shown in Fig. 1 N.
In the technique shown in Figure 1A -1N, when depositing peripheral components oxide side wall, can cellular zone control gate it
Between leave a void.After peripheral components side wall etching, a large amount of side wall oxides are left in unit area, therefore shown in Fig. 1 M
The step of in need a large amount of wet etching with the oxide in clearing cell area.
But a large amount of wet etching amount will will affect peripheral side wall and peripheral bottom silicon, and also will affect relevant device
Parameter.
Therefore the present inventor is it is further contemplated that a kind of control gate and gate polysilicon etching process out, below in conjunction with exemplary
The diagrammatic cross-section of embodiment describes this etching process.
Fig. 2A to Fig. 2 M shows cuing open for control gate according to another embodiment of the invention and gate polysilicon etching process
Face schematic diagram.
For ease of description, in Fig. 2A to Fig. 2 M, left part is cellular zone, and right part is peripheral components area.
As shown in Figure 2 A, multilayered structure is formed on substrate 200 first, wherein the multilayered structure of cellular zone is followed successively by tunnel
Oxide skin(coating) 201, doped polysilicon layer 202, silicon oxide/silicon nitride/silicon oxide layer (ONO) 203, doped polysilicon layer 204, nitrogen
SiClx layer 205, mask layer 206；The multilayered structure in peripheral components area is followed successively by tunnel oxide 201, doped polysilicon layer
202, doped polysilicon layer 204, silicon nitride layer 205, mask layer 206.
Substrate 200 can be the silicon materials including semiconductor element, such as the silicon or SiGe of monocrystalline, polycrystalline or non crystalline structure
(SiGe), the silicon (SOI) etc. being also possible on insulator.
It is different from process shown in above-mentioned Figure 1A -1N, firstly, handling to peripheral components area.
The mask layer 206 and silicon nitride layer 205 in peripheral device region can be removed by dry method etch technology appropriate,
As shown in Figure 2 B.Optional etching technics includes ion beam milling etching, plasma etching and reactive ion etching etc..
Then, doped polysilicon layer 202, the doped polysilicon layer 204 for carrying out peripheral components area are etched, more to be formed
Crystal silicon grid 207, as shown in Figure 2 C.
Peripheral region is carried out injection is lightly doped, to form lightly doped district 208, as shown in Figure 2 D.
Then, peripheral components side wall deposition and side wall etch process are carried out, to form side wall 209 on polysilicon gate 207,
During side wall etching, the hard mask layer 206 on cellular zone is removed, to form structure as shown in Figure 2 E.
Next, the source/drain region injection of peripheral region is carried out, to form the source/drain region 210 of peripheral region, such as Fig. 2 F institute
Show.
Then, cellular zone is handled.
Firstly, forming protection structure, in peripheral components area to protect peripheral components area during cellular zone is handled
Structure is not affected.In one embodiment, photoresist can be formed in peripheral components area by photoetching process as this protection
Structure.
Control gate etching is carried out to cellular zone, to form control gate 211, as shown in Figure 2 G.
Cellular zone is carried out again injection is lightly doped, to form lightly doped district 212, as illustrated in figure 2h.
The protection structure in peripheral components area is removed, cellular zone side wall deposition is carried out, thus conformal deposited side on the surface
Wall layers 213, as shown in figure 2i.In one embodiment, side wall layer 213 is silica and silicon nitride double-layer structure.
Then, the source/drain region injection of cellular zone is carried out, to form source/drain region 214 in cellular zone, as shown in fig. 2j.
Then, formation of the deposited oxide layer as stop portions region subsequent metal silicide, the then shape on cellular zone
Anisotropic dry etching is carried out at protection structure, and to peripheral components area, to remove the side wall layer 213 in wafer top surface, such as
Shown in Fig. 2 K.Equally, photoresist can be formed in peripheral components area by photoetching process as this protection structure.
In one embodiment, in order to protect 213 lower section of side wall layer in peripheral components area polysilicon and silicon substrate not by
To the damage of dry etching, stop etching when the thickness of side wall layer 213 is etched to about 10 to 70 angstroms.
Then, the protection structure in removal unit area, then wet etching is carried out, it removes remaining on polysilicon and silicon substrate
Oxide.In one embodiment, using hydrofluoric acid, remaining oxide in wafer surface is removed.
Finally, one layer of metal of conformal deposited on a surface of a wafer, passes through the metal meeting of low temperature rta technique and polycrystalline
Silicon in silicon or silicon substrate reacts to form metal silicide, without with silicon nitride or oxidation pasc reaction, followed by
High temperature rapid thermal annealing technique mutually reduces contact resistance by contact resistance by high resistant phase transition low-resistance in turn.In one embodiment
In, which is nickel.The metal is removed by selective etch again, since there are silicon nitride barrier, metals in cellular zone
Fail to react with polysilicon or silicon substrate and generate metal silicide, therefore the metal of cellular zone is removed in this step, and it is outer
The metal silicide formed on polysilicon gate and silicon substrate in peripheral device area is retained to form metal silicide layer 215, such as
Shown in Fig. 2 M.The purpose for forming the silicide of metal is to reduce resistance.
Compared with the technique shown in Figure 1A to Fig. 1 N, which is only used for the side wall retained in removal wafer surface
Layer oxide, therefore required etch quantity very little, will not impact other structures.
Etching process shown in A-2M according to fig. 2, first the gate polysilicon etching in progress peripheral components area, are then controlled
Grid etching processed, cellular zone side wall directly serve as metal silicide barrier oxide, can omit processing step shown in Fig. 1 K, thus
Simplify technique.Moreover, because the peripheral components side wall oxide on cellular zone is complete after the side wall etching in peripheral components area
Full removal, therefore do not need a large amount of wet etching.Due to reducing wet etching amount, side wall side wall and the silicon lining of peripheral components
Bottom is unaffected, and relevant device performance will not be affected.
In addition, carrying out control gate etching first, gate polysilicon etching is then carried out, is filled in peripheral components oxide side wall
There is voiding problem, this will lead to contact openings problem during cellular zone.And etching process shown in A-2M according to fig. 2, then not
There are problems that this.
Fig. 3 shows the flow chart of control gate and gate polysilicon etching process according to an embodiment of the invention.
Firstly, cellular zone multilayered structure and peripheral components area multilayered structure is formed on the substrate in step 301.
In step 302, peripheral components area multilayered structure is handled to form polysilicon gate and polysilicon gate side wall.?
In one embodiment, the processing to peripheral components area multilayered structure further includes carrying out that injection is lightly doped to peripheral region to be formed gently
The source/drain region injection of doped region, peripheral region is with techniques such as the source/drain regions that forms peripheral region.
In step 303, the multilayered structure of cellular zone is handled to form control gate.In one embodiment, to list
It includes that the techniques such as injection are lightly doped that the multilayered structure in first area, which carries out processing,.
In step 304, the conformal deposited side wall layer on cellular zone and peripheral components area surface.
Optionally, in step 305, the source/drain region injection of cellular zone is carried out.
In step 306, the side wall layer in peripheral components area on polysilicon gate and source/drain region is removed.
In step 307, metal silicide is formed on polysilicon gate and source/drain region in peripheral components area.Implement at one
In example, firstly, one layer of metal of conformal deposited on a surface of a wafer, by the low temperature rta technique metal can with polysilicon or
Silicon in silicon substrate reacts to form metal silicide, without with silicon nitride or oxidation pasc reaction, followed by high temperature
Rta technique mutually reduces contact resistance by contact resistance by high resistant phase transition low-resistance in turn, then is gone by selective etch
Except the metal, metal is generated since, there are silicon nitride barrier, metal fails to react with polysilicon or silicon substrate in cellular zone
Silicide, therefore the metal of cellular zone is removed in this step, and formed on polysilicon gate and silicon substrate in peripheral components area
Metal silicide be retained to form metal silicide layer.
The foregoing describe several embodiments of the invention.However, the present invention can be embodied as other concrete forms without carrying on the back
From its spirit or essential characteristics.Described embodiment should all be to be considered merely as illustrative and not restrictive in all respects.
Therefore, the scope of the present invention is by the appended claims rather than foregoing description limits.Fall into the equivalent scheme of claims
All changes in meaning and scope are covered by the range of claims.
Claims (11)
1. a kind of manufacturing method of memory, comprising:
Cellular zone multilayered structure and peripheral components area multilayered structure is formed on the substrate；
Peripheral components area multilayered structure is handled to form polysilicon gate and polysilicon gate side wall；
After the polysilicon gate and polysilicon gate side wall for forming the peripheral components area, etch the multilayered structure of the cellular zone with
Form control gate；
Side wall layer is deposited on the cellular zone and the peripheral components area；
Only remove the side wall layer on the polysilicon gate and source/drain region in the peripheral components area；
In peripheral components area polysilicon gate and source/drain region on form metal silicide,
Wherein, the cellular zone side wall directly serves as metal silicide barrier oxide.
2. the method as described in claim 1, which is characterized in that the processing to peripheral components area multilayered structure further includes following step
It is at least one of rapid:
After forming polysilicon gate, peripheral region is carried out injection is lightly doped；
After forming polysilicon gate side wall, the source/drain region injection of peripheral region is carried out to form the source/drain region of peripheral region.
3. the method as described in claim 1, which is characterized in that after forming control gate in cellular zone, carried out to cellular zone light
Doping injection.
4. method as claimed in claim 3, which is characterized in that after forming the side wall layer, to the cellular zone carry out source/
Drain region injection.
5. the method as described in claim 1, which is characterized in that the cellular zone multilayered structure include with one layer in lower layer or
Multilayer: tunnel oxide, doped polysilicon layer, silicon oxide/silicon nitride/silicon oxide layer, doped polysilicon layer and silicon nitride layer.
6. the method as described in claim 1, which is characterized in that peripheral components area multilayered structure includes with one in lower layer
Layer or multilayer: tunnel oxide, doped polysilicon layer, doped polysilicon layer, silicon nitride layer.
7. the method as described in claim 1, which is characterized in that remove the polysilicon gate and source/drain in the peripheral components area
Side wall layer in area at least one of includes the following steps:
Protection structure is formed on cellular zone, anisotropic dry etching is carried out to peripheral components area, by the side wall layer on top surface
Thickness etch specific thicknesses；
Protection structure in removal unit area carries out wet etching, removes remaining side wall layer on top surface.
8. the method for claim 7, which is characterized in that the specific thicknesses are 10 to 70 angstroms.
9. the method as described in claim 1, which is characterized in that in peripheral components area polysilicon gate and source/drain region on shape
At least one of include the following steps at metal silicide:
Deposited metal layer on a surface of a wafer；
To the metal layer carry out low temperature short annealing with the pasc reaction in the polysilicon gate and source/drain region in peripheral components area
Form metal silicide；
High temperature rapid thermal annealing is carried out to the metal silicide；And
Remove the metal layer not reacted.
10. method as claimed in claim 9, which is characterized in that the metal is nickel.
11. a kind of memory, including structure is manufactured by any one of claims 1 to 10 the method.
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| CN105355600A (en) * | 2014-08-20 | 2016-02-24 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of flash memory |
| CN105931992A (en) * | 2016-05-17 | 2016-09-07 | 上海华力微电子有限公司 | Technological method for forming side walls of different structures in different regions |
| CN109817625B (en) * | 2019-01-22 | 2021-05-07 | 上海华虹宏力半导体制造有限公司 | Word line polysilicon blocking oxide layer and manufacturing method thereof |
| CN109817634B (en) * | 2019-01-31 | 2021-04-13 | 长江存储科技有限责任公司 | 3D NAND memory and forming method thereof |
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