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CN105374693A - Semiconductor packages and methods of forming the same - Google Patents

Semiconductor packages and methods of forming the same Download PDF

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Publication number
CN105374693A
CN105374693A CN201410808031.XA CN201410808031A CN105374693A CN 105374693 A CN105374693 A CN 105374693A CN 201410808031 A CN201410808031 A CN 201410808031A CN 105374693 A CN105374693 A CN 105374693A
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CN
China
Prior art keywords
packaging part
bottom filler
electrical connector
tube core
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410808031.XA
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Chinese (zh)
Other versions
CN105374693B (en
Inventor
余振华
林俊成
蔡柏豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105374693A publication Critical patent/CN105374693A/en
Application granted granted Critical
Publication of CN105374693B publication Critical patent/CN105374693B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.

Description

Semiconductor package part and forming method thereof
Technical field
The present invention relates in general to semiconductor applications, more specifically, relates to semiconductor package part and forming method thereof.
Background technology
Semiconductor device is used for various electronic application, such as personal computer, mobile phone, digital camera and other electronic equipments.Semiconductor device uses each material layer of lithographic patterning to form circuit block thereon and element manufactures by square sequential aggradation insulation on a semiconductor substrate or dielectric layer, conductive layer and semiconductor material layer usually.
Semi-conductor industry experienced by fast development due to the improvement of the integration density of various electronic unit (such as, transistor, diode, resistor, capacitor etc.).To a great extent, the improvement of this integration density comes from the reducing of semiconductor technology node (such as, towards the reducing of process node of sub-20nm node).Along with in recent years to the growth of the demand of miniaturized, more speed and larger width and more low-power consumption and less delay, the less and demand having more the encapsulation technology of creationary semiconductor element is also increased.
Summary of the invention
According to an aspect of the present invention, provide a kind of method, comprising: form the first packaging part; Utilize connected structure that the second packaging part is engaged to the first packaging part, connected structure is connected to the first electrical connector; And bottom filler is formed between the first packaging part and the second packaging part.Wherein, form the first packaging part to comprise: above carrier substrates, form the first dielectric layer; The first electrical connector is formed at the first dielectric layer; By the first die attach for adjacent with the first electrical connector and be positioned at the first dielectric layer; Redistributing layer is formed above the first tube core and the first electrical connector; Above redistributing layer, form the second electrical connector, the second electrical connector is connected at least one in the first tube core and the first electrical connector; Remove carrier substrates to expose the first dielectric layer; With removal first dielectric layer to expose a part for the first tube core and the first electrical connector.
Preferably, between the first packaging part and the second packaging part, form bottom filler comprise: utilizing after the first packaging part is engaged to the first packaging part by connected structure, between the first packaging part and the second packaging part, inject bottom filler, bottom filler is around connected structure.
Preferably, inject bottom filler between the first packaging part and the second packaging part after, a part for the first tube core is exposed through bottom filler.
Preferably, between the first packaging part and the second packaging part, forming bottom filler comprise: utilizing before the first packaging part is engaged to the second packaging part by connected structure, above the first packaging part, forming bottom filler; With pattern bottom filler, at least to expose a part for the first electrical connector.
Preferably, pattern bottom filler also comprises: pattern bottom filler is to expose a part for the first tube core.
Preferably, between the first packaging part and the second packaging part, form bottom filler to comprise: form liquid epoxies, deformability gel, silicon rubber, non-conductive film, polymer, polybenzoxazole, polyimides, solder resist or their combination.
Preferably, remove the first dielectric layer also to comprise: etch the first dielectric layer to expose a part for the first tube core and the first electrical connector.
Preferably, remove the first dielectric layer also to comprise: grind the first dielectric layer to expose a part for the first tube core and the first electrical connector.
Preferably, form the first packaging part and also comprise: utilize moulding material to encapsulate the first tube core and the first electrical connector, the first electrical connector extends through moulding material, the second electrical connector is metal coupling.
According to a further aspect in the invention, provide a kind of method, comprising: form the first die package, the first die package comprises the first tube core, the first electrical connector and the first redistributing layer, and the first redistributing layer is connected to the first tube core and the first electrical connector; Bottom filler is formed above the first die package; Pattern bottom filler is to have the opening of the part exposing the first electrical connector; And utilizing connected structure that the second die package is engaged to the first die package, connected structure is connected to the first electrical connector in the opening of bottom filler.
Preferably, the method also comprises: the first die package and the second die package and adjacent die package are separated to form semiconductor package part, semiconductor package part comprises the first die package and the second die package.
Preferably, form the first die package also to comprise: above the first carrier substrates, form the first dielectric layer; Form the first electrical connector at the first dielectric layer, the first electrical connector extends from the first side of the first dielectric layer; By the first side of the first die attach to the first dielectric layer; Utilize moulding material to encapsulate the first tube core and the first electrical connector, the first electrical connector extends through moulding material; The first redistributing layer is formed above the first tube core, the first electrical connector and moulding material; Remove the first carrier substrates to expose the second side of the first dielectric layer, the second side is relative with the first side; And remove the first dielectric layer with the back side at the back side and the first electrical connector of exposing the first tube core, bottom filler is formed in the back side exposed of the first tube core and the back side exposed of the first electrical connector.
Preferably, the back side of the first tube core also comprises die attach film.
Preferably, there is through the bottom filler of patterning the sidewall at the back side being basically perpendicular to the first tube core.
Preferably, above the first die package, form bottom filler to comprise: form liquid epoxies, deformability gel, silicon rubber, non-conductive film, polymer, polybenzoxazole, polyimides, solder resist or their combination.
Preferably, the method also comprises: pattern bottom filler is positioned to be formed the opening aimed at above the first tube core and with the first tube core, and the width of opening is less than the width of the first tube core.
According to another aspect of the invention, provide a kind of semiconductor package part, comprise the first packaging part, the second packaging part and bottom filler.First packaging part comprises: the first tube core; Encapsulant, around the first tube core; And package via, extend through encapsulant.Second packaging part, comprises the second tube core, and the second packaging part is engaged to the first packaging part by one group of connector; And bottom filler, between the first packaging part and the second packaging part and around one group of connector, bottom filler has the sidewall at the back side being basically perpendicular to the first tube core.
Preferably, bottom filler comprises liquid epoxies, deformability gel, silicon rubber, non-conductive film, polymer, polybenzoxazole, polyimides, solder resist or their combination.
Preferably, bottom filler has the first opening be positioned at above the first tube core, and the width of the first opening is less than the width of the first tube core.
Preferably, the first packaging part has the first width and the second packaging part has the second width, and the second width is less than the first width.
Accompanying drawing explanation
When read with the accompanying drawing figures, various aspects of the present invention are understood according to following description in detail.Note, according to the standard practices of industry, all parts is not drawn in proportion.In fact, clear in order to what discuss, the size of all parts can increase arbitrarily or reduce.
Figure 1A to Fig. 1 J shows the sectional view of the intermediate steps of formation first packaging part according to some embodiments.
Fig. 2 A to Fig. 2 C shows the second packaging part is attached to the first packaging part shown in Figure 1A to Fig. 1 J and packaging part is divided into the sectional view of the intermediate steps of semiconductor package part according to some embodiments.
Fig. 3 A to Fig. 3 C shows the sectional view of the semiconductor package part according to some embodiments.
Fig. 4 A and Fig. 4 B shows the sectional view of the intermediate steps of the formation semiconductor package part according to some other embodiments.
Fig. 5 A to Fig. 5 C shows the sectional view of the semiconductor package part according to some other embodiments.
Fig. 6, Fig. 7 A and Fig. 7 B shows the sectional view of the intermediate steps of the formation semiconductor package part according to some other embodiments.
Fig. 8 shows the sectional view of the semiconductor package part according to some embodiments.
Embodiment
The following disclosure provides embodiment or the example of many different different characteristics for implementing present subject matter.The instantiation of parts or configuration is below described to simplify the present invention.Certainly, these are only example and are not used in restriction.Such as, in the following description, above second component or on form first component and can comprise the embodiment that first component and second component be formed directly to contact, and also can comprise and can form at first component and second component the embodiment that accessory components make first component and Part II directly not contact.In addition, the present invention can repeat reference numerals and/or letter in various embodiments.These repeat to be to simplify and clear, itself do not represent the relation between each discussed embodiment and/or structure.
In addition, for ease of describing, can usage space relative terms (such as " in ... below ", " under ", " bottom ", " top ", " top " etc.) to describe the relation of an element or parts and another element or parts shown in figure.Except the orientation shown in figure, the difference that space relative terms also comprises equipment in use or operation is directed.Device can otherwise directed (90-degree rotation or be in other directed), and therefore space used herein describes relatively can carry out similar explanation.
With reference to the embodiment (that is, three-dimensional (3D) integrated fan-out (InFO) stacked package (PoP) device) under specific condition, embodiment is described.But, other embodiments can also be applied to the parts of other electrical connections, include but not limited to the assembly in piled-up packing assembly, tube core-die assemblies, wafer-wafer assembly, die-substrate assembly, assembling, the substrate, mediplate, substrate etc. in process, or install input block, plate, tube core or miscellaneous part, or for the integrated circuit of any type that connects or the encapsulation of electric parts or install combination.
Figure 1A to Fig. 1 J shows the sectional view of the intermediate steps of formation two the first semiconductor package parts 100 according to some embodiments.The first semiconductor package part in Figure 1A comprises the crystal seed layer 108 above the adhesive layer 104 above carrier substrates 102, the dielectric layer 106 above adhesive layer 104 and dielectric layer 106.Carrier substrates 102 can be any suitable substrate, and its (during intermediary operation of manufacturing process) provides mechanical support for each layer above carrier substrates 102.Carrier substrates 102 can for comprising the wafer of glass, silicon (such as, Silicon Wafer), silica, metallic plate, ceramic material etc.
In carrier substrates 102 that adhesive layer 104 can be arranged on (such as, being laminated to).Adhesive layer 104 can be formed by the glue of such as ultraviolet (UV) glue, photothermal deformation (LTHC) material, or the laminate layers that can become for slice-shaped.
Dielectric layer 106 is formed in above adhesive layer 104.Dielectric layer 106 can be silicon nitride, carborundum, silica, low K dielectrics (such as, carbon-doped oxide), Ultra low k dielectric (such as, mix the silicon dioxide of porous carbon), polymer (such as epoxy resin, polyimides, benzocyclobutene (BCB), polybenzoxazole (PBO) etc.) or their combination, although other relatively soft organic dielectric materials can also be used.Dielectric layer 106 deposits by chemical vapor deposition (CVD), physical vapor deposition (PVD), ald (ALD), spin-on dielectric processes etc. or their combination.
Crystal seed layer 108 is formed in above dielectric layer 106.Crystal seed layer 108 can be made up of copper, titanium, nickel, gold etc. or their combination.Crystal seed layer 108 deposits by PVD, CVD, ALD etc. or their combination.
Figure 1B shows patterned seed layer 108 and forms electrical connector 110.Crystal seed layer 108 carries out patterning by etch process or any other suitable Patternized technique.
Electrical connector 110 can be formed in above crystal seed layer 108 and to extend out from crystal seed layer 108 on the direction on surface being basically perpendicular to dielectric layer 106.In certain embodiments, electrical connector 110 is formed by plating.In these embodiments, electrical connector 110 is made up of copper, aluminium, nickel, gold, silver, platinum, tin etc. or their combination, and can have the composite construction comprising multilayer.In these embodiments, the sacrifice layer 112 of such as photoresist is formed in above carrier substrates.In certain embodiments, crystal seed layer 108 is formed and patterned photo glue 112, then in the photoresist 112 of patterning, forms electrical connector 110.Photoresist 112 is formed by the wet process of such as spin coating proceeding or the dry process that such as applies dry film.Multiple opening is formed with the crystal seed layer 108 below exposing in photoresist 112.Then, plating step is performed to carry out plating operation to electrical connector 110.
In an alternative embodiment, electrical connector 110 can be column-like projection block, and it is formed to make a part for combined leads be attached to corresponding engagement ball by carrying out wire-bonded and cut combined leads above dielectric layer 106.Such as, electrical connector 110 can comprise bottom and top, and wherein, bottom can be the engagement ball (not shown) formed with wire-bonded, and top can be remaining combined leads (not shown).The top of electrical connector 110 can have uniform width and uniform shape, and its top section on whole top, mid portion and low portion are all uniform.Electrical connector 110 can be formed by non-welding metal material, and it engages by wire bonder.In certain embodiments, electrical connector 110 is made up of copper cash, gold thread etc. or their combination, and can have the composite construction comprising multilayer.In wirebond embodiment, crystal seed layer 108 and sacrifice layer 112 can be omitted.
Electrical connector 110 can form the dorsal part redistributing layer for the first packaging part.This dorsal part redistributing layer can be used for another packaging part or parts (see Fig. 2 A) to be connected to the first packaging part.
Fig. 1 C shows and removes sacrifice layer 112.Sacrifice layer 112 removes by suitable removal technique (such as, ashing or etch process).
Fig. 1 D shows and tube core 120 is attached to dielectric layer 106.First side of tube core 120 can utilize adhesive layer 126 to be attached to dielectric layer 106.Adhesive layer 126 can be any suitable adhesive, such as, and die attach film etc.Tube core 120 can be singulated dies or can for more than the tube core of two.Tube core 120 can comprise logic dice, Graphics Processing Unit (GPU) etc. or their combination of such as CPU (CPU).In certain embodiments, tube core 120 comprises die-stack part (not shown).It can comprise logic dice and store tube core.Tube core 120 can comprise I/O (I/O) tube core (such as, wide I/O tube core), and it provides connection between the first packaging part 10 and the second packaging part 200 (see Fig. 2 A) be attached subsequently.
Tube core 120 comprises the contact area 124 be positioned on the second side of tube core 120.In certain embodiments, contact area 124 is bond pad.Bond pad 124 can be formed in above the second side of tube core 120.In certain embodiments, bond pad 124 is by forming groove (not shown) to be formed in the dielectric layer (not shown) on the second side of tube core 120.Groove can be formed be embedded in dielectric layer to allow bond pad 124.In other embodiments, groove is omitted, because bond pad 124 can be formed on the dielectric layer.Bond pad 124 is by tube core 120 electricity and/or be physically connected to the second packaging part 200 (see Fig. 2 A) and/or the electrical connector 110 engaged subsequently.In certain embodiments, bond pad 124 comprises the thin crystal seed layer (not shown) be made up of copper, titanium, nickel, gold, tin etc. or their combination.The electric conducting material of bond pad 124 can be deposited on above thin crystal seed layer.Electric conducting material is formed by electrochemistry depositing process, CVD, ALD, PVD etc. or their combination.In one embodiment, the electric conducting material of bond pad 124 is copper, tungsten, aluminium, silver, gold, tin etc. or their combination.
In one embodiment, contact area 124 is for comprising the Underbump metallization (UBM) of three layers of electric conducting material (such as, titanium layer, layers of copper and nickel dam).But, it will be appreciated by those skilled in the art that can have many being suitable for forms the suitable material of UBM124 and the configuration of layer, such as, the configuration of chromium/chromium-copper alloy/copper/gold, the configuration of titanium/titanium tungsten/copper or the configuration of copper/nickel/gold.Any suitable material or the material layer that can be used for UBM124 are all included in the scope of the application.
Fig. 1 E shows the encapsulation of tube core 120 and electrical connector 110.In certain embodiments, tube core 120 and electrical connector 110 are encapsulated by moulding material 130.Moulding material 130 can such as use compression molded and be molded on tube core and electrical connector 110.In certain embodiments, moulding material 130 is made by moulding compound, polymer, epoxy resin, silica-filled material etc. or their combination.Can perform curing schedule to solidify moulding material 130, wherein, solidification can be hot curing, UV solidification etc. or their combination.
In certain embodiments, as referring to figure 1e, tube core 120, contact area 124 and electrical connector 110 can be imbedded in moulding material 130, and after solidification moulding material 130, moulding material 130 are performed to the planarization steps of such as grinding.Planarization steps is for removing the excessive portion of moulding material 130, and wherein excessive portion is positioned at the top face of contact area 124 and electrical connector 110.In certain embodiments, the surface of contact area 124 and the surperficial 110A of electrical connector 110 expose, and concordant with the surperficial 130A of moulding material 130 and the surperficial 120A of tube core 120.Electrical connector 110 can be described as molded through hole (TMV), package via (TPV) and/or InFO through hole (TIV), and hereinafter referred to as TIV110.
In other embodiments, contact area 124 is the through holes partly extended to from the second side of tube core 120 tube core 120, or in certain embodiments, is the through hole extending fully through tube core 120.Through hole 124 can form hole (not shown) by etch process and be formed and carry out filler opening with the electric conducting material of such as copper, aluminium, nickel, gold, silver, platinum, tin etc. or their combination in tube core 120, and hole can have the composite construction comprising multilayer.Tube core 120 can also comprise crystal seed layer, barrier layer, lining etc. or their combination.
Fig. 1 F shows and form redistributing layer 131 above tube core 120, TIV110 and moulding material 130.Redistributing layer 131 can comprise one or more metal level (sometimes referred to as M 1and/or M n), wherein, metal level M 1directly adjacent with tube core 120 metal level, and metal level M n(be sometimes referred to as metal layer at top M n) be distance tube core 120 metal level farthest.In whole description, term " metal level " is the set of the metal wire 132 in same layer.Redistributing layer 131 can comprise one or more passivation layer 134, wherein, and one or more metal level (M 1to M n) be arranged in one or more passivation layer 134.
Passivation layer 134 can be silicon nitride, carborundum, silica, low K dielectrics (such as, carbon-doped oxide), pole low K dielectrics (such as, mix the silicon dioxide of porous carbon), polymer (such as, epoxy resin, polyimides, BCB, PBO), solder resist (SR) etc. or their combination, although other relatively soft organic dielectric materials can also be used, and can be deposited by CVD, PVD, ALD, spin-on dielectric processes, laminating technology etc. or their combination.Passivation layer 134 can stand curing schedule to solidify passivation layer 134, and wherein, solidification can be hot curing, UV solidification etc. or their combination.
Metal level 132 can use list and/or dual-damascene technics, first via process or first smithcraft to be formed.Metal level 132 and through hole can be formed by the electric conducting material of such as copper, aluminium, titanium etc. or their combination, can have or not have barrier layer.
Mosaic technology refers to that the formation of the layer of the patterning be embedded in another layer makes the end face of two layers coplanar.The mosaic technology only forming groove or through hole is known as single mosaic technology.The mosaic technology simultaneously forming groove and through hole is known as dual-damascene technics.
In the exemplary embodiment, dual-damascene technics is used to form metal level 132.In this example, M 1then first layer can form next passivation layer 134 formed by forming etching stopping layer (not shown) on the passivation layer 134 of foot on etching stopping layer.Once deposited next passivation layer 134, just can etch away each several part of next passivation layer 134 to form groove type parts (such as, groove and through hole), its can filled conductive material to connect the zones of different of redistributing layer 134 and accommodating metal wire 132 and through hole.This process can be repeated until M for each layer of remaining metal nlayer.
Redistributing layer 131 can be described as the front side redistributing layer of the first packaging part 100.Front side redistributing layer 131 can be used for, by connector 136, first packaging part 100 is connected to one or more packaging part, package substrate, parts etc. or their combination (see Fig. 1 G).
The number of metal level 132 and the number of passivation layer 134 are only be not used in restriction in order to the object illustrated.Other number target zones being greater than or less than a shown metal level can also be had.Can also have and be different from the passivation layer of other numbers shown in Fig. 1 F, the metal level of other numbers.
Fig. 1 G shows and above redistributing layer 131, forms one group of conducting connecting part 136 and be electrically connected to redistributing layer 131.The projection etc. that conducting connecting part 136 can be formed for soldered ball, metal column, controlled collapse chip connection (C4) projection, dimpling block, chemical nickel platinum technology for gold extraction (ENEPIG).Conducting connecting part 136 can comprise electric conducting material, such as, and solder, copper, aluminium, gold, nickel, silver, platinum, tin etc. or their combination.Be in the embodiment of solder projection at conducting connecting part 136, first conducting connecting part 136 is formed by conventional method (such as, evaporation, plating, printing, solder transfer, soldered ball storing etc.) formation solder layer.Once solder layer is formed structurally, just perform backflow to make the projection shape of material forming for expecting.In another embodiment, conducting connecting part 136 is the metal column (such as, copper post) formed by sputtering, printing, plating, electroless plating, CVD etc.Metal column can be solderless, and has substantially vertical sidewall.In certain embodiments, metallic cover layer (not shown) is formed on the top of metal column connector 136.Metallic cover layer can comprise nickel, tin, tin-lead, gold, silver, platinum, indium, nickel-platinum-Jin, nickel-Jin etc. or their combination, and can be formed by depositing process.
Although not shown, can there is the UBM being connected to redistributing layer, conducting connecting part 136 is connected to UBM (not shown).UBM is formed by first forming one group of opening (not shown), and this group opening passes the passivation layer 134 at top until expose metal level M nin metal wire.UBM can extend across these openings in passivation layer 134, and extends along the surface of passivation layer 134.UBM can comprise three conductive material layers, such as, and titanium layer, layers of copper and nickel dam.But, it will be appreciated by those skilled in the art that can there is many being suitable for forms the suitable material of UBM and the configuration of layer, such as, the configuration of chromium/chromium-copper alloy/copper/gold, the configuration of titanium/titanium tungsten/copper or the configuration of copper/nickel/gold.The suitable material layer of any UBM of can be used for is included in the scope of the application all completely.
Fig. 1 H shows according to the removal carrier substrates 102 of an embodiment and adhesive layer 104 to expose dielectric layer 106.In this embodiment, while removal carrier substrates 102 and adhesive layer 104, the first packaging part is placed on frame 138, and wherein conducting connecting part 136 adjoins with frame 138.
Fig. 1 I shows according to the removal carrier substrates 102 of another embodiment and adhesive layer 104 to expose dielectric layer 106.In this embodiment, while removal carrier substrates 102 and adhesive layer 104, the first packaging part is placed on Second support substrate 140, and wherein conducting connecting part 136 adjoins with Second support substrate 140.This embodiment can comprise the adhesive 142 on Second support substrate 140, and conducting connecting part 136 is embedded in adhesive 142.Adhesive 142 can assist in ensuring that the first packaging part 100 is fixed to Second support substrate 140.After removal carrier substrates 102, remove adhesive 142 by stripping means (comprising thermal process, chemical stripping technique, laser ablation, UV process etc. or their combination).
Fig. 1 J shows the removal of dielectric layer 106.Dielectric layer 106 is removed by suitable removal technique (such as, etch process).After removal dielectric layer 106, expose a part of tube core 120 and TIV110.The back side 110B of TIV110 is exposed, and it can comprise crystal seed layer 108.In addition, the back side 120B of tube core 120 is exposed, and it can comprise adhesive layer 126.In certain embodiments, after removal dielectric layer 106, TIV110 is slotted by such as etch process.In certain embodiments, adhesive layer 126 is removed to expose the surface of tube core 120.In other embodiments, when tube core 120 being attached to carrier substrates 102 (see Fig. 1 C), adhesive layer 126 is not used.In certain embodiments, surperficial 130B and 120B is substantially coplanar and higher than surperficial 110B.In other words, TIV110 can be recessed in moulding material 130.
Fig. 2 A to Fig. 2 C shows the second packaging part is attached to the first packaging part shown in Figure 1A to Fig. 1 J and packaging part is divided into the sectional view of the intermediate steps of semiconductor package part according to some embodiments.With reference to Fig. 2 A, utilize one group of conducting connecting part 210 that second packaging part 200 is engaged to the first packaging part 100, form semiconductor package part 300.
Second packaging part 200 includes substrate 202 and is connected to the one or more stacking tube core 212 (212A and 212B) of substrate 202.Substrate 202 can be made up of semi-conducting material (such as, silicon, germanium, diamond etc.).Alternatively, combination materials (such as, SiGe, carborundum, GaAs, indium arsenide, indium phosphide, carbonization SiGe, gallium phosphide arsenic, InGaP, their combination etc.) can also be used.In addition, substrate 202 can be silicon-on-insulator (SOI) substrate.Usually, SOI substrate comprises semiconductor material layer, such as, and epitaxial silicon, germanium, SiGe, SOI, sige-on-insulator (SGOI) or their combination.In one alternate embodiment, substrate 202 is the insulation core based on such as galss fiber reinforced resin core.An Exemplary core material is the glass fiber resin of such as FR4.Alternate material for nuclear material comprises bismaleimide-triazine (BT) resin, or alternatively, comprises other printed circuit board (PCB)s (PCB) material or film.Laminated film or other laminate of such as aginomoto laminated film (ABF) can be used for substrate 202.Substrate 202 can be described as package substrate 202.
Substrate 202 can comprise active and passive device (not shown in Fig. 2 A).It will be appreciated by those skilled in the art that such as transistor, capacitor, resistor, their the various devices of combination etc. can be used for the 26S Proteasome Structure and Function requirement of the design meeting semiconductor package part 300.Any suitable method can be used to form these devices.
Substrate 202 can also comprise metal layer (not shown) and through hole 208.Metal layer can be formed in above active and passive device, and is designed to connect each device to form functional circuit.Metal layer can by dielectric layer (such as low k dielectric) and electric conducting material (such as, copper) layer alternately formation, wherein each conductive material layer interconnects by through hole, and forms metal layer by any suitable technique (such as deposit, inlay, dual damascene etc.).In certain embodiments, substrate 202 does not have active and passive device substantially.
Substrate 202 can have bond pad 204 to be connected to stack chip 212 on the first side of substrate 202, and on the second side of substrate 202, has bond pad 206 to be connected to conducting connecting part 210, and wherein the second side is relative with the first side of substrate 202.In certain embodiments, bond pad 204 and 206 by forming groove (not shown) to be formed in the dielectric layer (not shown) on first side and the second side of substrate 202.Groove can be formed be embedded in dielectric layer to allow bond pad 204 and 206.In other embodiments, groove is omitted, because bond pad 204 and 206 can be formed on the dielectric layer.In certain embodiments, bond pad 204 and 206 comprises the thin crystal seed layer (not shown) be made up of copper, titanium, nickel, gold, platinum etc. or their combination.The electric conducting material of bond pad 204 and 206 can be deposited on above thin crystal seed layer.Electric conducting material is formed by electrochemistry depositing process, electroless plating, CVD, ALD, PVD etc. or their combination.In one embodiment, the electric conducting material of bond pad 204 and 206 is copper, tungsten, aluminium, silver, gold etc. or their combination.
In one embodiment, bond pad 204 and 206 is that UBM, UBM comprise three conductive material layers, such as, and titanium layer, layers of copper and nickel dam.But, it will be appreciated by those skilled in the art that can also have many being suitable for forms the suitable material of UBM204 and 206 and the configuration of layer, such as, the configuration of chromium/chromium-copper alloy/copper/gold, the configuration of titanium/titanium tungsten/copper or the configuration of copper/nickel/gold.Any suitable material or the material layer that can be used for UBM204 and 206 are included in the scope of the application all completely.In certain embodiments, through hole 208 extends through substrate 202, and at least one bond pad 204 is connected to bond pad 206.
In the embodiment shown, stack chip 212 is connected to substrate 202 by bonding wire 214, although can also use other connectors of such as conductive projection.In one embodiment, stack chip 212 is stacking storage tube cores.Such as, stacking storage tube core 212 can comprise low-power (LP) double data rate (DDR) memory module, such as, and LPDDR1, LPDDR2, LPDDR3 or similar memory module.
In certain embodiments, stack chip 212 and bonding wire 214 encapsulate by moulding material 216.Such as use compression molded moulding material 216 can being molded on stack chip 212 and bonding wire 214.In certain embodiments, moulding material 216 is moulding compound, polymer, epoxy resin, silica-filled material etc. or their combination.Can perform curing schedule to solidify moulding material 216, wherein, solidification can be hot curing, UV solidification etc. or their combination.
In certain embodiments, stack chip 212 and bonding wire 214 are imbedded in moulding material 216, and after solidification moulding material 216, perform the planarization steps of such as grinding to remove the excessive portion of moulding material 216, and provide the surface of substantially flat for the second packaging part 200.
After formation second packaging part 200, the second packaging part 200 is engaged to the first packaging part 100 by conducting connecting part 210, bond pad 206 and TIV110.In certain embodiments, stacking storage tube core 212 is connected to tube core 210 by bonding wire 214, bond pad 204 and 206, through hole 208, conducting connecting part 210 and TIV110.
Conducting connecting part 210 can be similar to above-mentioned conducting connecting part 136, and therefore the descriptions thereof are omitted here, although conducting connecting part 210 and 136 is not must be identical.In certain embodiments, before engaged conductive connector 210, conducting connecting part 210 scribbles the solder flux (not shown) of such as exempting from clean solder flux.Conducting connecting part 210 can immerse in solder flux, or solder flux can spray to conducting connecting part 210.In another embodiment, solder flux can put on the surface of TIV110.
Joint between second packaging part 200 and the first packaging part 100 can be that solder bonds or direct metal-metal (such as, copper-copper or Xi-Xi) engage.In one embodiment, the second packaging part 200 is engaged to the first packaging part 100 by reflux technique.During this reflux technique, conducting connecting part 210 contacts with TIV110 with bond pad 206, with by the second packaging part 200 physical connection and be electrically connected to the first packaging part 100.After joint technology, intermetallic compound (IMC) 218 can be formed in the interface between TIV110 and conducting connecting part 210, and is formed in the interface between conducting connecting part 210 and bond pad 206 (not shown).
Fig. 2 B shows between the first packaging part 100 and the second packaging part 200 and form bottom filler 220 between each conducting connecting part 200.Bottom filler 220 can by liquid epoxies, deformability gel, silicon rubber, non-conductive film, polymer, PBO, polyimides, solder resist or they be combined to form.Bottom filler 220 provides support structure for conducting connecting part 210, and capillary force can be used after conducting connecting part 210 is bonded between the first packaging part 100 and the second packaging part 200 to distribute bottom filler 220.In these embodiments, bottom filler 220 comprises chamfering (fillet), and wherein, sidewall 220A is diagonal to the back side 120B of tube core 120.In certain embodiments, bottom filler 220 is formed to form opening 222 above tube core 120.
Fig. 2 C shows the semiconductor package part 300 of segmentation.Semiconductor package part 300 can remove from frame 138 and be placed on the top of the structure 232 of such as cutting belt.Semiconductor package part 300 is split by cutting tool 234 (such as, tube core saw, laser etc. or their combination).
The first packaging part 100 in Figure 1A to Fig. 1 J and Fig. 2 A to Fig. 2 C and the quantity of the second packaging part 200 are only be not used in restriction in order to the object illustrated.The packaging part of other quantity being greater than or less than shown two packaging parts can also be had.
Fig. 3 A to Fig. 3 C shows the sectional view according to the semiconductor package part 300 of embodiment dimly.With reference to Fig. 3 A, this embodiment has the bottom filler 220 comprising chamfering.First packaging part 100 has width W 100, the second packaging part has width W 200, and bottom filler 220 has the outer wide W between the first and second packaging parts 100 and 200 220.Opening 222 in bottom filler 220 has width W 222, and tube core 120 has width W 120.In one embodiment, width W 220be less than or equal to width W 100, width W 200be less than or equal to width W 220, and width W 222be less than or equal to width W 120.In another embodiment, width W 220be less than width W 100, width W 200be less than width W 220, and width W 222be less than width W 120.Bottom filler 220 has height H between the first and second packaging parts 100 and 200 220(being sometimes referred to as standing height).In one embodiment, height H 220in the scope of about 1 μm to about 200 μm.
Fig. 3 B shows another embodiment of semiconductor package part 300.This embodiment is similar to the embodiment of Fig. 3 A, except not having opening (see 222 in Fig. 3 A) in bottom filler 220.Opening 222 forms bottom filler 220 by the middle section only not at semiconductor package part 300 around the outer rim of semiconductor package part 300 and is formed.About this embodiment, no longer the content similar with previously described embodiment will be repeated here.
Fig. 3 C shows another embodiment of semiconductor package part 300.Embodiment in this embodiment and Fig. 3 B is similar, except being gripped with resilient coating 230 between the first packaging part 100 and bottom filler 220.About this embodiment, no longer the content similar with previously described embodiment will be repeated here.
Resilient coating 230 is formed in above tube core 120 (also having adhesive layer 126 if present), TIV110 and moulding material 130.Resilient coating 230 can be formed by polymer (such as, polyimides, PBO etc.).Resilient coating 230 also can be LTHC material.In one embodiment, resilient coating 230 is formed to have the thickness of about 0.1 μm to about 20 μm.
By removing dielectric layer 106 from the first packaging part 100, the warpage of the first packaging part 100 can be reduced, therefore can improve the coplanarity between the first packaging part 100 and the second packaging part 200 and standing height control.In addition, the use of exempting from clean solder flux eliminates the residual problem of solder flux between the first packaging part 100 and the second packaging part 200.In addition, by forming bottom filler 220 before cutting technique, protection conducting connecting part 210 is not by the impact of the fault (short circuit such as, between conducting connecting part) caused by fragment of cutting technique.In addition, between semiconductor package part 300, providing larger space for bottom filler 220 by making the width of the second packaging part be less than the width of the first packaging part 100, preventing oozing out of the bottom filler between the pollution of the bottom filler between two semiconductor package parts 300 and the second adjacent packaging part 200.
Fig. 4 A and Fig. 4 B shows the sectional view of the intermediate steps of the formation semiconductor package part 300 according to some other embodiments.This embodiment is similar to the embodiment of Figure 1A to Fig. 1 J and Fig. 2 A to Fig. 2 C, is formed and pattern bottom filler 220 before being engaged to the second packaging part 200 at the first packaging part 100.About this embodiment, no longer the content similar with previously described embodiment will be repeated.
Fig. 4 A shows the intermediate fabrication steps completed after the step shown in Figure 1A to Fig. 1 J.After the step of Fig. 1 J, bottom filler 220 is formed in above tube core 120, moulding material 130 and TIV110.Bottom filler 220 by CVD, PVD or ALD deposition, by the wet process of such as spin coating proceeding, silk screen printing process or formed by the dry process of such as roll extrusion dry film.Formation bottom filler 220 after, bottom filler 220 is patterned above TIV110, form opening 224, with expose TIV110 (with crystal seed layer 108, a part if present).In certain embodiments, bottom filler 220 is patterned so that at tube core 120, (with adhesive layer 126, if present) top forms opening 222.Pattern bottom filler 220 is carried out by using acceptable photoetching technique and etching (such as, laser etch process).Opening 222 is formed to have width W 222and opening 224 is formed to have width W 224.In one embodiment, width W 222be less than or equal to width W 120, and width W 224be less than or equal to the width W of TIV110 110.In another embodiment, width W 222be less than width W 120, and width W 224be less than width W 110.In the embodiment comprising resilient coating 230 (see Fig. 3 C and Fig. 5 C), the A/F of the resilient coating 130 in opening 224 is less than or equal to width W 224.Bottom filler 220 can be formed as the height H had in the scope of 1 μm to about 200 μm 220.In this embodiment, bottom filler 220 has the sidewall 220A of the back side 120B being basically perpendicular to tube core 120.In certain embodiments, bottom filler 220 is patterned, and makes to there is not bottom filler 220 in the line between the first adjacent packaging part 100.
Fig. 4 B shows and the second packaging part 200 is attached to the first packaging part 100 shown in Fig. 4 A.This is similar to above with reference to the technique described in Fig. 2 A, except there is bottom filler 220 during joint technology.About this embodiment, no longer repeat the content similar with previously described embodiment.Then, packaging part 200 and 100 will such as be split above with reference to the carrying out described by Fig. 2 C.
Fig. 5 A to Fig. 5 C shows the sectional view of the semiconductor package part 300 according to some other embodiments.These embodiments are similar to the embodiment described in Fig. 3 A to Fig. 3 C, except the sidewall 220A defining bottom filler 220 and bottom filler 220 in these embodiments before being joined together by packaging part is basically perpendicular to the back side of tube core 120 and does not have chamfering.About this embodiment, no longer repeat the content similar with previously described embodiment.
With reference to Fig. 5 A, bottom filler 220 has the opening 222 above tube core 120.Fig. 5 B shows bottom filler 220 and does not have opening 222 above tube core 120.Fig. 5 C shows wherein resilient coating 230 and is positioned at semiconductor package part 300 above the first packaging part 100.
By removing dielectric layer 106 from the first packaging part 100 and formed bottom filler 220 before bond package part, the warpage of the first packaging part 100 can be reduced, therefore can improve the coplanarity between the first packaging part 100 and the second packaging part 200 and standing height.In addition, by forming bottom filler 220 before division process, protection conducting connecting part 210 is not by the impact of the fault (short circuit such as, between conducting connecting part) caused by fragment of division process.In addition, for bottom filler 220 provides larger space between semiconductor package part 300, the problem that the pollution of the bottom filler between two semiconductor package parts 300 and bottom filler overflow between the second adjacent packaging part 200 is prevented by making the second packaging part 200 be less than the first packaging part 100.
Fig. 6, Fig. 7 A and Fig. 7 B shows the sectional view of the intermediate steps of the formation semiconductor package part according to some other embodiments.This embodiment is similar to above with reference to the embodiment shown in Fig. 1 J, except utilizing grinding technics but not etch process removes dielectric layer 106.About this embodiment, no longer the content similar with previously described embodiment will be repeated.
In this embodiment, grinding technics can be chemico-mechanical polishing (CMP) technique.Grinding technics can remove crystal seed layer 108 and adhesive layer 126.In certain embodiments, surperficial 130B, 120B and 110B are substantially coplanar.In some other embodiments, surperficial 130B and 120B is substantially coplanar, and surperficial 110B is recessed in moulding material 130.
The process of this embodiment can proceed attachment second packaging part 200 described by Fig. 2 A to Fig. 2 C and split.Arbitrary bottom filler scheme that this embodiment can adopt Fig. 2 A to Fig. 3 C and Fig. 4 A and Fig. 5 C to propose.
Fig. 7 A shows according to the first packaging part 100 in Fig. 6 and the sectional view of the semiconductor package part 300 utilizing the bottom filler scheme with chamfering in Fig. 2 A to Fig. 3 C and formed.Although bottom filler 220 is shown having opening 222, opening 222 can be omitted.Fig. 7 B shows according to the first packaging part 100 in Fig. 6 and the sectional view of the semiconductor package part 300 utilizing the non-chamfering bottom filler scheme of Fig. 4 A to Fig. 5 C and formed.
Fig. 8 shows the sectional view of the semiconductor package part 400 according to some embodiments.Semiconductor package part 400 comprises the semiconductor package part 300 being mounted to package substrate 402.Semiconductor package part 300 can be any embodiment of above-mentioned semiconductor package part 300.Semiconductor package part 300 uses conducting connecting part 136 to be mounted to package substrate 402.
Package substrate 402 can be made up of the semi-conducting material of such as silicon, germanium, diamond etc.Alternatively, can also compound-material be used, such as, SiGe, carborundum, GaAs, indium arsenide, indium phosphide, carbonization SiGe, gallium arsenide phosphide, phosphorus indium gallium, their combination etc.Therefore, package substrate 402 can be SOI substrate.Usually, SOI substrate comprises the semiconductor material layer of such as epitaxial silicon, germanium, SiGe, SOI, SGOI or their combination.In one alternate embodiment, package substrate 402 is based on the insulation core of such as galss fiber reinforced resin core.An Exemplary core material is the glass fibre of such as FR4.Alternate material for nuclear material comprises bismaleimide-triazine (BT) resin, or alternatively, comprises other PCB material or films.Laminated film or other laminate of such as ABF can be used for substrate 202.
Substrate 402 can comprise active and passive device (not shown in Fig. 8).It will be appreciated by those skilled in the art that such as transistor, capacitor, resistor, their the various devices of combination etc. can be used for the 26S Proteasome Structure and Function requirement of the design meeting semiconductor package part 400.Any suitable method can be used to form these devices.
Package substrate 402 can also comprise metal layer 404 (not shown) and through hole.Metal layer 404 can be formed in above active and passive device, and is designed to connect each device to form functional circuit.Metal layer 404 can by dielectric layer (such as low k dielectric) and conductive material layer (such as, copper) replace to be formed, wherein through hole is by each conductive material layer, and forms metal layer 404 by any suitable technique (such as deposit, inlay, dual damascene etc.).In certain embodiments, package substrate 402 does not have active and passive device substantially.
Semiconductor package part 400 comprises the bottom filler 406 between semiconductor package part 300 and substrate 402 and between each conducting connecting part 136.Bottom filler 406 can by liquid epoxies, deformability gel, silicon rubber, non-conductive film, polymer, PBO, polyimides, solder resist or they be combined to form.Bottom filler 406 provides support structure for conducting connecting part 136, and capillary force can be used after being bonded between semiconductor package part 300 and substrate 402 by conducting connecting part 136 to distribute bottom filler 406.In these embodiments, bottom filler 406 comprises chamfering, and upwards can extend along semiconductor package part with the sidewall of adjacent first packaging part 100, bottom filler 220 and the second packaging part 200.
By removing dielectric layer from the first packaging part and formed bottom filler before bond package part, the warpage of the first packaging part can be reduced, therefore can improve the coplanarity between the first packaging part and the second packaging part and standing height.In addition, by forming bottom filler before division process, protection conducting connecting part is not by the impact of the fault (short circuit such as, between conducting connecting part) caused by fragment of division process.In addition, for bottom filler provides larger space between semiconductor package part, the problem that the pollution of the bottom filler between two semiconductor package parts and bottom filler overflow between the second adjacent packaging part is prevented by making the second packaging part be less than the first packaging part.
An embodiment is a kind of method, comprises formation first packaging part.Form the first packaging part to comprise: above carrier substrates, form the first dielectric layer; The first electrical connector is formed at the first dielectric layer; By the first die attach for adjacent with the first electrical connector and be positioned at the first dielectric layer; Redistributing layer is formed above the first tube core and described first electrical connector; Above redistributing layer, form the second electrical connector, the second electrical connector is connected at least one in the first tube core and the first electrical connector; Remove carrier substrates to expose the first dielectric layer; And remove the first dielectric layer to expose a part for the first tube core and the first electrical connector.The method also comprises: utilize connected structure that the second packaging part is engaged to the first packaging part, connected structure is connected to the first electrical connector; And bottom filler is formed between the first packaging part and the second packaging part.
Another embodiment is a kind of method, comprising: form the first die package, and the first die package comprises the first tube core, the first electrical connector and the first redistributing layer, and the first redistributing layer is connected to the first tube core and the first electrical connector; Bottom filler is formed above the first die package; Pattern bottom filler is to have the opening of the part exposing the first electrical connector; And utilizing connected structure that the second die package is engaged to the first die package, connected structure is connected to the first electrical connector in the opening of bottom filler.
Another embodiment is a kind of semiconductor package part, comprises the first packaging part.First packaging part comprises: the first tube core; Encapsulant, around the first tube core; And package via, extend through encapsulant.This semiconductor package part also comprises the second packaging part, and comprising the second tube core, the second packaging part is engaged to the first packaging part by one group of connector; And bottom filler, between the first packaging part and the second packaging part and around one group of connector, bottom filler has the sidewall at the back side being basically perpendicular to the first tube core.
The feature discussing multiple embodiment above makes those skilled in the art can understand various aspects of the present invention better.It should be appreciated by those skilled in the art that they can easily based on the disclosure design or amendment for performing the object identical with embodiment described herein and/or realizing other techniques and the structure of same advantage.Those skilled in the art should also be appreciated that these equivalent structures do not deviate from the spirit and scope of the present invention, and can make a variety of changes, replace and change when not deviating from the spirit and scope of the present invention.

Claims (10)

1. a method, comprising:
Form the first packaging part, comprising:
The first dielectric layer is formed above carrier substrates;
The first electrical connector is formed at described first dielectric layer;
By the first die attach for adjacent with described first electrical connector and be positioned at described first dielectric layer;
Redistributing layer is formed above described first tube core and described first electrical connector;
Above described redistributing layer, form the second electrical connector, described second electrical connector is connected at least one in described first tube core and described first electrical connector;
Remove described carrier substrates to expose described first dielectric layer; With
Remove described first dielectric layer to expose a part for described first tube core and described first electrical connector;
Utilize connected structure that the second packaging part is engaged to described first packaging part, described connected structure is connected to described first electrical connector; And
Bottom filler is formed between described first packaging part and described second packaging part.
2. method according to claim 1, wherein, forms described bottom filler and comprises between described first packaging part and described second packaging part:
Utilizing after described first packaging part is engaged to described first packaging part by described connected structure, between described first packaging part and described second packaging part, inject described bottom filler, described bottom filler is around described connected structure.
3. method according to claim 2, wherein, inject described bottom filler between described first packaging part and described second packaging part after, a part for described first tube core is exposed through described bottom filler.
4. method according to claim 1, wherein, forms described bottom filler and comprises between described first packaging part and described second packaging part:
Utilizing before described first packaging part is engaged to described second packaging part by described connected structure, above described first packaging part, form described bottom filler; With
Bottom filler described in patterning, at least to expose a part for described first electrical connector.
5. method according to claim 4, wherein, described in patterning, bottom filler also comprises: bottom filler described in patterning is to expose a part for described first tube core.
6. method according to claim 1, wherein, between described first packaging part and described second packaging part, form described bottom filler to comprise: form liquid epoxies, deformability gel, silicon rubber, non-conductive film, polymer, polybenzoxazole, polyimides, solder resist or their combination.
7. packaging part method according to claim 1, wherein, removes described first dielectric layer and also comprises: etch described first dielectric layer to expose a part for described first tube core and described first electrical connector.
8. a method, comprising:
Form the first die package, described first die package comprises the first tube core, the first electrical connector and the first redistributing layer, and described first redistributing layer is connected to described first tube core and described first electrical connector;
Bottom filler is formed above described first die package;
Bottom filler described in patterning is to have the opening of the part exposing described first electrical connector; And
Utilize connected structure that the second die package is engaged to described first die package, described connected structure is connected to described first electrical connector in the described opening of described bottom filler.
9. method according to claim 8, also comprise: described first die package and described second die package and adjacent die package are separated to form semiconductor package part, described semiconductor package part comprises described first die package and described second die package.
10. a semiconductor package part, comprising:
First packaging part, comprising:
First tube core;
Encapsulant, around described first tube core; With
Package via, extends through described encapsulant;
Second packaging part, comprises the second tube core, and described second packaging part is engaged to described first packaging part by one group of connector; And
Bottom filler, between described first packaging part and described second packaging part and around described one group of connector, described bottom filler has the sidewall at the back side being basically perpendicular to described first tube core.
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US9543170B2 (en) 2017-01-10
TW201608651A (en) 2016-03-01

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