CN105356738B - A kind of start-up circuit for cuk type switch converters - Google Patents

Abstract

A starting circuit for a cuk control circuit is characterized in that it includes a set of counters composed of D flip-flops, a clamping voltage circuit composed of bias current IB1 and voltage dividing resistors R1, R2, R3, R4, and R5, A comparator composed of MOS transistors MP1, MP2, MN1, MN2 and MN3, a comparator composed of MOS transistors MN4, MN5 and MN6 and a level shift circuit. The high four outputs of the counter are respectively connected to the switches of the resistors R1, R2, R3 and R4 in the clamping voltage circuit to generate a step-down clamping voltage Vr, and Vr is connected to the comparator input pair transistors MP2 and MN4 Gate, the gate of another pair of input pair transistors MP1 and MN5 is connected to the reference output voltage VREF, after comparing Vr and VREF through a comparator, the larger value is output by the MN6 transistor. The output signal is connected to the inverting input terminal of the error amplifier through the resistor-capacitor network in the type III compensation network to provide a reference voltage value for the output voltage feedback signal during the startup process, thereby realizing the normal startup of the cuk control circuit.

Description

A kind of starting circuit for cuk type switching converter

technical field

The invention belongs to the field of microelectronics and switching power supply, in particular to a cuk control circuit with single-cycle plus type III compensation, in particular to a starting circuit for a negative-voltage cuk switching power supply.

Background technique

Organic Light Emitting Diode OLED (Organic Light Emitting Diode OLED) has the characteristics of softness, transparency, clear picture quality, energy saving and environmental protection, and is regarded as the most promising next-generation flat-panel display technology. In order to maximize the brightness of light emission, the cathode of the OLED display needs a negative voltage for power supply, so the design of negative voltage chips has become the mainstream trend in this field. The cuk circuit adopts DC chopper technology, which has the characteristics of low output current ripple, which also makes the cuk converter have a wide application prospect in occasions with high requirements on ripple.

Figure 1 shows the cuk control circuit with single-cycle plus type III compensation. The control circuit converts the output negative voltage value into a positive voltage signal and feeds it back to the loop by sampling the divided voltage signal of the output voltage and the power supply voltage. The voltages are compared, and the resulting error amplified signal is compared with the output of the integrator to generate a duty ratio signal to drive the switch to control the output voltage. However, in the start-up phase, the divided signal of the output voltage and the power supply voltage is greater than the reference voltage, and the output of the error amplifier is at a high level. At this time, the output voltage of the integrator is low and cannot intersect with the output voltage of the error amplifier. RS flip-flop The output level of the cuk will not be reversed, so the circuit cannot start normally, so that the cuk circuit enters another stable state. Therefore, a startup circuit needs to be added to enable the cuk control circuit to start normally.

Contents of the invention

The purpose of the present invention is to add the cuk control circuit of type III compensation for existing single cycle in the start-up stage, the divided voltage signal of output voltage and supply voltage is greater than reference voltage, the output of error amplifier is high level, and because of the integrator The output voltage is low and cannot intersect with the output voltage of the error amplifier, so that the output level of the RS flip-flop cannot be reversed, resulting in the problem that the circuit cannot be started normally. Design a control loop that can enable single-cycle control and type III compensation. Start-up circuit for cuk control circuit for normal start-up.

Technical scheme of the present invention is:

A start-up circuit for a cuk control circuit with single-cycle control and type III compensation is characterized in that it includes a set of counters composed of D flip-flops, a clamping voltage circuit, a comparator and a level shift circuit. The high four outputs of the counter are respectively connected to the switches of resistors R1, R2, R3 and R4 in the clamping voltage circuit, thereby generating a step-down clamping voltage Vr, which is connected to the inverting input of the comparator Terminal and one input terminal of the level shift circuit, the non-inverting input terminal of the comparator and the other terminal of the level shift circuit are connected to the reference output voltage VREF, and the larger value of VREF and the clamping voltage Vr is compared by MN6 of the level shift circuit output.

The counter includes 6 D flip-flops Q1, Q2, Q3, Q4, Q5, Q6, the CLK terminal of the D flip-flop Q1 is connected to an externally input clock signal, and the input terminal D is connected to its inverting output terminal Q_ and The CLK terminal of D flip-flop Q2 is similarly connected to Q2, Q3, Q4, and Q5 of D flip-flop. The inverting output terminal of D flip-flop Q5 is connected to the CLK terminal of D flip-flop Q6, and the D input terminal of Q6 Connect its inverting output terminal Q_ terminal.

The clamping voltage circuit includes a bias current source IB1 and voltage dividing resistor strings R1, R2, R3, R4, R5, one end of the bias current source IB1 is connected to the power supply voltage VDD, one end is connected to the resistor R1, and the resistors R1, R2, R3 , R4, R5 are sequentially connected to the ground in series, and the two ends of the resistors R1, R2, R3, and R4 are respectively connected to the control switches S1, S2, S3, and S4, and the connecting end of the resistor R1 and the bias current IB1 generates a clamping voltage Vr.

The clamping voltage Vr is connected to the gates of the input pair of transistors MP2 and MN4, the gate of the other input pair of transistors MP1 and MN5 is connected to the reference output voltage VREF, and the source of the PMOS transistor MP2 is in phase with the source of the PMOS transistor MP1. connected, and connected to one end of the bias current IB2, the other end of the bias current IB2 is connected to the power supply voltage VDD; the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2, the source of MN2 is grounded, the gate of MN2 and The drains are connected, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, and is connected to the gate of the NMOS transistor MN3, the source of MN1 is grounded, and the gate of MN1 is connected to the gate of MN2 , the source of the NMOS transistor MN3 is grounded, and the drain is connected to the reference output voltage VREF; the gates of the NMOS transistor MN4 and the NMOS transistor MN5 are respectively connected to the clamping voltage Vr and the reference output voltage VREF, the drains of MN4 and MN5 are connected, and Connected to the power supply voltage VDD, the sources of MN4 and MN5 are connected, and connected to one end of the bias current IB3, the other end of the bias current IB3 is grounded, the source of the NMOS transistor MN6 is connected to the source of MN4 and MN5, and the gate Connected to the drain and connected to one end of the bias current IB4, the other end of the bias current IB4 is connected to the power supply voltage VDD, and the bias currents IB3 and IB4 satisfy the following relationship:

IB3=2*IB4;

The width-to-length ratios of MN4, MN5 and MN6 are equal, and the gate of MN6 is connected to the VREF1 terminal of the type III compensation network shown in FIG. 1 as the output signal CLAMP_OUT.

The non-inverting output terminals Q of the counters Q3, Q4, Q5 and Q6 are respectively connected to the control switches S1, S2, S3 and S4 of R1, R2, R3 and R4 in the clamping voltage circuit.

The NMOS transistors MN4 and MN5 in the level shift circuit and the bias current IB3 form a common-source output circuit, and its output voltage is boosted by the diode-connected MN6 and then output.

Advantage of the present invention and remarkable effect:

(1) The novel start-up circuit of the present invention does not use a capacitor with a large area, which can effectively reduce the area and cost of the chip.

(2) The novel carrying current compensation circuit of the present invention has a simple structure and better realizes its functions.

Description of drawings

Fig. 1 is the schematic diagram of the CUK type switching converter with single-cycle plus type III compensation.

FIG. 2 is a specific implementation of the startup circuit of the present invention.

Fig. 3 is the current and voltage waveforms of each node of the circuit of the present invention.

Fig. 4 is the current and voltage waveforms of each node of the cuk control circuit after the circuit of the present invention is added.

Detailed ways

The present invention will be further described below in conjunction with drawings and embodiments.

As shown in Figure 1, the single-cycle control plus type III compensation cuk switching converter includes a power stage circuit, single-cycle control plus type III compensation circuit. The power stage includes input inductor L1, output inductor L2, input capacitor C1, output capacitor C2, power transistor MN1, freewheeling diode D1, load resistor Ro and feedback resistor strings R1, R2. One end of the input inductor L1 is connected to the power supply voltage VDD, and the other end is connected to one end of the input capacitor C1 and the drain of the power transistor MN1; the other end of the input capacitor C1 is connected to one end of the output inductor L2 and the positive end of the freewheeling diode D1. The negative end of the diode D1 is grounded; the other end of the output inductor L2 is connected to one end of the output filter capacitor C2 as the output voltage Vo, and the other end of the output capacitor C2 is grounded; one end of the load resistor Ro is connected to the output voltage Vo end, and the other end is grounded. The feedback resistor string includes a first resistor R1 and a second resistor R2, one end of the first resistor is connected to one end of the second resistor, and at the same time, the end of the first resistor generates a feedback signal VFB, and the other end of the first resistor is connected to The input voltage is connected, and the other end of the second resistor is connected to the output terminal Vo of the cuk converter. The control part is composed of integrator, type III compensation network, comparator, RS flip-flop, feedback resistor string and load resistor. The integrator includes a resistor Rz, a capacitor Cz, and an operational amplifier E1. One end of Rz is connected to the inverting end of E1, and the other end is connected to the positive end of the freewheeling diode D1; the capacitor Cz is connected across the inverting end and output end of E1. The switch K is connected in parallel with both ends of the capacitor Cz, wherein the switch K is controlled by the Q_ terminal of the RS flip-flop, and the non-inverting terminal of E1 is grounded. Type III compensation network includes an error amplifier and two resistor-capacitor networks. The resistor-capacitor network composed of C11, C22 and R5 is connected across the inverting terminal and output terminal of the error amplifier. The reference voltage VREF1 is formed by compensating resistors R3, R4 and C33. Another resistor-capacitor network is connected to the inverting terminal of the error amplifier, and the non-inverting terminal of the error amplifier is connected to the feedback signal VFB. The output voltage VEA_OUT of the error amplifier is connected to the inverting terminal of the comparator COMP, and the output voltage VE1_OUT of the integrator is connected to the non-inverting terminal of the comparator COMP, and the output of the comparator COMP is connected to the reset terminal R terminal of the RS flip-flop, and the RS trigger The setting terminal S of the flip-flop is connected to the clock signal, and the output terminal Q of the RS flip-flop is connected to the gate of the power transistor MN1 through the driving circuit to control and generate a duty ratio signal.

Fig. 2 shows the soft-start circuit used for single-cycle control plus type III compensation negative voltage cuk switching converter of the present invention, which includes a group of counters composed of D flip-flops, clamping voltage circuits, comparators and level shifters bit circuit. The high four outputs of the counter are respectively connected to the switches of resistors R1, R2, R3 and R4 in the clamping voltage circuit, thereby generating a step-down clamping voltage Vr, which is connected to the inverting input of the comparator Terminal and one input terminal of the level shift circuit, the non-inverting input terminal of the comparator and the other terminal of the level shift circuit are connected to the reference output voltage VREF, and the larger value of VREF and the clamping voltage Vr is compared by MN6 of the level shift circuit output.

The counter is composed of 6 D flip-flops Q1, Q2, Q3, Q4, Q5, and Q6. The CLK terminal of D flip-flop Q1 is connected to the external input clock signal, and the input terminal D is connected to its inverting output terminal Q_ terminal and D trigger The CLK terminal of the trigger Q2, similarly, the Q2, Q3, Q4, and Q5 of the D flip-flop are also connected sequentially in the same way, the inverting output terminal of the D flip-flop Q5 is connected to the CLK terminal of the D flip-flop Q6, and the D input terminal of Q6 Connect its inverting output terminal Q_ terminal. The non-inverting output terminals Q of D flip-flops Q3, Q4, Q5 and Q6 are respectively connected to the control switches S1, S2, S3 and S4 of R1, R2, R3 and R4 in the clamping voltage circuit;

The clamping voltage circuit includes a bias current source IB1 and a series of voltage dividing resistors R1, R2, R3, R4, R5. One end of the bias current source IB1 is connected to the power supply voltage VDD, and the other end is connected to a resistor R1. The resistors R1, R2, R3, R4, R5 is sequentially connected to the ground in series, and the control switches S1, S2, S3, and S4 are respectively connected across the two ends of the resistors R1, R2, R3, and R4 in sequence, and the connection end of the resistor R1 and the bias current IB1 generates a clamping voltage Vr;

The clamping voltage Vr is connected to the gates of the input pair of transistors MP2 and MN4, the gates of the other input pair of transistors MP1 and MN5 are connected to the reference output voltage VREF, the source of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP1, and Connect to one end of the bias current IB2, the other end of the bias current IB2 is connected to the power supply voltage VDD, the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2, the source of MN2 is grounded, the gate and the drain are connected, The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, and connected to the gate of the NMOS transistor MN3, the source of MN1 is grounded, the gate of MN1 is connected to the gate of MN2, and the gate of the NMOS transistor MN3 The source is grounded, and the drain is connected to the reference output voltage VREF;

The gates of NMOS transistor MN4 and NMOS transistor MN5 are respectively connected to the clamping voltage Vr and the reference output voltage VREF, the drains of MN4 and MN5 are connected to the power supply voltage VDD, the sources of MN4 and MN5 are connected to the bias One end of the current IB3, the other end of the bias current IB3 is grounded, the source of the NMOS transistor MN6 is connected to the source of MN4 and MN5, the gate is connected to the drain, and connected to one end of the bias current IB4, the bias current The other end of IB4 is connected to the power supply voltage VDD, and the bias currents IB3 and IB4 satisfy the following relationship:

IB3=2*IB4;

The width-to-length ratios of MN4, MN5 and MN6 are equal, and the gate of MN6 is connected to the VREF1 terminal of the type III compensation network shown in FIG. 1 as the output signal CLAMP_OUT.

Working process of the present invention is:

As shown in Figure 2, during the start-up phase, the output terminals Q of the counters Q3, Q4, Q5, and Q6 are all set to zero, the switches S1, S2, S3, and S4 are not closed, and the resistors R1, R2, R3, and R4 are sequentially Connected to the ground in series, the output clamping voltage Vr is the largest at this time, which is greater than the reference voltage VREF, and the output VC_OUT of the comparator is at a high level, thereby turning on the MN3 tube and pulling down VREF to clamp it. Since Vr is greater than VREF, the MN4 tube Open, the MN5 tube is closed, and the width-to-length ratios of MN4, MN5, and MN6 are equal, and IB3 is twice that of IB4, so the VGS of MN4 and MN6 are equal, and Vr and CLAMP_OUT are equal;

When the counter counts to a certain value, the switches S1, S2, S3, and S4 are closed sequentially, and the Vr voltage ladder goes downward. When Vr is less than VREF, the output VC_OUT of the comparator is low level, so that the MN3 tube is turned off, and VREF is no longer Pull-down clamp, because Vr is less than VREF, MN4 tube is off, MN5 tube is on, and the width-to-length ratio of MN4, MN5 and MN6 is equal, and IB3 is twice that of IB4, so the VGS of MN5 and MN6 are equal, and VREF and CLAMP_OUT are equal. The current and voltage waveforms of each node of the circuit are shown in Figure 3.

In the initial stage of startup, VREF1 is connected to the Vr signal, Vr is greater than VFB, VEA_OUT outputs a low level, and the output of the integrator VE1_OUT is able to intersect with VEA_OUT to generate a duty cycle signal to control the driver, the output voltage begins to drop, and VFB also begins to drop , VREF1 (that is, Vr) also begins to step down with the counting of the counter, and VEA_OUT begins to rise gradually. When VREF1 is converted to VREF, the circuit can be started normally, and the node current and voltage waveforms are shown in Figure 4.

The features and contents of the present invention have been disclosed above, but those skilled in the art may make various replacements and modifications based on the description of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to the above-mentioned embodiments, but should include various replacements and modifications that do not depart from the present invention, and are covered by the claims.

The parts not involved in the present invention are the same as the prior art or can be realized by adopting the prior art.

Claims (4)

1. a kind of start-up circuit for cuk control circuits, it is characterized in that it includes one group of counter being made of d type flip flop, Clamping voltag circuit, comparator and level shift circuit；High four output of counter is coupled in clamping voltag circuit On the switch of resistance R1, R2, R3, R4, comparator is connected to generate ladder downward clamping voltag Vr, clamping voltag Vr One input terminal of inverting input and level shift circuit, the in-phase input end of comparator and the other end of level shift circuit The higher value of reference output voltage VREF, reference output voltage VREF and clamping voltag Vr are connect by the MN6 ratios of level shift circuit After export；The counter includes 6 d type flip flops, i.e. d type flip flop Q1, d type flip flop Q2, d type flip flop Q3, d type flip flop The CLK of Q4, d type flip flop Q5, d type flip flop Q6, d type flip flop Q1 terminate externally input clock signal, the input terminal of d type flip flop Q1 D terminates the ends its reversed-phase output Q_ and the ends CLK of d type flip flop Q2；The anti-phase output of the CLK termination d type flip flops Q1 of d type flip flop Q2 The ends Q_, the input terminal D of d type flip flop Q2 is held to terminate the ends its reversed-phase output Q_ and the ends CLK of d type flip flop Q3；D type flip flop Q3's CLK terminates the ends reversed-phase output Q_ of d type flip flop Q2, and the input terminal D of d type flip flop Q3 terminates the ends its reversed-phase output Q_ and D is touched Send out the ends CLK of device Q4；The ends reversed-phase output Q_ of the CLK termination d type flip flops Q3 of d type flip flop Q4, the input terminal D of d type flip flop Q4 Terminate the ends its reversed-phase output Q_ and the ends CLK of d type flip flop Q5；The anti-phase output of the CLK termination d type flip flops Q4 of d type flip flop Q5 The ends Q_, the input terminal D of d type flip flop Q5 is held to terminate the ends its reversed-phase output Q_ and the ends CLK of d type flip flop Q6, d type flip flop Q6's is defeated Enter to hold D to connect the ends its reversed-phase output Q_.

2. the start-up circuit according to claim 1 for cuk control circuits, it is characterised in that：The clamping voltag Circuit includes bias current sources IB1 and divider resistance string R1, R2, R3, R4, R5, the termination supply voltages of bias current sources IB1 mono- VDD, a terminating resistor R1, resistance R1, R2, R3, R4, R5 are sequentially connected in series to ground, and the both ends resistance R1, R2, R3, R4 connect respectively Control the connecting pin generation clamping voltag Vr of switch S1, S2, S3, S4, resistance R1 and bias current IB1.

3. the start-up circuit according to claim 1 or 2 for cuk control circuits, it is characterised in that：The clamp electricity Pressure Vr is connected to grid of the input to pipe MP2 and MN4, and another input meets reference output voltage VREF to the grid of pipe MP1 and MN5, The source electrode of PMOS tube MP2 and the source electrode of PMOS tube MP1 connect, and are connected to one end of bias current IB2, and bias current IB2's is another One termination supply voltage VDD；The drain electrode of PMOS tube MP2 is connected to the drain electrode of NMOS tube MN2, the source electrode ground connection of MN2, the grid of MN2 Connecting with drain electrode, the drain electrode of PMOS tube MP1 and the drain electrode of NMOS tube MN1 connect, and connect with the grid of NMOS tube MN3 pipes, The source electrode of MN1 is grounded, and the grid of MN1 and the grid of MN2 connect, and the source electrode ground connection of NMOS tube MN3, drain electrode is connected to benchmark output electricity It presses on VREF；The grid of NMOS tube MN4 and NMOS tube MN5 connect respectively clamping voltag Vr and reference output voltage VREF, MN4 and The drain electrode of MN5 is connected, and the source electrode for being connected to supply voltage VDD, MN4 and MN5 is connected, and is connected to one end of bias current IB3, partially The other end ground connection of electric current IB3 is set, the source electrode of NMOS tube MN6 is connected with MN4 and MN5 and source electrode, and grid and drain electrode connect, and connect To one end of bias current IB4, another termination supply voltage VDD of bias current IB4, bias current IB3 and IB4 meet following Relationship：

IB3=2*IB4；The breadth length ratio of NMOS tube MN4, MN5 and MN6 meet equal, and the grid of NMOS tube MN6 is as output signal CLAMP_OUT is connected to the ends VREF1 of III type compensation network.

4. being used for the start-up circuit of cuk control circuits according to claim 1, it is characterised in that：The level shift electricity NMOS tube in road（MN4, MN5）And bias current IB3 forms common source output circuit, output voltage connects by diode It is exported after the MN6 boostings of method.