CN105355598A - Method for restraining reverse narrow width effect and manufacturing CMOS - Google Patents

Abstract

The invention relates to the technical fields of semiconductor device manufacturing, and in particular to a method for restraining a reverse narrow width effect and manufacturing a CMOS. The method comprises the steps of providing a semiconductor substrate, wherein an STI groove is formed in the semiconductor substrate; active regions are prepared in the two sides of the STI groove in the semiconductor substrate; preparing a first oxide layer to cover the bottom and the side wall of the STI groove; and performing an ion implantation technology on the bottom and the side wall of the STI groove to form a baffle region for isolating doped ions in the active regions from the first oxide layer in the semiconductor layer so as to effectively restrain the reverse narrow width effect, to realize the effective regulation and control on the threshold voltage of small-sized devices, and to improve the stability and the reliability of the small-sized devices; and in addition, according to the method, the relatively low cost, high controllability, and compatibility with the existing CMOS manufacturing technology are realized.

Description

Suppression of anti-narrow channel effect and method of making CMOS

technical field

The invention relates to the technical field of manufacturing semiconductor devices, in particular to a method for suppressing the reverse narrow channel effect and manufacturing CMOS.

Background technique

As the semiconductor process enters the era of Ultra Large Scale Integration (ULSI), the geometric size of transistors on a chip is continuously reduced to approach the physical limit. Smaller devices have increased the integration of chips to meet increasingly complex circuit function requirements. However, as the line width decreases, the sensitivity of transistor electrical parameters to geometric dimensions becomes higher and higher. Some edge effects which are negligible in long-channel devices become the main factors affecting the fluctuation of electrical parameters.

As one of the most important electrical parameters of transistors, threshold voltage (ThresholdVoltage) has been used to characterize its electrical performance. The speed of the circuit, the noise margin all require an accurate prediction of the threshold voltage. Since it is very sensitive to geometrical dimensions, the fluctuation of the threshold voltage of small-sized devices has always been a research focus. Reverse narrow channel effect (Reversenarrowwidtheffect, RNWE) is one of the important directions.

In a shallow trench isolation (Shallow trench isolation, STI) process, RNWE exhibits a rapid drop in threshold voltage as the channel width becomes smaller. This results in increased circuit leakage and increased power consumption.

In order to suppress RNWE, the industry has proposed and verified effective methods, such as:

The shallow trench isolation liner (STIliner) introduces the nitride liner (nitrideliner) to form a double liner (doubleliner) structure, or introduces NOanneal (annealing) after the oxide liner (oxideliner) for nitriding;

Using additional neutral atom implants in the channel, such as Ge;

Introduce B ion implantation at the substrate (Substrate) or STIoxide interface (tilt 0 degrees or 30-40 degrees combined with wafer rotation).

From the perspective of semiconductor manufacturing, the above methods of suppressing NWE are more or less deficient:

STINitrideliner: Severely affects the aspect ratio of STI (aspectratio), resulting in STI vacancy defects (void defect), and because it is a thermal process (thermal process), the cost is too high, and the throughput of the production line (throughput) is too slow;

STIliner introduces NOanneal: it is also a thermal process, the cost is too high, and the throughput of the production line is too slow;

Ge implant (implant): the implantation of large mass elements will lead to increased defects;

Substrate/STIoxide interface introduces Bimplant (tilt 0 degrees or 30-40 degrees combined with wafer rotation): increase the process steps of STI etching (etch), sometimes need to add additional photomask (photomask) process, the cost is high.

Contents of the invention

In view of the above problems, the present invention provides a method for suppressing the anti-narrow channel effect and making CMOS, which can effectively suppress RNWE and improve the stability and reliability of small-sized devices; and the cost is low, the controllability is good, and it can be compared with existing Compatible with CMOS fabrication technology.

The technical solution adopted by the present invention to solve the problems of the technologies described above is:

A method for suppressing the anti-narrow channel effect, comprising:

providing a semiconductor substrate formed with an STI groove, and active regions are prepared on both sides of the STI groove in the semiconductor substrate;

preparing a first oxide layer to cover the bottom and sidewalls of the STI groove;

An ion implantation process is performed on the bottom and sidewalls of the STI trench to form a barrier region in the semiconductor substrate that isolates dopant ions in the active region from the first oxide layer.

Preferably, in the above-mentioned method for suppressing the reverse narrow channel effect, nitrogen ions are used to perform the ion implantation process.

Preferably, in the above-mentioned method for suppressing the reverse narrow channel effect, the energy range of the nitrogen ion implantation is 4-15 keV.

Preferably, in the above-mentioned method for suppressing the reverse narrow channel effect, the nitrogen ion implantation concentration ranges from 10 ¹⁴ to 10 ¹⁶ /cm ^-2 .

Preferably, the above-mentioned method for suppressing the reverse narrow channel effect, wherein, the inclination angle between the nitrogen ion implantation and the vertical direction of the semiconductor substrate is 0-45 degrees.

Preferably, the above method for suppressing the reverse narrow channel effect, wherein, when the inclination angle is greater than 0 degrees, the nitrogen ion implantation is performed in combination with the rotation of the semiconductor substrate.

The present invention also provides a kind of method of making CMOS, it is characterized in that, comprises the following steps:

Step 1, providing a semiconductor substrate provided with several active regions, after depositing a pad oxide layer on the semiconductor substrate, depositing a pad nitride layer on the pad oxide layer;

Step 2, apply photoresist to the active regions to form a photomask, and engrave the circuit pattern on the photomask into the active regions;

Step 3, dry etching to form an STI groove between every two active regions, and then performing wet cleaning to remove the photoresist;

Step 4, using hot phosphoric acid etching to remove the pad nitride layer above the sharp corner of the STI groove;

Step 5, preparing and generating a first oxide layer on the bottom and side walls of the STI groove;

Step 6, performing nitrogen ion implantation on the bottom and side walls of the STI trench.

Preferably, in the above-mentioned method for manufacturing CMOS, in the fifth step, the first oxide layer is prepared by using an in-situ water gas generation process.

Preferably, the above-mentioned method for manufacturing CMOS, wherein, in the sixth step, the pad nitride layer that has not been etched on the pad oxide layer in the step 4 is used as a mask to mask the bottom of the STI groove and The nitrogen ion implantation is performed on the sidewall.

Preferably, in the above-mentioned method for manufacturing CMOS, in the sixth step, the energy range of the nitrogen ion implantation is 4-15 keV; the concentration range is 10 ¹⁴ -10 ¹⁶ /cm ^-2 .

Preferably, the above-mentioned method for manufacturing CMOS, wherein, in the sixth step, the inclination angle between the nitrogen ion implantation and the vertical direction of the semiconductor substrate is 0-45 degrees; and when the inclination angle is greater than 0 degrees, The nitrogen ion implantation is performed in conjunction with the rotation of the semiconductor substrate.

Preferably, the above-mentioned method for making CMOS also includes the following subsequent steps:

High-density plasma filling and chemical mechanical polishing in shallow trench isolation regions, well formation and passivation in active regions.

The above technical solution has the following advantages or beneficial effects: a method for suppressing the reverse narrow channel effect and manufacturing CMOS provided by the present invention effectively suppresses the reverse narrow channel effect (Reversenarrowwidth effect, RNWE) by ion (N ion) implantation, and realizes The effective control of the threshold voltage of the small-sized device improves the stability and reliability of the small-sized device; and the cost is low, the controllability is good, and it is compatible with the existing CMOS manufacturing technology.

Description of drawings

The invention and its characteristics, configurations and advantages will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. Like numbers designate like parts throughout the drawings. The drawings may not be drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

Fig. 1 is a step diagram of the method for suppressing the reverse narrow channel effect of the present invention;

Fig. 2 is the step figure of the method for making CMOS of the present invention;

3 to 8b are schematic diagrams of the stages of the method for fabricating CMOS according to the present invention.

detailed description

The method for suppressing the reverse narrow channel effect and the method for manufacturing CMOS of the present invention will be described in detail below in conjunction with specific embodiments.

Embodiment one:

As shown in Figure 1, the method for suppressing the reverse narrow channel effect of the present invention mainly includes: providing a semiconductor substrate formed with an STI groove, and active regions are prepared on both sides of the STI groove in the semiconductor substrate ; prepare the first oxide layer to cover the bottom and sidewall of the STI groove; carry out an ion implantation process to the bottom and sidewall of the STI groove to form a mixture of doping ions in the active region and the first oxide layer in the semiconductor substrate Barrier area for isolation.

As a preferred embodiment, nitrogen ions are used in this embodiment to perform the above ion implantation process, and the energy range of nitrogen ion implantation is 4-15 keV; the concentration range is 10 ¹⁴ -10 ¹⁶ /cm ^-2 ; The inclination angle in the vertical direction of the substrate is 0-45 degrees; and when the inclination angle is greater than 0 degrees, nitrogen ion implantation needs to be performed in combination with the rotation of the semiconductor substrate.

Specifically, as shown in FIGS. 8a and 8b, FIG. 8a is a schematic diagram of the bottom and sidewalls of the STI groove implanted (that is, N ions are vertically implanted) with an inclination angle of 0 degrees between N ions and the vertical direction of the semiconductor substrate 10; FIG. 8b is a schematic diagram of the bottom and sidewall of the STI trench where N ions are implanted at an angle greater than 0 degrees from the vertical direction of the semiconductor substrate 10 (that is, N ions are implanted at a certain angle to the vertical direction, and the angle is less than 45 degrees).

The principle of the present invention to suppress the anti-narrow channel effect is to introduce N element into the interface between the sharp angle (STIcorner) of the STI groove and the silicon substrate (Sisubstrate) or the oxide layer (STIoxide) of the STI groove by means of ion implantation, so as to suppress the narrow channel effect. The channel dopant impurity (such as B) diffuses into the STIoxide, thereby improving the stability of the threshold voltage.

Embodiment two:

As shown in Figure 2, the main steps of making CMOS in this embodiment include:

Step 1, pre-active area lithography (pre-AAphoto): as shown in Figure 3, a semiconductor substrate 10 (specifically a silicon substrate in this embodiment) provided with several active areas (not marked in the figure) is provided 10) After depositing a pad oxide layer (padoxide) 11 on the silicon substrate 10, and then depositing a pad nitride layer (padNitride) 12 on the pad oxide layer 11.

Step 2, active area photolithography (AAphoto): as shown in Figure 4, apply photoresist (PR) 13 to several active areas on the silicon substrate 10 to form a photomask, and the circuit pattern on the photomask Engraving to the active area; the function of the photoresist 13 is to protect the active area (that is, the active area) from being etched when the STI groove is formed by subsequent etching.

Step 3, active area etching and photoresist removal (AAetch&PRstrip): as shown in Figure 5, dry etching (dryetch) to form STI groove 14 between every two active areas (Figure 5 is clearly shown , only two active regions and an STI groove 14 formed between them are marked. In actual production, several active regions can be set on the silicon substrate, and an STI is formed between every two active regions. groove), followed by wet cleaning to remove the photoresist 13 covering the active area.

Step 4, pad nitride layer removal (Padnitride pullback): as shown in FIG. 6 , use hot phosphoric acid (H ₃ PO ₄ ) to etch to remove the pad nitride layer 12 above the corner of the STI groove 14 (ie, as shown in FIG. The pad nitride layer 12 indicated by the dotted box in 6 is removed).

Step 5, STI liner oxide deposition (STI liner oxide deposition): generation As shown in FIG. 7 , a liner oxide (liner oxide) 15 is formed on the bottom and sidewalls of the STI slot 14 by using an in-situ water gas generation process (ISSG).

Step 6, nitrogen ion implantation (Nitrogenimplant): Nitrogen ion implantation is performed on the bottom and side walls (including sharp corners) of the STI trench 14 .

As a preferred embodiment, the energy range of nitrogen ion implantation in step 6 is 4-15 keV; the concentration range is 10 ¹⁴ -10 ¹⁶ /cm ^-2 . Moreover, as shown in FIG. 8a, N ions (the arrows in FIG. 8a represent implanted N ions) can be implanted into the STI groove at a vertical angle to the silicon substrate 10 (that is, the angle between the vertical direction to the silicon substrate 10 is 0 degrees). 14 bottom and sidewalls (including sharp corners); or as shown in Figure 8b, N ions (arrows in Figure 8b represent implanted N ions) can form a certain angle with the vertical direction of the silicon substrate 10 (the angle less than 45 degrees) obliquely injected into the bottom and sidewalls of the STI groove 14 (also including sharp corners). It should be noted that in actual production, the inclination angle during N ion implantation can be adjusted according to process requirements, as long as the angle between the inclination angle and the vertical direction of the silicon substrate 10 is greater than 0 degrees and less than 45 degrees. When the angle is greater than 0 degrees, nitrogen ion implantation needs to be performed in combination with the rotation of the silicon substrate 10 .

As a preferred embodiment, in step six, the nitrogen ion implantation is performed using the pad nitride layer 12 that has not been etched in step four as a mask.

After the nitrogen ion implantation is completed, the method for manufacturing CMOS in this embodiment also includes subsequent steps: shallow trench isolation region high-density plasma filling (STIHDPfill) and chemical mechanical polishing (CMP), active region well formation (wellformation) and passivation treatment (passivation). Since these subsequent steps are consistent with the current CMOS manufacturing process, this embodiment will not repeat them here.

In summary, the present invention provides a method for suppressing the reverse narrow channel effect and manufacturing CMOS, effectively suppressing the reverse narrow channel effect (Reversenarrowwidth effect, RNWE) by ion (N ion) implantation, and realizing the threshold value of small-sized devices The effective regulation of the voltage improves the stability and reliability of small-sized devices; and the cost is low, the controllability is good, and it can be compatible with the existing CMOS manufacturing technology.

Those skilled in the art should understand that those skilled in the art can implement the variation example by combining the existing technology and the foregoing embodiments, and details are not described here. Such variations do not affect the essence of the present invention, and will not be repeated here.

The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and the devices and structures that are not described in detail should be understood to be implemented in a common manner in the art; Under the circumstances of the technical solution of the invention, many possible changes and modifications can be made to the technical solution of the present invention by using the methods and technical contents disclosed above, or be modified into equivalent embodiments with equivalent changes, which does not affect the essence of the present invention . Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (12)

1. suppress a method for reversed narrow-path effect, it is characterized in that, comprising:

There is provided the Semiconductor substrate that is formed with STI groove, and the both sides being positioned at described STI groove in described Semiconductor substrate are all prepared and are had active area;

Prepare bottom and sidewall that the first oxide layer covers described STI groove;

Ion implantation technology is carried out, to form the baffle area Doped ions in described active area and described first oxide layer being carried out isolating in described Semiconductor substrate to the bottom of described STI groove and sidewall.

2. the method for claim 1, is characterized in that, adopts Nitrogen ion to carry out described ion implantation technology.

3. method as claimed in claim 2, it is characterized in that, the energy range of described N~+ implantation is 4 ~ 15keV.

4. method as claimed in claim 2, it is characterized in that, the concentration range of described N~+ implantation is 10 ¹⁴~ 10 ¹⁶/ cm ^-2.

5. method as claimed in claim 2, it is characterized in that, the angle of inclination of described N~+ implantation and described Semiconductor substrate vertical direction is 0 ~ 45 degree.

6. method as claimed in claim 5, it is characterized in that, when described angle of inclination is greater than 0 degree, described N~+ implantation is carried out in the rotation in conjunction with described Semiconductor substrate.

7. make a method of CMOS, it is characterized in that, comprise the following steps:

Step one, provides the Semiconductor substrate that is provided with some active areas, deposit pad oxide on described Semiconductor substrate after, and deposition pad nitration case on described pad oxide;

Step 2, coating photoresist forms light shield to described some active areas, and the circuit pattern on described light shield is scribed described active area;

Step 3, dry etching, to form STI groove between every two described active areas, carries out wet-cleaned afterwards to remove described photoresist;

Step 4, use hot phosphoric acid etch remove described STI groove wedge angle on pad nitration case;

Step 5, prepares generation first oxide layer in the bottom of described STI groove and sidewall;

Step 6, carries out N~+ implantation to the bottom of described STI groove and sidewall.

8. method as claimed in claim 7, is characterized in that, in described step 5, utilize on-the-spot aqueous vapor generating process to prepare described first oxide layer.

9. method as claimed in claim 7, is characterized in that, in described step 6, adopts the described pad nitration case that pad oxide described in step 4 is not etched as mask, carries out described N~+ implantation to the bottom of described STI groove and sidewall.

10. method as claimed in claim 7, it is characterized in that, in described step 6, the energy range of described N~+ implantation is 4 ~ 15keV; Concentration range is 10 ¹⁴~ 10 ¹⁶/ cm ^-2.

11. methods as claimed in claim 7, is characterized in that, in described step 6, the angle of inclination of described N~+ implantation and described Semiconductor substrate vertical direction is 0 ~ 45 degree; And when described angle of inclination is greater than 0 degree, described N~+ implantation is carried out in the rotation in conjunction with described Semiconductor substrate.

12. methods as claimed in claim 7, is characterized in that, the described method making CMOS also comprises following subsequent step:

Shallow channel isolation area high-density plasma is filled and chemico-mechanical polishing, and active area trap is formed and Passivation Treatment.