CN105355596A - Method for manufacturing CMOS device - Google Patents

Abstract

The invention relates to the field of semiconductors, and provides a method for manufacturing a CMOS device, comprising: growing a first grid oxide layer on a substrate surface. Coating photoresist on the surface of the first gate oxide layer of the high voltage device part and performing photoetching. The first gate oxide layer is etched to etch away the first gate oxide layer of the low-voltage device part. A second gate oxide layer is grown on the surface of the substrate, and the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer. Coating photoresist on the surface of the first gate oxide layer of the high voltage device part and performing photoetching. A threshold implant is performed on the substrate. Polysilicon is grown on the first gate oxide layer and the second gate oxide layer. This method can not only perform threshold implantation to adjust the threshold voltage of low-voltage devices, but also prevent ions from entering high-voltage devices, thereby reducing the threshold voltage of high-voltage devices when manufacturing CMOS devices with both low-voltage devices and high-voltage devices.

Description

A kind of CMOS device manufacturing method

technical field

The invention relates to the field of semiconductors, in particular to a method for manufacturing a CMOS (Complementary Metal Oxide Semiconductor) device.

Background technique

The CMOS devices produced by the traditional CMOS device manufacturing process can only meet the power requirements of 5V, but with the development of technology, high-voltage devices that can be applied to high voltages have been produced. When a high-voltage device is used as a start-up tube or drive circuit, its threshold voltage is much higher than that of ordinary CMOS, and a voltage lower than this threshold voltage cannot drive a high-voltage device to work, and the risk of increasing the voltage lies in the breakdown of the gate, causing the device damage. Therefore, when manufacturing a CMOS device with a high voltage device, it is necessary to make the threshold voltage of the high voltage device as small as possible.

As shown in Figure 1, one of the CMOS devices with high-voltage devices has both low-voltage devices and high-voltage devices. The oxide layer on the surface of this device includes a field oxide layer (abbreviated as field oxide) and a gate oxide layer. Low-voltage devices include PMOS (PositiveChannelMetalOxideSemiconductorP-channel metal-oxide-semiconductor) devices and NMOS (NegativeChannelMetalOxideSemiconductorN-channel metal-oxide-semiconductor) devices. Since the threshold voltages of PMOS devices and NMOS devices are asymmetrical, it is necessary to inject such as Ions of boron ions perform threshold voltage regulation of low-voltage devices. However, when the threshold implantation is performed in the traditional process, ions will be implanted into the high-voltage device, and the threshold of the high-voltage device will become larger, contrary to the purpose of reducing the threshold voltage of the high-voltage device.

Therefore, there is a need for a method that, when manufacturing CMOS devices with both low-voltage devices and high-voltage devices, can perform threshold implantation to adjust the threshold voltage of low-voltage devices, and prevent ions from entering high-voltage devices, thereby reducing the threshold voltage of high-voltage devices. .

Contents of the invention

The embodiment of the present invention provides a method for manufacturing a CMOS device, which can be applied to manufacture a CMOS device having both a low-voltage device and a high-voltage device, so as to adjust the threshold voltage of the low-voltage device and reduce the threshold voltage of the high-voltage device.

In order to achieve the above object, an embodiment of the present invention provides a method for manufacturing a CMOS device including a high-voltage device part and a low-voltage device part, including the following steps:

A first gate oxide layer is grown on the surface of the substrate. Coating photoresist on the surface of the first gate oxide layer of the high-voltage device part, and performing photoetching on the first gate oxide layer. The first gate oxide layer is etched to etch away the first gate oxide layer of the low-voltage device part. A second gate oxide layer is grown on the surface of the substrate, and the thickness of the second gate oxide layer is smaller than that of the first gate oxide layer. Coating photoresist on the surface of the first gate oxide layer of the high-voltage device part, and performing photoetching on the first gate oxide layer. A threshold implant is performed on the substrate. Polysilicon is grown on the first gate oxide layer and the second gate oxide layer.

The CMOS device manufacturing method using the above steps can reduce the threshold voltage of the high-voltage device while adjusting the threshold voltage of the low-voltage device when manufacturing a CMOS device having both a low-voltage device and a high-voltage device.

Preferably, after etching the first gate oxide layer, removing the photoresist is also included.

After etching the first gate oxide layer and removing the photoresist, the second gate oxide layer can be grown more smoothly.

Preferably, removing the photoresist is also included after performing the substrate threshold implantation.

Removing the photoresist after the threshold implant enables smoother polysilicon growth.

Preferably, the first gate oxide layer is etched using a wet etching technique.

Since there is no high requirement on the thickness of the first gate oxide layer after etching in the above solution, a wider wet etching technique is used for etching with lower precision but higher selectivity.

An embodiment of the present invention provides another manufacturing method of a CMOS device including a high-voltage device part and a low-voltage device part based on the same idea, including the following steps: growing a first gate oxide layer on the surface of the substrate. Coating photoresist on the first gate oxide layer of the high-voltage device part, and performing photoetching on the first gate oxide layer. Etching the first gate oxide layer to etch the first gate oxide layer of the low-voltage device part into a second gate oxide layer with a first thickness, the first thickness being smaller than the first gate oxide layer layer thickness. A threshold implant is performed on the substrate. Polysilicon is grown on the first gate oxide layer and the second gate oxide layer.

Compared with the method provided by the previous embodiment of the present invention, the above method can better control the thickness of the first gate oxide layer of the high-voltage device part because it does not need to grow the second gate oxide layer, and also saves raw materials .

Preferably, after threshold implantation is performed on the substrate, the photoresist is removed.

Removing the photoresist after the threshold implant enables smoother polysilicon growth.

Preferably, the first gate oxide layer is etched using an ion milling etching technique.

Since the thickness of the gate oxide layer of the etched low-voltage device is required in this manufacturing method, the ion milling etching technique with higher precision is selected to etch the first gate oxide layer.

The CMOS device manufacturing method provided by the embodiment of the present invention uses the photoetched photoresist to mask the high-voltage device part when performing threshold injection, and realizes the low-voltage device when manufacturing a CMOS device with both low-voltage devices and high-voltage devices. While performing threshold voltage adjustment, the threshold voltage of the high voltage device is reduced.

Description of drawings

FIG. 1 is a schematic diagram of a CMOS device having both a low voltage device and a high voltage device.

FIG. 2 is a flow chart of a method for manufacturing a CMOS device provided by an embodiment of the present invention.

3a-3h are schematic diagrams of processing the CMOS device in each step of the manufacturing method of the CMOS device in FIG. 2 .

FIG. 4 is a flow chart of another CMOS device manufacturing method provided by an embodiment of the present invention.

5a-5f are schematic diagrams of processing the CMOS device in each step of the manufacturing method of the CMOS device in FIG. 4 .

detailed description

As shown in Fig. 2 and Fig. 3a-Fig. 3h, the flow chart of a CMOS device manufacturing method provided by the embodiment of the present invention mainly includes the following main steps:

S201, as shown in FIG. 3a, grow a first gate oxide layer on the surface of the substrate. In this embodiment, the substrate is a P-type substrate (P-Sub), and the thickness of the first gate oxide layer is And the first gate oxide layer is formed by thermally oxidizing the surface of the substrate.

S202 , as shown in FIG. 3 b , after coating a photoresist on the surface of the first gate oxide layer of the high-voltage device part, perform photoetching on the first gate oxide layer.

S203, as shown in FIG. 3c, etch the first gate oxide layer to completely etch away the first gate oxide layer of the low-voltage device part, while the first gate oxide layer of the high-voltage device part is due to the photoresist can be fully preserved. After etching the first gate oxide layer, preferably, the photoresist is removed. Regarding the removal of the photoresist, a stripping method or other methods may be used. As for the choice of etching method, preferably wet etching can be selected, because this etching does not require high etching precision, so a more selective and wider wet etching method can be used for etching. eclipse.

S204 , as shown in FIG. 3 d , grow a second gate oxide layer on the surface of the substrate, and the thickness of the second gate oxide layer is smaller than the thickness of the first gate oxide layer. Since the first gate oxide layer of the low voltage device part has been etched away, the surface of the low voltage device part only has the second gate oxide layer. In this embodiment, the thickness of the second gate oxide layer is Since prior to this, a thickness of Therefore, the thickness of the second gate oxide layer formed on the surface of the high-voltage device by the second thermal oxidation is extremely small. Therefore, in this embodiment, the surface of the high-voltage device after the second gate oxide layer is still grown The gate oxide layer is called the first gate oxide layer. In addition, in this embodiment, the second gate oxide layer is formed by thermally oxidizing the surface of the substrate.

S205. As shown in FIG. 3e, apply photoresist on the surface of the first gate oxide layer of the high-voltage device part, and perform photolithography on the first gate oxide layer. In this photolithography, the photoresist only covers the high-voltage device surface of the first gate oxide layer.

S206 , as shown in FIG. 3f , perform threshold implantation on the substrate, and implant boron ions with an energy of 25 keV and a dose of 9E11 atoms/cm2. Since the high-voltage device is covered by a photoresist that has undergone photolithography, boron ions cannot pass through the photoresist and enter the high-voltage device. Therefore, at this time, because boron ions cannot enter the interior of the high-voltage device, the threshold voltage of the high-voltage device will not rise, while the threshold voltage of the low-voltage device is adjusted because the low-voltage device has been implanted with boron ions.

S207, as shown in FIG. 3g, removing the photoresist. The photoresist can be removed by stripping or by other methods.

S208 , as shown in FIG. 3 h , growing polysilicon on the first gate oxide layer and the second gate oxide layer to form a polysilicon layer.

As shown in FIG. 4 and FIG. 5a-FIG. 5f, the embodiment of the present invention provides a flow chart of another CMOS device manufacturing method, which mainly includes the following main steps:

S401, as shown in FIG. 5a, grow a first gate oxide layer on the surface of the substrate. In this embodiment, the substrate is a P-type substrate (P-Sub), and the thickness of the first gate oxide layer is And it grows on the substrate surface by thermal oxidation.

S402 , as shown in FIG. 5 b , coating a photoresist on the first gate oxide layer of the high-voltage device part, and performing photoetching on the first gate oxide layer.

S403, as shown in FIG. 5c, etching the first gate oxide layer. When performing etching, always pay attention to the thickness of the gate oxide layer, and etch the first gate oxide layer of the low-voltage device part to the second gate oxide layer whose thickness is smaller than the thickness of the first gate oxide layer. In this embodiment The thickness of the second gate oxide layer is

Since the low-voltage device part is not completely etched away, and then the second thermal oxidation is performed, at this time, the gate oxide layer of the high-voltage device part will no longer grow, so this method is conducive to controlling the gate of the high-voltage device part. The thickness of the extreme oxide layer is reduced, and raw materials are also saved at the same time.

At the same time, in this embodiment, the ion milling method is used for etching. Since there are specific requirements for the thickness of the first gate oxide layer of the low-voltage device after etching, the ion milling method with high etching accuracy is used. method for etching.

S404, as shown in FIG. 5d, perform threshold implantation, implant boron ions with an energy of 25 keV, and a dose of 9E11 atoms/cm2. Since the exposed photoresist covers the high voltage device at this time, boron ions cannot pass through the photoresist and enter the high voltage device. Therefore, at this time, because boron ions cannot enter the interior of the high-voltage device, the threshold voltage of the high-voltage device will not rise, while the threshold voltage of the low-voltage device is adjusted because the low-voltage device has been implanted with boron ions.

S405, as shown in FIG. 5e, removing the photoresist. The photoresist can be removed by stripping or by other methods.

S406, as shown in FIG. 5f, growing polysilicon on the first gate oxide layer and the second gate oxide layer to form a polysilicon layer.

In this embodiment, since the second growth of the gate oxide layer is not performed, raw materials are saved, and it is also beneficial to control the thickness of the gate oxide layer of the high-voltage device part.

The CMOS device manufacturing method provided by the embodiment of the present invention shields the high-voltage device part during threshold injection, and realizes adjusting the threshold voltage of the low-voltage device on the CMOS device with both low-voltage devices and high-voltage devices, while reducing the high voltage. device threshold voltage.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (7)

1. a complementary metal oxide semiconductors (CMOS) cmos device manufacture method, described cmos device comprises high tension apparatus part and low-voltage device part, it is characterized in that, comprising:

The first grid oxic horizon is grown at substrate surface;

At the first grid oxide layer surface-coated photoresist of high tension apparatus part, and photoetching is carried out to described first grid oxide layer;

Described first grid oxide layer is etched, to etch away the first grid oxide layer of low-voltage device part;

Grow the second grid oxic horizon at described substrate surface, the thickness of described second grid oxide layer is less than the thickness of described first grid oxide layer;

At the first grid oxide layer surface-coated photoresist of high tension apparatus part, and photoetching is carried out to described first grid oxide layer;

Threshold value injection is carried out to described substrate;

Growing polycrystalline silicon in described first grid oxide layer and second grid oxide layer.

2. the method for claim 1, is characterized in that, after etching, also comprises: remove described photoresist described first grid oxide layer.

3. the method for claim 1, is characterized in that, after injecting, also comprises: remove described photoresist described substrate threshold value.

4. the method for claim 1, is characterized in that, carries out etching comprise described first grid oxide layer: use wet etching technique to etch described first grid oxide layer.

5. a complementary metal oxide semiconductors (CMOS) cmos device manufacture method, described cmos device comprises high tension apparatus part and low-voltage device part, it is characterized in that, comprising:

The first grid oxic horizon is grown at substrate surface;

The first grid oxide layer of high tension apparatus part applies photoresist, and photoetching is carried out to described first grid oxide layer;

Described first grid oxide layer is etched, with by the first grid oxide layer of low-voltage device part etching for thickness is the second grid oxide layer of the first thickness, described first thickness is less than the thickness of first grid oxide layer;

Threshold value injection is carried out to described substrate;

Growing polycrystalline silicon in described first grid oxide layer and second grid oxide layer.

6. method as claimed in claim 5, is characterized in that, after carrying out threshold value injection, also comprise: remove described photoresist to described substrate.

7. method as claimed in claim 5, is characterized in that, carry out etching comprise described first grid oxide layer: use ion beam milling lithographic technique to etch described first grid oxide layer.