CN105355559A - Method for preparing semiconductor device - Google Patents

Abstract

The invention relates to the field of semiconductor device optimization, in particular to a method for preparing a semiconductor device. By depositing the non-epitaxial growth layer twice, and etching part of the first non-epitaxial growth layer and the oxide layer, the second non-epitaxial growth layer is exposed, and then sequentially depositing a high dielectric layer on the outer surface of the exposed second non-epitaxial growth layer. The electrical constant layer and the metal layer form the gate, which forms a fully surrounded metal gate structure, which effectively suppresses the problems of short channel effect, leakage field and punch-through in the FinFET structure, and improves the performance of the device. .

Description

A method of preparing a semiconductor device

technical field

The invention relates to the field of semiconductor device optimization, in particular to a method for preparing a semiconductor device.

Background technique

With the development of integrated circuits, the device size is getting smaller and smaller, and the integration level is getting higher and higher. With the continuous reduction of the feature size of semiconductor devices, the traditional planar semiconductor manufacturing technology can no longer be used, and non-planar semiconductor devices have emerged. For example, the application of new technologies such as silicon-on-insulator, double gate, and multi-gate. At present, fin field effect transistors are widely used in the field of small size, and semiconductor devices with a gate-all-around structure have special performance in device performance and can effectively suppress short channel effects. It is exactly what the semiconductor industry is pursuing. Since the device channel is surrounded by the gate, the influence of the leakage field of the device is also eliminated, effectively suppressing the leakage and punch-through problems of the device. Since the fully surrounded gate is suspended from the bottom substrate, the manufacturing process of the fully surrounded gate device is relatively complicated.

Therefore, there is an urgent need for a new method for forming a fully-enclosed gate.

Contents of the invention

In view of the above-mentioned problems, the present invention discloses a method for preparing a semiconductor device, and its specific technical solution is:

A method for preparing a semiconductor device, comprising:

A semiconductor device is provided, the semiconductor device includes a base layer and an oxide layer located on the upper surface of the base layer;

Depositing a patterned mask layer on the upper surface of the oxide layer, and using the mask layer as a mask to etch the oxide layer to the upper surface of the base layer to form a trench;

removing the mask layer, and performing a first non-doped epitaxial growth in the trench to form a first non-doped epitaxial growth layer;

performing a second non-doped epitaxial growth in the trench to form a second non-doped epitaxial growth layer, and the upper surface of the second non-doped epitaxial growth layer and the upper surface of the oxide layer are in the same plane;

Etching part of the oxide layer to expose the second non-doped epitaxial growth layer and part of the first non-doped epitaxial growth layer;

The exposed first non-doped epitaxial growth layer is removed, and a high dielectric constant layer and a metal material layer are sequentially grown outside the second non-doped epitaxial growth layer to form a metal gate.

The above method is characterized in that the base layer is made of single crystal silicon.

The above-mentioned method is characterized in that the method also includes:

The oxide layer is deposited by chemical vapor deposition.

The above method is characterized in that the material of the oxide layer is silicon oxide.

The above method is characterized in that the oxide layer is etched to the upper surface of the base layer by dry method.

The above-mentioned method is characterized in that the method also includes:

forming an oxide layer outside the second non-doped epitaxial growth layer by using an in-situ water vapor generation process;

Polysilicon is deposited on the surface of the oxide layer to form a polysilicon gate.

The above method is characterized in that the first non-doped epitaxial growth layer is formed using a germanium doping process.

The above method is characterized in that wet etching is used to remove part of the first non-doped epitaxial growth layer.

The above method is characterized in that SiCoNi is used to etch part of the oxide layer.

The above technical solution has the following advantages or beneficial effects:

A method for preparing a semiconductor device designed by the present application, by depositing the non-epitaxial growth layer twice, and etching part of the first non-epitaxial growth layer and the oxide layer, exposing the second non-epitaxial growth layer, and then The outer surface of the second non-epitaxial growth layer deposits a high dielectric constant layer and a metal layer in sequence to form a gate, thus forming a fully surrounded metal gate structure, which effectively suppresses the short channel effect in the FinFET structure. , Leakage field and punch-through problems, improve device performance.

Description of drawings

The invention and its characteristics, configurations and advantages will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings. Like numbers designate like parts throughout the drawings. The drawings may not be drawn to scale, emphasis instead being placed upon illustrating the gist of the invention.

Figure 1 is a schematic diagram of the application process;

Fig. 2-Fig. 7 are schematic diagrams of the structure of the present application.

detailed description

The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

The present invention has designed a kind of method for preparing semiconductor device, and this method specifically includes the following steps:

A semiconductor substrate is provided, and an oxide layer and a patterned mask layer are sequentially covered on the substrate;

Etching the oxide layer to form grooves;

Perform the first non-doped epitaxial growth on the exposed semiconductor substrate surface;

Carry out the second non-doped epitaxial growth;

partially removing the oxide layer to expose the non-doped fin structure;

Etching the non-doped semiconductor substrate to form a channel structure suspended above the substrate;

A layer of high dielectric constant material and a layer of metal material are sequentially deposited on the periphery of the channel to form a finned metal gate structure.

The following will be described in conjunction with specific embodiments

Embodiment one

As shown in Figures 1 to 7, the present invention designs a method for preparing a metal gate fin-shaped semiconductor device, which specifically includes:

Provide a semiconductor device, the semiconductor device includes a base layer 1 and an oxide layer 2, the oxide layer 2 is located on the upper surface of the base layer 1, according to the specific operation requirements of the application, the material of the base layer 1 is polysilicon, namely A polysilicon substrate. The oxide layer 2 is made of silicon oxide, specifically, a silicon oxide layer is deposited on a silicon substrate by chemical vapor deposition;

After the silicon oxide layer 2 is deposited on the silicon substrate, a mask layer 3 is deposited on the upper surface of the silicon oxide layer, and then a pattern is opened on the mask layer 3, and the remaining mask layer 3 is used as a mask Etching the silicon oxide layer, specifically etching the silicon oxide layer by dry method, etch to the upper surface of the silicon substrate, and then stopping the etching, thus forming a groove 4;

The remaining mask layer is removed to expose the silicon oxide layer and the trench 4 , and then a first non-doped epitaxial growth is performed in the trench 4 to form a first non-doped epitaxial growth layer 5 . In this application, the first non-doped epitaxial growth layer 5 is formed by doping the grooves with germanium doping technology, or the first non-doped epitaxial growth layer 5 is formed by doping the grooves with carbon doping technology. 5. Such two doping processes can be used for doping epitaxy in this application;

The first non-doped epitaxial growth only forms part of the trench, that is to say, it does not completely fill the entire trench 4. According to specific process requirements and design schemes, the thickness of the deposited first non-doped epitaxial growth layer can be increased. Appropriate adjustments. After the first non-doped epitaxial growth layer 5 is deposited, a second non-doped epitaxial growth is performed on the upper surface of the first non-doped epitaxial growth layer 5 in the trench, and the second non-doped epitaxial growth is formed after the second non-doped epitaxial growth The second non-doped epitaxial growth layer 6 . Specifically, the upper surface of the second non-doped epitaxial growth layer 6 and the upper surface of the silicon oxide layer are on the same plane, that is, the upper surface of the second non-doped epitaxial growth layer is flush with the upper surface of the silicon oxide layer. Of course, if the upper surface of the second non-doped epitaxial growth layer 6 formed by the second non-doped epitaxial growth exceeds the upper surface of the silicon oxide layer, the excess part can be polished so that the remaining second non-doped epitaxial growth layer 6 The upper surface of the hetero-epitaxial growth layer 6 is flush with the upper surface of the silicon oxide layer;

After the second non-doped epitaxial growth layer 6 is formed, part of the silicon oxide layer is removed. Specifically, a part of the silicon oxide layer can be removed by dry etching, or it can be removed by wet etching. In this application , preferably using SiCoNi to etch part of the oxide layer. Certainly, the specific size of the silicon oxide layer to be removed is also determined according to how to operate in a specific embodiment, and will not be repeated here. The etched part of the silicon oxide layer specifically exposes part of the first non-doped epitaxial growth layer 5 and the entire second non-doped epitaxial growth layer 6, but still leaves a certain thickness of the silicon oxide layer. That is to say, the entire silicon oxide layer has not been completely removed;

After part of the silicon oxide layer is removed, part of the first non-doped epitaxial growth layer 5 is exposed, and wet etching is used to remove this part of the exposed first non-doped epitaxial growth layer 5, so that the entire second The non-doped epitaxial growth layer 6 is completely exposed and suspended. Finally, a high dielectric constant material layer 7 and a metal material layer 8 are deposited on the surface of the fully exposed second non-doped epitaxial growth layer, and the high dielectric constant material layer 7 is located on the second non-doped epitaxial growth layer 6 On the surface, the metal material layer 8 is located on the surface of the high dielectric constant material layer 7, finally forming a metal gate fin-shaped semiconductor device. Specifically, an atomic layer deposition method is used to deposit a high dielectric constant material layer, and then sputtering is used to deposit a metal material layer.

In this application, a metal gate fin-shaped semiconductor device is finally formed, and the ultimate goal is to effectively suppress the short channel effect, leakage field and punch-through problems in the fin field effect transistor FinFET structure, and improve the device performance. Therefore, after the second non-doped epitaxial growth layer is exposed, an oxidation process or an in-situ water vapor generation process can be continued to form an oxide layer on the surface of the second non-doped epitaxial growth layer. Depositing polysilicon on the surface of the oxide layer as a gate can also achieve the above effects.

Embodiment two

A metal gate fin-shaped semiconductor device, the semiconductor device specifically includes a silicon substrate, a silicon oxide layer located on the upper surface of the silicon substrate, the silicon oxide layer is partially filled with a first non-doped epitaxial growth layer, Then the upper surface of the silicon oxide layer is prepared with a center-symmetrical source and drain, and a second non-doped epitaxial growth layer is suspended between the source and drain, and then a high dielectric dielectric layer is set on the second non-doped epitaxial growth layer. A constant material layer and a metal material layer are used to form a metal gate fin-shaped semiconductor device.

In summary, in a method for preparing a semiconductor device designed by the present application and its specific device, the non-epitaxial growth layer is deposited twice, and a part of the first non-epitaxial growth layer and the oxide layer are etched, and the second The non-epitaxial growth layer is exposed, and then a high dielectric constant layer and a metal layer are sequentially deposited on the outer surface of the exposed second non-epitaxial growth layer to form a gate, thus forming a fully surrounded metal gate structure. In the fin field effect transistor In the FinFET structure, problems such as short channel effect, leakage field and punch-through are effectively suppressed, and device performance is improved.

Those skilled in the art should understand that those skilled in the art can implement the variation example by combining the existing technology and the foregoing embodiments, and details are not described here. Such variations do not affect the essence of the present invention, and will not be repeated here.

The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and the devices and structures that are not described in detail should be understood to be implemented in a common manner in the art; Under the circumstances of the technical solution of the invention, many possible changes and modifications can be made to the technical solution of the present invention by using the methods and technical contents disclosed above, or be modified into equivalent embodiments with equivalent changes, which does not affect the essence of the present invention . Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (9)

1. A method for preparing a semiconductor device, characterized in that, comprising: A semiconductor device is provided, the semiconductor device includes a base layer and an oxide layer located on the upper surface of the base layer; Depositing a patterned mask layer on the upper surface of the oxide layer, and using the mask layer as a mask to etch the oxide layer to the upper surface of the base layer to form a trench; removing the mask layer, and performing a first non-doped epitaxial growth in the trench to form a first non-doped epitaxial growth layer; performing a second non-doped epitaxial growth in the trench to form a second non-doped epitaxial growth layer, and the upper surface of the second non-doped epitaxial growth layer and the upper surface of the oxide layer are in the same plane; Etching part of the oxide layer to expose the second non-doped epitaxial growth layer and part of the first non-doped epitaxial growth layer; The exposed first non-doped epitaxial growth layer is removed, and a high dielectric constant layer and a metal material layer are sequentially grown outside the second non-doped epitaxial growth layer to form a metal gate. 2. The method according to claim 1, wherein the base layer is made of single crystal silicon. 3. The method according to claim 1, characterized in that the method further comprises: The oxide layer is deposited by chemical vapor deposition. 4. The method according to claim 1, wherein the material of the oxide layer is silicon oxide. 5. The method according to claim 1, characterized in that dry etching the oxide layer to the upper surface of the base layer. 6. The method according to claim 1, further comprising: forming an oxide layer outside the second non-doped epitaxial growth layer by using an in-situ water vapor generation process; Polysilicon is deposited on the surface of the oxide layer to form a polysilicon gate. 7 . The method according to claim 1 , wherein the first non-doped epitaxial growth layer is formed using a germanium doping process. 8. The method according to claim 1, characterized in that wet etching is used to remove part of the first non-doped epitaxial growth layer. 9. The method of claim 1, wherein a portion of the oxide layer is etched using SiCoNi.