CN105355229A - Write circuit and read circuit of asynchronous circuit system for synchronous random-access memory - Google Patents

Abstract

The invention proposes a writing circuit and a reading circuit of a synchronous random access memory by an asynchronous circuit system. The asynchronous circuit system adopts a dual-track four-phase handshake protocol. The write circuit includes a write enable opening circuit part, a write address and write data conversion and transmission circuit part, a write start and a write completion response circuit part. The read circuit includes a read enable and enable circuit part, a read address and read data conversion and transmission circuit part, a read enable and read completion response circuit part. After the writing circuit and the reading circuit of the present invention are connected, the reading and writing of the synchronous random access memory by the asynchronous circuit system fully conforms to the four-phase dual-track handshake protocol, and the synchronous random access memory is completely inserted into the transmission chain of the four-phase dual-track handshake protocol, and at the same time The data delay output during reading is completely encapsulated in the reading circuit, and there is no need to adjust the original asynchronous circuit system conforming to the four-phase dual-rail handshake protocol.

Description

Write circuit and read circuit of synchronous random access memory by asynchronous circuit system

technical field

The invention belongs to the technical field of interface circuits, and relates to an interface circuit, especially a writing circuit and a reading circuit.

Background technique

At present, most digital circuit designs adopt a synchronous method, that is, a synchronous circuit. The design of synchronous circuits is simplified based on two fundamental assumptions: all signals in the circuit are binary; and all blocks share a common discrete timing defined by a global clock signal distributed throughout the circuit.

Asynchronous digital circuits, referred to as asynchronous circuits, are essentially different from synchronous circuits; although binary signals are also used, there is no common discrete timing and no global clock is required. Asynchronous circuits generally implement data synchronization, communication, and operation sequences between different components through handshake protocols. Compared with synchronous circuits, asynchronous circuits do not have high-frequency clocks, and the flipping of the circuit is only performed when the input data changes; at the same time, unlike synchronous circuits, asynchronous circuits do not need to use registers to synchronize the output of combinational logic. Therefore, the asynchronous circuit has the characteristics of low power consumption, high speed, low electromagnetic noise radiation, easy modularization and easy reuse, and is a typical green circuit.

Due to the above-mentioned advantages of asynchronous circuits, more and more attention has been paid to them in recent years, and some asynchronous CMOS digital integrated circuits have gradually occupied the market, such as the smart card market and the heterogeneous multi-core processor market. However, there is still a lack of asynchronous IP modules in the design of CMOS integrated circuits for asynchronous circuits, especially the lack of random access memory. Random access memory is used in most asynchronous circuit systems. At present, registers or latches are usually used in the design of CMOS asynchronous integrated circuits, which leads to complex circuits and high power consumption; full-customized design methods can also be used, which are cumbersome and complicated to design, and need to be specific to specific integrated circuits. The manufacturing process is carried out, and the portability is poor. At the same time, the testability of the RAM designed by these methods is poor, which is not conducive to mass production.

Therefore, if the asynchronous circuit system can adopt the mature synchronous RAM module with good testability in the existing synchronous circuit, the design and manufacturing cost of the asynchronous circuit system will be greatly reduced.

One of the most commonly used handshake protocols in asynchronous circuits is the four-phase dual-rail handshake protocol. The four-phase dual-track handshake protocol refers to the handshake communication using a dual-track encoding method and a four-phase signal transmission protocol. Dual-track encoding refers to encoding the request signal and the data signal together by using two lines to represent an information bit to form a signal for communication, that is, using two wires to represent a bit of information x. One of the wires x.t represents a logic 1 (or true value) and the other wire x.f represents a logic 0 (or false value). {x.t,x.f}={1,0} and {x.t,x.f}={0,1} are "valid" states, representing 1 and 0 respectively; {x.t,x.f}={0,0} represent "null" state; while {x.t,x.f}={1,1} is not used in the protocol. The four-phase signal transmission protocol needs to have a low-level step and is level-sensitive, so it is also called a zero-return signal transmission protocol or a level-sensitive signal transmission protocol. The four-phase signal transmission protocol needs four steps to complete a handshake process: the sending end sends data and sets the request signal to high level; the receiving end receives the data and sets the response signal to high level; the sending end responds to the receiving end and sets the request signal to high level; The signal is set to low level; the receiving end responds to the sending end and sets the response signal to low level. The four-phase two-track handshake channel is shown in Figure 1; the communication steps of the four-phase two-track handshake protocol are shown in Figure 2.

In the first step, the sender starts to send valid information. For the case of only one information bit, it sends the state of {x.t,x.f}={1,0} or {x.t,x.f}={0,1}.

In the second step, after the receiving end receives the information, in the case of multiple information bits, it needs to wait until the channels of all information bits become "valid" and then set the response signal to high level.

In the third step, the sender sends the "empty" state information after receiving the response signal (that is, the response signal is high), that is, for the case of a single information bit, that is, {x.t,x.f}={0,0} state, for multiple information bits In the case of , it is necessary to set the channels of all information bits to the "empty" state as a response.

Finally, after finding that all information bit channels are "empty" state information, the receiving end sets the response signal to low level as a response to complete the information transmission.

Static random access memory (SRAM) is a kind of memory that can save the data stored in it without refreshing the circuit, and can read and write in random order. SRAM can be divided into single-port and dual-port. Single-port has only one set of clock, address and data ports, and dual-port has two sets of clock, address and data ports. Usually its main control signals include:

ADD: address signal, use A[m:0] to represent the (m+1)-bit address signal, and A[i] to represent the i-th address signal;

: Module selection signal, usually a low level indicates that the memory module is selected;

: Write enable signal, usually a low level indicates that the write operation is valid;

RE: read enable signal, usually a high level indicates that the read operation is valid;

D_out: data output signal, use D_out[n:0] to represent the (n+1) bit data output signal, and D_out[j] to represent the jth bit data output signal;

D_in: data input signal, use D_in[n:0] to represent the (n+1) bit data input signal, and D_in[j] to represent the jth bit data input signal;

: Data output enable signal, active low;

CLK: clock signal.

Contents of the invention

The object of the present invention is to provide an interface circuit capable of realizing the application of the synchronous random access memory in the asynchronous circuit system.

In order to achieve the above object, the solution of the present invention is:

A writing circuit of an asynchronous circuit system to a synchronous random access memory, the asynchronous circuit system adopts a dual-track four-phase handshake protocol, including a write permission opening circuit part, a write address and write data conversion transmission circuit part, write start and write completion Response circuit part; the write permission opening circuit part is used to enable the write permission operation of the synchronous random access memory according to the dual-track write permission signal of the asynchronous circuit system; the write address and write data conversion transmission circuit part is used for Convert the dual-rail write address signal and write data signal of the asynchronous circuit system into the write address signal and write data signal of the synchronous random access memory; the write start and write complete response circuit parts are used to send the The synchronous RAM sends a write enable signal and sends a write complete signal to the asynchronous circuit system.

The write enable circuit part includes a first-type AND gate and a first-type tri-state gate; the two input terminals of the first-type AND gate are respectively connected to two ports of the dual-rail write enable signal of the asynchronous circuit system, The output end is connected to the control enabling end of the first type tri-state gate; the input end of the first type tri-state gate is connected to the logic 1 signal port in the dual-rail write permission signal of the asynchronous circuit system, and the output end is connected to all The write enable signal port of the synchronous random access memory.

The write address and write data conversion transmission circuit part includes a write address conversion transmission circuit; the write address conversion transmission circuit includes a logic 1 signal port of the dual-rail write address signal of the asynchronous circuit system and the The wires connected to the corresponding write data address ports in the synchronous random access memory.

The write address and write data conversion and transmission circuit part includes a write data conversion and transmission circuit; the write data conversion and transmission circuit includes the logic 1 signal port of the dual-rail write data signal in the asynchronous circuit system and the The wires connected to the corresponding write data port in the synchronous random access memory.

The write start and write completion response circuit part includes at least one first type OR gate, at least one second type OR gate and a first type C unit circuit; the input end of each first type OR gate is connected to the asynchronous circuit system A pair of address output ports of each second-type OR gate are connected to a pair of data output ports of the asynchronous circuit system; each output of the first-type OR gate and the second-type OR gate is connected to Different input ends of the first type C unit circuit, the first type C unit circuit also has an input port connected to the logic 0 signal port in the dual-rail write permission signal in the asynchronous circuit system; the output end of the first type C unit circuit includes Two branches; one branch is directly connected to the clock signal port of the synchronous random access memory, and the other branch is connected to the write completion response port of the asynchronous circuit system after the first delay circuit is connected in series.

A reading circuit for synchronous random access memory by an asynchronous circuit system, the asynchronous circuit system adopts a dual-track four-phase handshake protocol, including a read permission open circuit part, a read address and read data conversion transmission circuit part, read open and read complete Response circuit part; the read permission opening circuit part is used to enable the read permission operation of the synchronous random access memory according to the dual-rail read permission signal of the asynchronous circuit system; the read address and read data conversion transmission circuit part is used for converting a dual-rail read address signal of the asynchronous circuitry into a read address signal of the synchronous random access memory and converting a signal read from the synchronous random access memory into a dual-rail data signal of the asynchronous circuitry; the The read enable and read complete response circuit part is used to send a read enable signal to the synchronous random access memory and send a read complete signal to the asynchronous circuit system.

The read permission opening circuit part includes a second-type AND gate and a second-type tri-state gate; the two input terminals of the second-type AND gate are respectively connected to the two ports of the dual-rail read permission signal of the asynchronous circuit system, and the output terminal Connect the control enabling end of the second type tri-state gate; the input end of the second type tri-state gate is connected to the logic 1 signal port in the dual-rail read permission signal of the asynchronous circuit system, and the output end is connected to the read port of the synchronous random access memory. Signal ports are allowed.

The read address and read data conversion transmission circuit part includes a read address conversion transmission circuit; the read address conversion transmission circuit includes a logic 1 signal port directly connected to the dual-rail read address signal of the asynchronous circuit system and the The wire of the port corresponding to the read address in the synchronous random access memory.

The read address and read data conversion and transmission circuit part includes a read data conversion and transmission circuit; the read data conversion and transmission circuit includes (n1+1) branch circuits; each branch circuit includes a first type inversion device, the second type C unit circuit and two third type AND gates; in each of the branch circuits, the input end of the first type inverter is connected to the j1th bit data signal read by the synchronous random access memory; The second type C unit circuit includes two input ports and an output port, one input port is connected to the output of the read-on and read-complete response circuit parts, the other input port is connected to the output end of the second type inverter, and the output port is connected to One input end of the two third-type AND gates, the input end of the second-type inverter is connected to the read completion response port of the asynchronous circuit system; the other input end of the first third-type AND gate is connected to the first The output terminal of the class inverter, the output terminal is connected to the logic 0 signal port of the j1th double-rail read data of the asynchronous circuit system; the other input terminal of the second third type AND gate is connected to the synchronous random access memory The j1th read data signal port, the output terminal is connected to the logic 1 signal port of the j1th double-rail read data of the asynchronous circuit system; wherein, (n1+1) is the dual-rail read data signal of the asynchronous circuit system The number of digits; 0≤j1≤n1.

The read-on and read-complete response circuit parts include at least one third-type OR gate and a third-type C unit circuit; each pair of dual-rail read address ports of the asynchronous circuit system is connected to two different third-type OR gates. Input terminal; the output terminal of each third type OR gate is respectively connected to different input terminals of the third type C unit circuit, and the third type C unit circuit also has an input terminal connected to the dual-rail read enable signal of the asynchronous circuit system the logic 1 signal port; the output of the third type C unit circuit includes three branches; the first branch is directly connected to the clock signal port of the synchronous random access memory, and the second branch is connected to the asynchronous circuit after the second delay circuit is connected in series The read completion response port of the system, the third branch is connected in series with the third delay circuit to form (n1+1) branches, which are respectively connected to an input port of each second type C unit circuit.

Due to the adoption of the above solution, the beneficial effect of the present invention is: after the writing circuit and the reading circuit of the present invention are connected, the reading and writing of the synchronous RAM by the asynchronous circuit system fully complies with the four-phase dual-rail handshake protocol. In the write operation, the asynchronous circuit system acts as the sending end of the task, and the writing circuit acts as the receiving end. In the read operation, the asynchronous circuit system is first used as the task sender, and the read circuit is used as the receiver to transmit the read address; when the output data of the synchronous random access memory is ready, the read circuit is used as the task sender, and the asynchronous circuit As the receiving end, the system transmits the data read from the SRAM, so that the SRAM is completely inserted into the transmission chain of the four-phase dual-rail handshake protocol, and at the same time, the data delay output during reading is fully encapsulated in the reading circuit , no need to adjust the original asynchronous circuit system conforming to the four-phase dual-rail handshake protocol.

Description of drawings

FIG. 1 is a schematic diagram of a four-phase dual-track handshake channel;

Fig. 2 is a schematic diagram of the communication steps of the four-phase dual-track handshake protocol;

FIG. 3 is a schematic structural diagram of a writing circuit in an embodiment of the present invention;

Fig. 4 is the writing data connection schematic diagram of writing circuit shown in Fig. 3 and main signal port of asynchronous circuit system and synchronous random access memory;

5 is a timing diagram of the main process of writing data into a synchronous random access memory by an asynchronous circuit system in an embodiment of the present invention;

6 is a schematic structural diagram of a reading circuit in an embodiment of the present invention;

Fig. 7 is a schematic diagram of reading data connection between the reading circuit shown in Fig. 6 and the main signal port of the asynchronous circuit system and the synchronous random access memory;

FIG. 8 is a timing diagram of the main process of reading data from the synchronous RAM by the asynchronous circuit system in the embodiment of the present invention.

detailed description

The present invention will be further described below in conjunction with the embodiments shown in the accompanying drawings.

The invention proposes an interface circuit for an asynchronous circuit system to write and read a synchronous random access memory, which includes a write circuit and an interface circuit. Wherein, the asynchronous circuit system adopts a dual-track four-phase handshake protocol. In this embodiment, the SRAM is a dual-port SRAM. The synchronous random access memory adopting the interface circuit and connection method of the present invention can be seamlessly connected to the asynchronous circuit system adopting the dual-track four-phase handshake protocol without destroying the handshake protocol chain of the asynchronous circuit system.

On the asynchronous circuitry side, addresses and data are encoded on two rails. The address and data signals are represented as follows:

D0_in[m1:0] and D1_in[m1:0] represent the (m1+1)-bit dual-rail data signal that the asynchronous circuit system is going to output to the synchronous random access memory. Among them, D0_in[i1] and D1_in[i1] represent the i1th dual-rail data, D0_in represents a logic 0 signal, D1_in represents a logic 1 signal; (m1+1) represents the number of bits of the dual-rail write data signal of the asynchronous circuit system, 0 ≤i1≤m1.

D0_out[n1:0] and D1_out[n1:0] represent the (n1+1)-bit dual-track encoding adopted by the data read by the asynchronous circuit system to the synchronous random access memory. Among them, D0_out[j1] and D1_out[j1] represent the j1th dual-rail data, D0_out represents a logic 0 signal, D1_out represents a logic 1 signal; (n1+1) represents the number of bits of the dual-rail read data signal of the asynchronous circuit system, 0 ≤j1≤n1.

A0[m2:0] and A1[m2:0] represent (m2+1)-bit dual-rail address signals for the asynchronous circuit system to write data into the synchronous random access memory. Among them, A0[i2] and A1[i2] represent the i2th dual-rail address signal, A0 represents a logic 0 signal, and A1 represents a logic 1 signal; (m2+1) represents the number of bits of the dual-rail write address signal of the asynchronous circuit system, 0≤i2≤m2.

A0[n2:0] and A1[n2:0] represent (n2+1)-bit dual-rail address signals for the asynchronous circuit system to read data from the synchronous RAM. Among them, A0[j2] and A1[j2] represent the j2th dual-rail address signal, A0 represents a logic 0 signal, and A1 represents a logic 1 signal; (n2+1) represents the number of bits of the dual-rail read address signal of the asynchronous circuit system, 0≤j2≤n2.

A schematic structural diagram of a writing circuit for writing data into a synchronous random access memory by an asynchronous circuit system proposed by the present invention is shown in FIG. 3 . The writing circuit includes a writing permission opening circuit part, a writing address and writing data conversion transmission connection circuit part, a writing start and a writing completion answering circuit part.

The write enable enabling circuit part is used for enabling the write enable operation of the synchronous random access memory according to the dual-rail write enable signal of the asynchronous circuit system. The writing permission opening circuit part includes a first-type AND gate and a first-type three-state gate. The AND gate of the first type includes two input ends and an output end, and the tri-state gate of the first type includes an input end, an output end and a control enabling end. The two input terminals of the first type AND gate are respectively connected to the two ports of the dual-rail write enable signal of the asynchronous circuit system, and the output terminals are connected to the control enable terminal of the first type tri-state gate. The input end of the first type tri-state gate is connected to the port WE1 of the logic 1 signal in the dual-rail write enable signal of the asynchronous circuit system, and the output end is connected to the write enable signal port of the synchronous random access memory.

The write address and write data conversion transmission circuit section includes a write address conversion transmission circuit and a write data conversion transmission circuit. The writing address conversion transmission circuit is used for converting the dual-rail writing address signal of the asynchronous circuit system into the writing address signal of the synchronous random access memory. The writing data conversion transmission circuit is used for converting the dual-rail writing data signal of the asynchronous circuit system into the writing data signal of the synchronous random access memory. The writing address conversion transmission circuit includes a wire connecting the logic 1 signal port of the i2th bit of the (m2+1) bit dual-rail writing address signal of the asynchronous circuit system and the i2th bit port of the writing data address in the synchronous random access memory. The writing data conversion transmission circuit includes a wire connecting the logic 1 signal port of the i1th bit of the (m1+1) bit dual-rail writing data signal of the asynchronous circuit system and the i1th bit port of the writing data port of the synchronous random access memory.

The write enable and write complete response circuit part is used to send a write start signal to the synchronous random access memory and send a write complete signal to the asynchronous circuit system. The write start and write complete response circuit part includes (m1+1) first-type OR gates connected with (m1+1) pairs of data output ports of the asynchronous circuit system, (m2+1) and (m2) of the asynchronous circuit system +1) A second-type OR gate connected to the address output port and a first-type C-unit circuit with (m1+m2+3) inputs. The output ends of each of the first type OR gate and the second type OR gate are connected to different input ends of the first type C unit circuit, in addition, the first type C unit circuit also has an input end and a double rail of an asynchronous circuit system A logic 0 signal in the write enable signal is connected to port WE0. The output end of the first type C unit circuit includes two branches, one branch is directly connected to the clock signal port of the synchronous random access memory, and the other branch is connected to the asynchronous circuit system writing completion response port after being connected in series with the first delay circuit.

The connection between the writing circuit and the main signal port of the asynchronous circuit system and the synchronous random access memory is shown in FIG. 4 . Among them, the synchronous RAM The port can be directly controlled by the asynchronous circuit system to be set to a low level during data writing, or it can be directly connected to a low level as shown in Figure 4. The WE1 and WE0 signals of the asynchronous circuit system are write enable signals using dual-track coding, where WE1 represents a logic 1 signal, and WE0 represents a logic 0 signal; Addr_a is a write response signal port.

In the write circuit, the write enable signal of the dual-rail code of the asynchronous circuit system is output to the port. When WE0 is high and WE1 is low, The output is low level; when WE0 is low level and WE1 is high level, The output is high level; when both WE0 and WE1 are low level, The output is high impedance. The signal representing logic 1 in the data signal and address signal of the dual-rail encoding of the asynchronous circuit system is directly output to the corresponding data and address bit ports of the synchronous random access memory through the writing circuit, that is, A1[i2] corresponds to A[i2], and D1_in[ i1] corresponds to D_in[i1]. At the same time, each group of dual-rail signals in the double-track encoded data signal and address signal are respectively connected to the first type of OR gate and the second type of OR gate operation, and then the output of the first type of OR gate and the second type of OR gate are connected together with the WE0 signal into the first class C unit circuit. When WE0 becomes high level, and both the dual-rail data and address signals change from "empty" state to "valid" state, the output terminal of the first type C unit circuit changes from low level to high level, generating a rising edge Signal. This rising edge signal is directly output to the CLK port of the SRAM. At the same time, the high-level signal is output to the Addr_a port after a delay, as a response to the effective reception of the data and address signals of the asynchronous circuit system. When WE0 is low level, and both the dual-rail data and address signals become "empty", the first type C unit circuit outputs a low level, and this low level is output to the Addr_a port after a delay, as an asynchronous circuit The system data and address are the response to the empty state valid detection.

The main process of writing data to the synchronous RAM by the asynchronous circuit system is shown in Figure 5, and the specific process is as follows:

a) The asynchronous circuit system sets WE1 to low level and WE0 to high level, and at the same time puts the data and address to be written into D0_in[m1:0], D1_in[m1:0] and A0[m2:0] respectively ], A1[m2:0]. The asynchronous circuitry data is encoded using a four-phase dual-rail handshake protocol.

b) The signal in step a) is converted by the writing circuit, so that the output terminal of the writing circuit For low level, the A[m2:0] and D_in[m1:0] terminals respectively place the address of the data to be written and the data to be written.

c) When all the data in step b) is ready, the writing circuit outputs a rising edge signal from the CLK port, writes the data into the synchronous random access memory, and then the writing circuit writes the Addr_a port voltage of the writing circuit according to the four-phase dual-rail protocol Pull high in response to the asynchronous circuitry, indicating that the data to be written and the corresponding address have been received.

d) After the asynchronous circuit system detects that the input level of the Addr_a port is high, it transfers D0_in[m1:0], D1_in[m1:0] and A0[m2:0], A1[m2 :0] and WE1 and WE0 are all set to low level, the write circuit Correspondingly, it becomes a high-impedance state.

e) After the writing circuit detects that D0_in[m1:0], D1_in[m1:0] and A0[m2:0], A1[m2:0] are all at low level, the Addr_a port will Pulled low as an output data signal to asynchronous circuitry

For an empty response, complete a write task.

The present invention also proposes a reading circuit for reading data from a synchronous random access memory using an asynchronous circuit system using a dual-track four-phase handshake protocol, and its structural diagram is shown in FIG. 6 . The read circuit includes a read enable and enable circuit part, a read address and read data conversion and transmission circuit part, a read enable and read completion response circuit part.

The read enable enabling circuit part is used for enabling the read enable operation of the synchronous random access memory according to the double-rail read enable signal of the asynchronous circuit system. The read enable opening circuit part includes a second-type AND gate and a second-type tri-state gate. The second-type AND gate includes two input terminals and an output terminal, and the second-type tri-state gate includes an input terminal, an output terminal and a control enabling terminal. The two input terminals of the second-type AND gate are respectively connected to the two ports of the dual-rail read enable signal of the asynchronous circuit system, and one output terminal is connected to the control enable terminal of the second-type tri-state gate. The input end of the second type tri-state gate is connected to the logic 1 signal port RE1 of the dual-rail read enable signal of the asynchronous circuit system, and the output end is connected to the wire of the read enable signal port of the synchronous random access memory.

The read address and read data conversion transmission circuit part includes a read address conversion transmission circuit and a read data conversion transmission circuit, which are respectively used to convert the dual-rail read address signal of the asynchronous circuit system into the read address signal and the read address signal of the synchronous random access memory. Dual-rail data signal used to convert signals read from synchronous RAM to asynchronous circuitry.

The read address conversion transmission circuit includes a wire directly connecting the logic 1 signal port of the j2th bit of the (n2+1) double-rail read address signal in the asynchronous circuit system and the j2th bit port of the synchronous random access memory read address.

The read data conversion transmission circuit includes (n1+1) branch circuits. Each branch circuit includes a first-type inverter, a second-type C unit circuit with two inputs and two third-type AND gates. The function of the j1th branch circuit is to convert the j1th bit data signal read by the synchronous RAM into the j1th bit dual-rail read data signal of the asynchronous circuit system. The first type of inverter includes an input terminal and an output terminal, and the input terminal is connected to the j1th bit data signal read by the SRAM. A second type of C cell circuit includes two input ports and one output port. The read completion response port (D_out_a) of the asynchronous circuit system is connected to an input port of the second type C unit circuit in each branch circuit after being connected in series with a second type inverter, and the third part of the read open and read completion response circuit part The output port of the C-like unit circuit is connected in series with the third delay circuit and then connected to another input port of the second C-unit circuit of each branch circuit of the read data conversion and transmission circuit. The output end of the second type C unit circuit includes two branches, which are respectively connected to one input end of two third type AND gates. The other input terminal of the first third-type AND gate is connected to the output terminal of the first-type inverter in the branch circuit, and the output terminal is connected to the logic 0 signal port of the j1th double-rail read data of the asynchronous circuit system ; The other input end of the second AND gate of the third type is connected to the j1th bit read data signal of the synchronous random access memory, and the output end is connected to the logic 1 signal port of the j1th bit dual-rail read data of the asynchronous circuit system.

The read-on and read-complete response circuits are used to send a read-start signal to the synchronous random access memory and send a read-complete signal to the asynchronous circuit system. The read-on and read-complete response circuits include (n2+1) third-type OR gates respectively connected to (n2+1) pairs of dual-rail read address ports of the asynchronous circuit system, and one AND (n2+1) third-type OR gates The third type C unit circuit connected to the output end of the OR gate. Wherein, the third type C unit power supply includes (n2+2) input terminals, and the output terminals of each third type OR gate are respectively connected to different input terminals of the third type C unit circuit; the third type C unit circuit There is also an input connected to the logic 1 signal port RE1 in the dual rail read enable signal of the asynchronous circuitry. The output terminal of the third type C unit circuit includes three branches. One branch is directly connected to the clock signal port of the synchronous random access memory; the other branch is connected in series with the second delay circuit and then connected to the read completion response port of the asynchronous circuit system; the third branch is connected in series with the third delay circuit to form (n1+1) branches, They are respectively connected to one input port of (n1+1) second type C unit circuits in the read data conversion and transmission circuit.

The connection between the reading circuit and the main signal port of the asynchronous circuit system and the synchronous random access memory is shown in FIG. 7 . Among them, the synchronous RAM and It can be directly controlled by the asynchronous circuit system to be set to low level during data reading, or it can be directly connected to low level as shown in FIG. 7 . The RE1 and RE0 signals of the asynchronous circuit system are read enable signals using dual-rail encoding, where RE1 represents a logic 1 signal, and RE0 represents a logic 0 signal; Addr_a is the read response signal port; D_out_a is the read completion response port.

In the read circuit, the dual-rail code read enable signal of the asynchronous circuit system is output to the RE port through the second-type AND gate and the second-type tri-state gate. When RE0 is high level and RE1 is low level, RE output is low level; when RE0 is low level and RE1 is high level, RE output is high level; when both RE0 and RE1 are low level, The RE output is high impedance.

The signal representing logic 1 in the dual-rail coded address signal of the asynchronous circuit system is directly output to the corresponding address bit port of the synchronous RAM through the read circuit, that is, A1[j2] corresponds to A[j2]. At the same time, each group of dual-rail signals in the dual-rail coded address signals is respectively connected to the third-type OR gate operation, and then the output of the third-type OR gate and the RE1 signal are connected to the third-type C unit together. When RE1 becomes high level and the dual-rail address signals change from "empty" state to "valid" state, the output terminal of the third type C unit circuit changes from low level to high level, generating a rising edge signal. This rising edge signal is directly output to the CLK port of the SRAM. At the same time, the high-level signal is output to the Addr_a port after a delay, as a response to the effective reception of the address signal of the asynchronous circuit system. When RE1 is low level, and the dual-rail address signals are all in the "empty" state, the third type C unit circuit outputs low level, and this low level is output to the Addr_a port after a delay, as the data for the asynchronous circuit system and the response to the valid detection of the empty state of the address.

After the CLK signal output by the reading circuit is delayed, and the data reception response signal D_out_a of the asynchronous circuit system is input to the second type C unit circuit after passing through the second inverter, the data output port signal D_out[ to the synchronous random access memory is generated. j1] output control signal. When D_out_a is low level and the signal is high level after CLK delay, the output of the second type C unit circuit is high level, at this time the D0_out[j1] and D1_out[j1] signals correspond to the dual-rail coding of D_out[j1] Signal. When D_out_a is high level and the signal is low level after CLK delay, no matter what level D_out[j1] is, both D1_out[j1] and D0_out[j1] output low level and become "empty" state.

The main process of reading data from the synchronous RAM by the asynchronous circuit system is shown in Figure 8, and the specific process is:

a) The asynchronous circuit system sets RE0 to low level and RE1 to high level, and at the same time puts the addresses of the data to be read in A0[n2:0] and A1[n2:0] respectively. Address data is encoded using a dual-rail protocol.

b) The signal in step a) passes through the read circuit, and when the output terminal RE of the read circuit is at a high level, it is converted into an address signal of address A[n2:0] of the synchronous random access memory ready to read data.

c) When all the data in step b) is ready, the reading circuit outputs a rising edge signal from the CLK port, and then the reading circuit pulls the Addr_a port level of the reading circuit high according to the four-phase dual-rail protocol, and sends to the asynchronous circuit system Indicates that the address to read data has been received.

d) After the asynchronous circuit system detects that the input level of the Addr_a port is high, it sets A0[n2:0], A1[n2:0], RE1 and RE0 all to low level according to the four-phase dual-rail protocol.

e) The reading circuit reads data from the D_out[n1:0] port of the SRAM after a period of delay. The delay time is greater than the interval from when the CLK terminal of the synchronous random access memory is ready to output data after receiving the rising edge signal. Then, the reading circuit converts the data read by the D_out[n1:0] port into a dual-track protocol code and outputs it on D0_out[n1:0] and D1_out[n1:0].

f) After the asynchronous circuit system detects that D0_out[n1:0] and D1_out[n1:0] have valid data, it reads the data in; and pulls the level of the D_out_a port high according to the four-phase dual-rail protocol as a reference to the read circuit Acknowledgment, indicating that data has been received.

g) After the reading circuit detects that the D_out_a port is at a high level, it pulls down all the levels of the D0_out[n1:0] and D1_out[n1:0] ports according to the four-phase dual-rail protocol.

h) The asynchronous circuit system detects that the D0_out[n1:0] and D1_out[n1:0] port levels are all low, and then pulls the D_out_a port level low according to the four-phase dual-rail protocol, as a response to the read circuit, indicating data The signal is empty and has been received, and a read task is completed.

To sum up, after the writing circuit and the reading circuit of the present invention are connected, the reading and writing of the synchronous RAM by the asynchronous circuit system fully complies with the four-phase dual-track handshake protocol. In the write operation, the asynchronous circuit system acts as the sending end of the task, and the writing circuit acts as the receiving end. In the read operation, the asynchronous circuit system is first used as the task sender, and the read circuit is used as the receiver to transmit the read address; when the output data of the synchronous random access memory is ready, the read circuit is used as the task sender, and the asynchronous circuit As the receiving end, the system transmits the data read from the SRAM, so that the SRAM is completely inserted into the transmission chain of the four-phase dual-rail handshake protocol, and at the same time, the data delay output during reading is fully encapsulated in the reading circuit , no need to adjust the original asynchronous circuit system conforming to the four-phase dual-rail handshake protocol.

The above description of the embodiments is for those of ordinary skill in the art to understand and apply the present invention. It is obvious that those skilled in the art can easily make various modifications to these embodiments, and apply the general principles described here to other embodiments without creative effort. Therefore, the present invention is not limited to the embodiments herein. Improvements and modifications made by those skilled in the art according to the disclosure of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims (10)

1. an asynchronous circuit system is to the write circuit of synchronous random access memory, described asynchronous circuit system adopts double track four phase Handshake Protocol, it is characterized in that: comprise writing and allow open circuit part, writing address and write data conversion and transmission circuit part, write and start and write into answering circuit part;

Described writing allows open circuit part to operate for the permission of writing of opening described synchronous random access memory according to the double track written allowance signal of described asynchronous circuit system;

Said write address and write data conversion and transmission circuit part are used for the writing address signal and the write data-signal that the double track writing address signal of described asynchronous circuit system and write data-signal are converted to described synchronous random access memory;

Described writing starts and writes into answering circuit part and write settling signal for sending to described synchronous random access memory to write enabling signal and send to described asynchronous circuit system.

2. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: described in write and allow open circuit part to comprise the first kind and door and first kind triple gate; The described first kind is connected two ports of the double track written allowance signal of described asynchronous circuit system respectively with two input ends of door, and output terminal connects the control Enable Pin of described first kind triple gate; The input end of described first kind triple gate connects the logical one signal port in the double track written allowance signal of described asynchronous circuit system, and output terminal connects the written allowance signal port of described synchronous random access memory.

3. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: said write address and write data conversion and transmission circuit part comprise writing address conversion and transmission circuit;

Said write address conversion and transmission circuit comprises the wire connected by write data address port corresponding with described synchronous random access memory for the logical one signal port of the double track writing address signal of described asynchronous circuit system.

4. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: said write address and write data conversion and transmission circuit part comprise write data conversion and transmission circuit;

Said write data conversion and transmission circuit comprises wire write FPDP corresponding with described synchronous random access memory for the logical one signal port of double track write data-signal in described asynchronous circuit system connected.

5. asynchronous circuit system according to claim 1 is to the write circuit of synchronous random access memory, it is characterized in that: described in write and start and write into answering circuit part and comprise at least one first kind or door, at least one Equations of The Second Kind or door and first kind C element circuit;

The input end of each first kind or door is connected with a pair address output end mouth of described asynchronous circuit system, the input end of each Equations of The Second Kind or door is connected with a pair data-out port of described asynchronous circuit system;

The output terminal of each first kind or door and Equations of The Second Kind or door is all connected the different input ends of first kind C element circuit, and first kind C element circuit also has an input end to connect logic zero signal port in described asynchronous circuit system in double track written allowance signal;

The output terminal of first kind C element circuit comprises two-way branch; One tunnel branch directly connects the clock signal port of described synchronous random access memory, another road branch connect to connect described asynchronous circuit system after the first delay circuit write into response port.

6. an asynchronous circuit system is to the reading circuit of synchronous random access memory, described asynchronous circuit system adopts double track four phase Handshake Protocol, it is characterized in that: comprise and read to allow open circuit part, read address and read data conversion and transmission circuit part, read open and run through answering circuit part;

Described reading allows open circuit part to operate for the permission of reading of opening described synchronous random access memory according to the double track read enable signal of described asynchronous circuit system;

Described reading address and reading data conversion and transmission circuit part are used for the double track reading address signal of described asynchronous circuit system being converted to the reading address signal of described synchronous random access memory and the signal read from described synchronous random access memory being converted to the dual-rail data signal of described asynchronous circuit system;

Answering circuit part is opened and run through to described reading for sending reading enabling signal to described synchronous random access memory and sending reading settling signal to described asynchronous circuit system.

7. asynchronous circuit system according to claim 6 is to the reading circuit of synchronous random access memory, it is characterized in that: described in read to allow open circuit part to comprise Equations of The Second Kind and door and Equations of The Second Kind triple gate;

Equations of The Second Kind is connected two ports of the double track read enable signal of described asynchronous circuit system respectively with two input ends of door, and output terminal connects the control Enable Pin of Equations of The Second Kind triple gate;

The input end of Equations of The Second Kind triple gate connects the logical one signal port in the double track read enable signal of described asynchronous circuit system, and output terminal connects the read enable signal port of described synchronous random access memory.

8. asynchronous circuit system according to claim 6 is to the reading circuit of synchronous random access memory, it is characterized in that: described reading address and reading data conversion and transmission circuit part comprise reading address conversion and transmission circuit;

Described reading address conversion and transmission circuit comprises the wire reading the corresponding ports of address in the logical one signal port of the double track reading address signal directly connecting described asynchronous circuit system and described synchronous random access memory.

9. asynchronous circuit system according to claim 6 is to the reading circuit of synchronous random access memory, it is characterized in that: described reading address and reading data conversion and transmission circuit part comprise reading data conversion and transmission circuit;

Described reading data conversion and transmission circuit comprises (n1+1) individual branch circuit; Each branch circuit includes first kind phase inverter, Equations of The Second Kind C element circuit and two the 3rd classes and doors;

In each described branch circuit, the input end of first kind phase inverter connects the jth 1 bit data signal of described synchronous random access memory reading; Equations of The Second Kind C element circuit comprises two input ports and an output port, the output opening and run through answering circuit part is read described in an input port connects, another input port connects the output terminal of Equations of The Second Kind phase inverter, output port connects an input end of two the 3rd classes and door, and the reading that the input end of Equations of The Second Kind phase inverter connects described asynchronous circuit system completes response port;

First the 3rd class is connected the output terminal of first kind phase inverter with another input end of door, output terminal connects the logic zero signal port of jth 1 double track reading data of described asynchronous circuit system; Second the 3rd class is connected jth 1 readout data signal port of described synchronous random access memory with another input end of door, output terminal connects the logical one signal port of jth 1 double track reading data of described asynchronous circuit system;

Wherein, (n1+1) is the figure place of the double track readout data signal of described asynchronous circuit system; 0≤j1≤n1.

10. asynchronous circuit system according to claim 9 is to the reading circuit of synchronous random access memory, it is characterized in that: described in read to open and run through answering circuit part and comprise at least one the 3rd class or door, the 3rd class C element circuit;

Often pair of double track of described asynchronous circuit system reads address port and connects the 3rd different classes or two input ends of door; The output terminal of each 3rd class or door connects the different input end of the 3rd class C element circuit respectively, and the 3rd class C element circuit also has an input end to connect logical one signal port in the double track read enable signal of described asynchronous circuit system;

The output of the 3rd class C element circuit comprises three tunnel branches; First via branch directly connects the clock signal port of described synchronous random access memory, second tunnel branch connect to connect described asynchronous circuit system after the second delay circuit run through response port, form (n1+1) road branch after 3rd tunnel branch series connection the 3rd delay circuit, be connected with an input port of each Equations of The Second Kind C element circuit respectively.