CN105354010B - Processor and method for executing hardware data by processor - Google Patents

Abstract

A processor and a method for executing hardware data by the processor are provided, the processor comprises a processing core, the processing core detects whether a preset program is executed on the processor and inquires the prefetching characteristic related to the preset program, wherein the prefetching characteristic is mutual exclusion or sharing. The processor also includes a hardware data prefetcher that performs hardware prefetching for the predetermined program using the prefetch characteristic. The present invention can perform an analysis of changing prefetch characteristics at runtime, thus making it easier to determine when other memory access agents will access which memory block at compile time, as opposed to software prefetching.

Description

Processor and method for executing hardware data by processor

technical field

This invention relates to data prefetching for processors and claims priority to US Provisional Application No. 62/066,131, filed October 20, 2014, which is incorporated by reference in its entirety.

Background technique

As the processor's internal access time to the cache memory continues to grow unequal to the processor's access time to the system memory, it highlights the need for better prefetch methods for processors. For example, Mowry describes a way to modify a compiler to use exclusive-mode prefetching that, when performing local analysis on partitioned memory, refers to an "equivalent class, which may be a reference set of a single reference," and Insert "An exclusive-mode prefetch rather than a shared-mode prefetch on a given equivalent class if at least one member of the equivalent class is a write", see "Delay tolerance of data prefetching controlled by software ", Mowry, Todd Carl, Ph.D. Dissertation, Stanford University, 1994, p. 89.

One disadvantage of the software-based approach to prefetching, as Mowry states, is that the prefetch instructions will be written in the program and thus increase the microcode size, which may need to be stored on the system's primary storage medium (such as the hard disk) More storage space to keep larger programs, and also to maintain more space in system memory while larger programs are executing. Additional instructions also consume processor resources, such as dispatch slots, reservation station areas, and execution unit areas, which can negatively impact processor performance and, more specifically, reduce the effective The look-ahead capability, therefore, has a huge impact on the parallel processing capabilities using the instruction hierarchy. Another disadvantage is that it will not benefit all programs executed on the processor, but only those programs that are profiled and compiled using an optimizing compiler.

Contents of the invention

The present invention provides a processor comprising a core for detecting whether a predetermined program is executing on the processor, the core also queries a prefetch characteristic associated with the predetermined program being executed on the processor, Wherein the prefetching feature is mutual exclusion or sharing. The processor also includes a hardware data prefetcher that uses the prefetch feature to perform hardware prefetch for the predetermined program.

The present invention further provides a hardware data prefetcher method executed by a processor, the method includes querying a prefetching characteristic related to the predetermined program being executed on the processor, wherein the prefetching characteristic is exclusive or shared. The method also includes performing hardware prefetching for the predetermined program using the prefetch feature.

The present invention also provides a processor, the processor includes a core for detecting whether a predetermined program is being executed on the processor, and in response to detecting that the predetermined program is being executed on the processor, each of the processors Each of the one or more range registers of the memory device loads an address range thereinto, each of the one or more range registers has an associated prefetch property, wherein the prefetch property is mutually exclusive or shared. The processor also includes a hardware data prefetcher that performs hardware prefetching for the predetermined program using the prefetching characteristics associated with the address range loaded into the range register.

The present invention also provides a hardware data prefetcher method executed by a processor, the method includes detecting whether a predetermined program is being executed on the processor. The method also includes loading address ranges into one or more range registers of each of the processors in response to detecting that the predetermined program is being executed on the processor, each of the one or more range registers The device has an associated prefetch characteristic, wherein the prefetch characteristic is exclusive or shared. The method also performs hardware prefetching for the predetermined program using the prefetch property associated with the address range loaded into the range register.

The present invention can observe the accesses of memory blocks by other memory access agents during operation, that is, perform analysis to change the prefetch characteristics, so compared with software prefetch, it is easy to determine other memory access agents at compile time When to access which memory block.

Description of drawings

FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of the hardware data prefetcher of FIG. 1 .

FIG. 3 is a flowchart of the operation of the system of FIG. 1 .

4 to 11 are flowcharts of the operation of dynamically updating the prefetch characteristic according to the access analysis of a memory block by multiple memory access agents in FIG. 1 .

12 is a flowchart of operations for performing hardware prefetching using off-line program analysis to determine prefetch characteristics.

Figure 13 depicts a block diagram of multiple range registers.

FIG. 14 is a flowchart of the operation of dynamically updating the prefetch characteristic according to the access analysis of a memory block by multiple memory access agents in FIG. 1 .

Among them, a brief description of the symbols in the drawings is as follows:

100: Computing Systems

101: Memory access agent

102: Nuclear

103: Processor

104: Graphics Processing Unit (GPU)

106: Direct memory access (DMA) device

108: System memory

112: bus

114: memory block

122: Hardware data prefetcher

124: Last level cache memory (LLC)

132: Prefetch feature

202: Memory access history

204: Update module

206: Prefetch module

212: Part of memory access history 206

208: Prefetch request

232: Microcode Extraction

234: Program load/store

236: Spy

1302: Address range field

1304: Prefetch attribute field

302～312, 402～406, 502～506, 602～608, 702～712, 802～812, 902～912, 1002～1008, 1102～1112, 1202～1208, 1402～1408: steps.

Detailed ways

<term>

A memory access agent is a device that accesses system memory. For example, processing cores, graphics processing units, and peripherals that perform direct memory access (DMA) are all memory access agents.

The hardware data prefetcher reads data from system memory based on an estimate that the memory access agent will need the data in the future. In particular, as described herein, a hardware prefetch is not a software prefetch, it refers to a processor Data is read from system memory by the processor as a result of executing an architectural prefetch instruction. Thus, the processor performs hardware prefetching based on the processor's analysis at runtime (ie, analysis of memory accesses that occurs concurrently with hardware prefetching). In contrast, software prefetching related to prefetching instructions inserted in the program architecture (eg, at compile time) is performed before program execution, and thus does not occur simultaneously with software prefetching. The data read by the hardware prefetch execution may be instructions executed by the processor, or non-instruction data, such as data operands when the processor executes instructions.

A memory block is a series of storage locations, such as memory pages, in system memory.

The prefetch feature is used to indicate the prefetch nature required by the data reader to be mutually exclusive with the ownership of the relevant cache line (mutually exclusive prefetch feature), or the requirement is to allow other memory blocks to reserve the cache line The prefetch nature of the replica (shared prefetch feature). When a prefetch uses the exclusive prefetch feature, it will consist of a bus transfer instructing each other memory access agent to invalidate its local cache line copy (writing back the current data value if modified), which is usually When considered to be a read invalid bus transfer, read intent-to-modify bus transfer, read ownership, or similar technical names; conversely, when prefetching uses the shared prefetch feature, it will include a shared state that allows each Other memory access agents keep their local cache line copies of bus transfers, which are often referred to as pure read bus transfers, or read shared OK bus transfers, or similar technical names.

FIG. 1 shows a block diagram of a computer system 100 according to an embodiment of the present invention. The computer system 100 includes a memory access broker 101 that shares a system memory 108 and is accessed through a bus 112 . The memory access agent 101 may include a peripheral device 106 performing direct memory access (DMA), a graphics processing unit (GPU) 104 , and a processor 103 . The processor 103 includes a plurality of processing cores 102, a last level cache (LLC) 124 shared by the cores 102, and a hardware data prefetcher 122, and the GPU 104 and the DMA 106 may also include a hardware data prefetcher 122. Although only two cores 102 are shown in FIG. 1 , embodiments with other numbers of cores can also utilize the techniques of the present invention.

The hardware data prefetcher 122 includes a prefetch property 132, which is used by the hardware data prefetcher 122 to perform hardware prefetch from a memory block 114 of the system memory 108, the prefetch property 132 has a value of exclusive or shared . The hardware data prefetcher 122 dynamically and selectively updates the prefetch characteristics 132 based on the analysis of accesses to the memory block 114 by the memory access agent 101 . The hardware data prefetcher 122 will be further described in FIG. 2 and other diagrams below.

The processor 103 may include a bus interface unit as an interface between the processor 103 and the bus 112, and each core 102 includes an instruction cache, instruction decoder, instruction dispatcher, memory subsystem (e.g. load/store unit, memory buffer), other execution units, and a local data cache (such as a first-level data cache).

When the hardware data prefetcher 122 issues a hardware prefetch request to the bus interface unit, it will be accompanied by the prefetch characteristic 132 (ie, shared or exclusive). The bus unit responds and performs a transfer on the bus 112 to take ownership of the cache line associated with the hardware prefetch request. If the prefetch property 132 is exclusive, the BUI executes a command to instruct other memory access agents 101 to invalidate their local cache line copies and to write back the current data values when the local cache line copies are modified. If the prefetch property 132 is shared, the bus interface unit performs a bus transfer that allows each other memory access agent to keep its local copy of the cache line.

When a cache line prefetches the cache memory of a processor 103 and the cache line can be prefetched, its state is either exclusive to other cores 102 or its state is shared with other system memory 108 shared by other memory access agents 101. For example, if a cache line is to be shared by multiple cores 102, it can effectively cause the cache line to be prefetched in the shared state; , it effectively prefetches cache lines under mutual exclusion rather than sharing.

Please refer to FIG. 2 , which depicts a block diagram of the hardware data prefetcher 122 in FIG. 1 . The hardware data prefetcher 122 includes an update module 204 for receiving information from the memory access history 202 . The memory access history 202 includes information about accesses made to the system memory 108 by the memory access agent 101. In particular, the memory access history 202 includes the microcode fetches executed by each core 102 from the system memory 108. 232 (i.e., instruction fetch 232) information, program loads/stores 234 performed by the core 102 to the system memory 108, and snoops 236 generated in response to accesses to the system memory 108 generated on the bus 112 (the system Memory 108 accesses are generated by one of a plurality of memory access agents 101 including the hardware data prefetcher 122). This information may include, but is not limited to, the memory address, the type of access (e.g., fetch, load, store), and the identity of each memory access agent 101 (which also includes the core 102 that originated the access). identification code). Preferably, the hardware data prefetcher 122 maintains a separate prefetch profile 132 and separate memory history 202 for active blocks 114 of system memory 108 accessed by the processor 103 . The update module 204 updates the prefetch characteristic 132 according to the analysis of the memory access history 202 , related embodiments will be described as follows.

The hardware data prefetcher 122 also includes a prefetch module 206 that receives the prefetch characteristics 132 . When starting the prefetch module 206 to analyze the memory access history of the core 102, and predicting those data that will be needed by the core 102 in the future according to the analysis, the prefetch module 206 also receives a memory access history related to the core 102 202 part of 212. The prefetching module 206 performs hardware prefetching of the prefetched data by generating a prefetch request 208 including the prefetch characteristic 132 to the bus interface unit. The prefetch characteristic may include a default value, that is, shared or mutual Rebuke. For example, the preset value can be preset by selectively blowing the fuse and its state when the core 102 is manufactured, or by a constant value in the core 102 microcode. The prefetch module 206 may prefetch one or more valuable cache lines from the system memory 108, and store them in the cache memory 124, and/or the cache memory of the processor 103 lower in the cache memory hierarchy ( For example, in the private cache memory of core 102).

Please refer to FIG. 3 , which depicts a flowchart of the operation of the system shown in FIG. 1 .

In step 302 , the memory access agent 101 accesses a memory block 114 in the system memory 108 , the access may include the core 102 accessing the memory block 114 as described in step 306 . The hardware data prefetcher 122 accumulates access information in the memory access history 202 associated with each active memory bank 114. The flow goes to step 304 .

In step 304, the update module 204 analyzes the memory access agent 101's access to the memory block 114, and dynamically updates the prefetch characteristic 132 related to the memory block 114 according to the analysis. In step 312 , the update module 204 continues to analyze and update the prefetch characteristic 132 when the prefetch module 206 continues to perform hardware prefetch on the memory block 114 . Steps 304 to 312 in FIG. 3 have shown the operation flow, and the embodiment of the analysis will be described later with subsequent figures.

In step 306, core 102 executes the program, which includes fetching program instructions from system memory 108 and performing loads/stores to system memory 108 in response to execution of the fetched program instructions. In addition, instructions access, load, and store access memory blocks 114 (eg, memory pages) of system memory 108 . Basically, the access will be performed to multiple memory banks 114 . The hardware data prefetcher 122 accumulates access information in the memory access history 202 associated with each active memory bank 114 . The process goes from step 306 to step 308 .

In step 308 , the prefetch module 206 predicts which data of the memory block 114 will be needed by the core 102 according to the portion 212 of the memory access history 202 of the core 102 to the memory block 114 accumulated in step 306 . The flow goes from step 308 to step 312 .

In step 312 , the prefetch module 206 performs a hardware prefetch of the data estimated in step 308 using the prefetch characteristics 132 dynamically updated in step 304 . Although steps 302 to 304 show the memory access broker 101 driving the update of the prefetch feature, it should be noted that the memory access by the memory access broker 101 at step 302 and the prefetch at step 304 Fetch properties 132 dynamic updates can occur concurrently. Furthermore, although the estimation is driven by memory accesses by the core 102 at steps 306, 308, through 312 of the flow, and the estimation uses the dynamically updated prefetch feature to drive hardware prefetching, it should be noted that at step 306 The memory access by core 102 and the prefetching at step 308 and the hardware prefetching at step 312 may occur concurrently. As shown in FIG. 3 , return to steps 302 and 306 from step 312, because the process occurs simultaneously in steps 302 and 304, and steps 306, 308 and 312, so the prefetching performed in step 312 is hardware prefetching. No software prefetching.

It should be noted that although the above process only depicts the operation of a single memory block, the hardware data prefetcher 122 can perform hardware data prefetch on multiple memory blocks 114, and can also use the dynamically updated prefetch feature at the same time 132 for prefetching. Preferably, the hardware data prefetcher 122 maintains an associated dynamically updated prefetch characteristic 132 for each memory block 144 for which it performs hardware prefetch.

One benefit of mutual exclusion rather than shared prefetch cache lines is that doing so results in a single bus transfer instead of two bus transfers, i.e. instead of a first transfer of requested data followed by a get and ownership A second transfer of mutually exclusive data. Mutual prefetch is a single transfer that combines two requests and requires mutual exclusion of the data. This approach is especially useful for architectures with multi-chip multi-core processors where each core has its own last-level cache. There are benefits.

The benefit of hardware prefetching based on the prefetching characteristics described here to dynamically change between shared or exclusive over the software prefetching solution is that the hardware prefetching solution can observe other memory access agents at runtime. accesses to memory blocks, i.e. when they occur perform analysis that changes the prefetching characteristics, however for software prefetch solutions it is difficult to determine at compile time when other memory access agents will which memory block to access.

Please refer to FIG. 4 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the analysis of the memory access agent 101 accessing a memory block 114 in FIG. 1 . The flow starts at step 402 .

In step 402, the initial value of the prefetch characteristic 132 of the memory bank 114 is mutually exclusive, because the default value is mutually exclusive (as described above), or it is based on an initial access to the memory bank 114 The prefetch property 132 of the memory block 114 is initialized to mutual exclusion (eg, as described in accordance with FIG. 6 or FIG. 10 ). In general, if a core 102 reads data it will most likely also update the data, and in general, the data in the memory bank 114 will generally have similar properties. Therefore, as previously mentioned, mutually exclusive prefetching of cache lines to perform a single bus transfer rather than multiple bus transfers can reduce bus 112 traffic and reduce latency. The flow goes to step 404 .

In step 404, the hardware data prefetcher 122 is notified that a cache line in the memory bank 114 has been snooped by other memory access agents 101 and has the intention to write to the memory line which will result in a memory history 202, which also means that the data of other cache lines in the memory block 114 will be written by other memory access agents. In this case, since the prefetching of the cache line between the core 102 and other memory access agents 101 may be affected, the mutually exclusive prefetching of these cache lines may be adversely affected. The flow goes to step 406 .

In step 406 , the update module 204 updates the prefetch property 132 to share in response to the snoop of step 404 . The process ends at step 406 .

Please refer to FIG. 5 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the memory access agent's access analysis to the memory block 114 in FIG. 1 . The flow starts at step 502 .

In step 502, the prefetch characteristics 132 of each memory bank 114 are initially set to shared, either because the default value is shared (as described above), or based on an initial memory bank 114 The prefetch property 132 of the memory block 114 is initialized to shared for fetching (eg, as described with respect to FIG. 6 or FIG. 10 ). The flow goes to step 504 .

In step 504, the hardware data prefetcher 122 keeps track (eg, recorded in the memory access history 202) of the number of cache lines in the memory bank 114 that have been written by the core 102 and detects that the number has exceeded a critical value. This may indicate that data for other cache lines in the memory bank 114 will be written by the core 102 , and the reason why exclusive prefetching of these memory lines would be adversely affected in this case is as follows. The threshold value can be a predetermined value, programmed by system software, or dynamically updated by the hardware data prefetcher 122 according to the performance analysis of prefetch execution. In one embodiment, the threshold value is 1, that is, the prefetch property 132 is updated to exclusive based on the first write to the memory block 114 . The flow goes to step 506 .

In step 506 , the update module 204 updates the prefetch property 132 to be exclusive in response to the threshold being exceeded in step 504 . The flow ends at step 506 .

Please refer to FIG. 6 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the memory access agent 101 performing access analysis on the memory block 114 in FIG. 1 . The flow starts at step 602.

In step 602 , the update module 204 detects an initial access by the core 102 to the memory block 114 . The process proceeds to step 604 .

In decision step 604, the update module 204 determines whether the initial access is an instruction fetch or a load/store. If it is command fetching, the process goes to step 606 , otherwise, goes to step 608 .

In step 606, the update module 204 updates the prefetch property 132 to share in response to determining that the initial access is an instruction fetch in step 604, which is beneficial because when an instruction fetch is performed on a memory block 114 , the remaining accesses to the memory block 114 may also be instruction fetches, and essentially the memory locations containing instructions are never written to once loaded into memory. In one embodiment, the hardware data prefetcher 122 continues to perform hardware prefetching from the memory bank 114 using the dynamically updated shared prefetch feature 132 at step 606, however, as in other embodiments described herein, When the hardware data prefetcher 122 monitors and analyzes accesses to memory blocks, the initial prefetch property 132 can be updated from shared to exclusive (and vice versa). The flow ends at step 606 .

In step 608 , update module 204 updates prefetch property 132 to exclusive in response to determining in step 604 that the initial access is a load/store. In one embodiment, the hardware data prefetcher 122 continues to perform hardware prefetching from the memory bank 114 using the dynamically updated exclusive prefetch attribute 132 at step 608, however, as in other embodiments described herein , when the hardware data prefetcher 122 monitors and analyzes accesses to memory blocks, the initial prefetch property 132 can be updated from exclusive to shared (and vice versa). The process ends at step 608 .

Please refer to FIG. 7 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the memory access agent 101 performing access analysis on the memory block 114 in FIG. 1 . The flow starts at step 702 .

In step 702, the update module 204 maintains the count of instructions fetched by the core 102 from the memory block 114 (for example, recorded in the memory access history 202), represented by fetch_cnt, and the instruction count value from the memory block 114 The program loads/stores the count value and is represented by load_store_cnt. The process proceeds to step 704 .

In decision step 704, update module 204 determines whether fetch_cnt is greater than load_store_cnt. If yes, the flow goes to step 706 , otherwise the flow goes to step 708 .

In step 706, the update module 204 updates the prefetch property 132 to share in response to the determination in step 704 that fetch_cnt is greater than load_store_cnt. The flow goes to step 706 .

In step 708, the update module 204 judges whether the fetch_cnt is smaller than load_store_cnt, if yes, the process proceeds to step 712, otherwise, the process ends.

In step 712, the update module 204 updates the prefetch property 132 to exclusive in response to the determination in step 708 that fetch_cnt is less than load_store_cnt. The flow ends at step 712 .

Please refer to FIG. 8 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the memory access broker 101 performing access analysis on the memory block 114 in FIG. 1 . The flow starts at step 802 .

In step 802, the hardware data prefetcher 122 maintains a count of instructions fetched by a core 102 from the memory block 114 (for example, recorded in the memory access history 202), represented by fetch_cnt, and from the memory block The program load/store count value from 114 is represented by load_store_cnt. The process proceeds to step 804 .

In decision step 804, the update module 204 determines whether the difference between fetch_cnt and load_store_cnt is greater than a threshold. If yes, the flow goes to step 806 , otherwise the flow goes to step 808 . The threshold value can be a predetermined value, programmed by system software, or dynamically updated by the hardware data prefetcher 122 according to the performance analysis of prefetch execution.

In step 806 , the update module 204 updates the prefetch property 132 to share in response to the determination in step 804 that the difference between fetch_cnt and load_store_cnt is greater than the threshold. The flow goes to step 806.

In decision step 808, the update module 204 determines whether the difference between load_store_cnt and fetch_cnt is greater than a threshold. If yes, the flow goes to step 812, otherwise the flow ends. The threshold value at step 808 may be the same as or different from the threshold value used at step 804 .

In step 812 , the update module 204 updates the prefetch property 132 to exclusive in response to the determination in step 808 that the difference between load_store_cnt and fetch_cnt is greater than the threshold. The process ends at step 812.

Please refer to FIG. 9 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the memory access agent 101 performing access analysis on the memory block 114 in FIG. 1 . The flow starts at step 902 .

In step 902, the hardware data prefetcher 122 maintains a count of instructions fetched by a core 102 from the memory block 114 (for example, recorded in the memory access history 202), represented by fetch_cnt, and from the memory block The program load/store count value from 114 is represented by load_store_cnt. The process proceeds to step 904 .

In decision step 904, the update module 204 determines whether the difference between fetch_cnt and load_store_cnt is greater than a threshold. If yes, the flow goes to step 906 , otherwise the flow goes to step 908 .

In step 906 , the update module 204 updates the prefetch property 132 to share in response to the determination in step 904 that the difference between fetch_cnt and load_store_cnt is greater than the threshold. The process ends at step 906.

In decision step 908, the update module 204 determines whether the difference between fetch_cnt and load_store_cn is less than a threshold. If yes, the flow goes to step 912, otherwise the flow ends. The threshold value at step 908 may be the same as or different from the threshold value used at step 904.

In step 912 , the update module 204 updates the prefetch property 132 to exclusive in response to the determination in step 908 that the difference between fetch_cnt and load_store_cnt is less than the threshold. The flow ends at step 912.

Please refer to FIG. 10 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the memory access agent 101 performing access analysis on the memory block 114 in FIG. 1 . The process starts at step 1002.

In step 1002 , the update module 204 detects an initial access by the core 102 to the memory block 114 . The flow goes to step 1004.

In decision step 1004, the update module 204 determines whether the initial access is a load or a store. If it is loaded, the process goes to step 1006, otherwise goes to step 1008. In this context, a load access includes a fetch of a program instruction and a load performed by the program load instruction.

In step 1006, the update module 204 updates the prefetch characteristic 132 to share in response to determining that the initial access is a load in step 1004. In one embodiment, the hardware data prefetcher 122 continues to use the dynamically updated Shared prefetch feature 132 is used to perform hardware prefetch from memory bank 114. However, as in other embodiments described in the specification, when hardware data prefetcher 122 monitors and analyzes memory bank accesses, the initial The prefetch property 132 can be updated from shared to exclusive (and vice versa). The flow goes to step 1006 .

In step 1008 , the update module 204 updates the prefetch property 132 to be exclusive in response to determining that the initial access is a store in step 1004 . This is beneficial because when a store is performed to one slave memory bank 114, the remaining accesses to the memory bank 114 may also be stores. In one embodiment, the hardware data prefetcher 122 continues to perform hardware prefetching from the memory bank 114 using the dynamically updated exclusive prefetch property 132 at step 1008, however, as in other embodiments described herein , when the hardware data prefetcher 122 monitors and analyzes accesses to memory blocks, the initial prefetch property 132 can be updated from exclusive to shared (and vice versa). The process ends at step 1008.

Please refer to FIG. 11 , which depicts an operation flowchart of dynamically updating the prefetch characteristic 132 according to the memory access agent 101 performing access analysis on the memory block 114 in FIG. 1 . The flow starts at step 1102 .

In step 1102, the hardware data prefetcher 122 maintains the load count value (for example, recorded in the memory access history 202) of a core 102 from the memory block 114, represented by load_cnt, and from the memory block 114 The coming program stores the count value and is represented by store_cnt. The process proceeds to step 1104 .

In decision step 1104, the update module 204 determines whether the ratio of load_cnt to store_cnt is greater than a threshold. If yes, the flow goes to step 1106 , otherwise the flow goes to step 1108 . The threshold value can be a predetermined value, programmed by system software, or dynamically updated by the hardware data prefetcher 122 according to the prefetch performance analysis.

In step 1106 , the update module 204 updates the prefetch property 132 to share in response to the determination in step 1104 that the ratio of load_cnt to store_cnt is greater than the threshold. The process ends at step 1106.

In decision step 1108, the update module 204 determines whether the ratio of store_cnt to load_cnt is greater than a threshold. If yes, the flow goes to step 1112, otherwise the flow ends. The threshold value at step 1108 may be the same as or different from the threshold value used at step 1104 .

In step 1112 , the update module 204 updates the prefetch property 132 to be exclusive in response to determining in step 1008 that the ratio of store_cnt to load_cnt is greater than the threshold. The process ends at step 1112.

Please refer to FIG. 12 , which depicts an operational flowchart of using off-line program analysis to determine prefetch characteristics to perform hardware prefetch. The flow starts at step 1202.

In step 1202, a program is analyzed to determine that hardware prefetching performs better when the processors are performing shared prefetching or exclusive prefetching. The analysis is performed on a number of different programs of interest (eg, programs that are frequently executed, or programs that are known to generally take a long time to execute, so their execution performance is important and needs to be optimized). Preferably, when the processor uses the shared prefetch feature to perform hardware prefetch, the program will be executed many times, and when the processor uses the exclusive prefetch feature to perform hardware prefetch, the program will be executed many times, Its implementation results will be recorded, for example, for each shared or mutually exclusive configuration, the average value of multiple execution results will be calculated. In another embodiment, the analysis will use common experimental values when multiple systems communicate with a server, where the server provides the desired configuration when the system uses a configuration information and dynamically determines the improved configuration of the system Information and performance data. Such implementations are for example U.S. Patent Nos. 14/474,623 and 14/474,699 filed September 2, 2014, both of which refer to U.S. Patent No. 62/000,808 filed May 20, 2014. Provisional Applications claim priority, and all of them are hereby incorporated by reference. In this example, dynamic system configuration includes dynamic updates to prefetch characteristics 132 . The flow goes to step 1204 .

In step 1204, a table with an entry for each program is compiled. Preferably, each entry includes the identification properties of the program and the prefetching properties that provide the best performance in step 1202 . The identifying characteristics may include a program name (eg, known to the operating system), memory access patterns, and/or the number of different instruction types used by the program. The table may also contain system software, such as device drivers, that was last executed on the processor 103 . The flow goes to step 1206 .

In step 1206 , the programs in the table are checked to see if they are being executed in the processor 103 . In one embodiment, the system software detects that the program is running. For example, the operating system can query the program name of the running program, just as the operating system queries the name of each program in its execution table. In another embodiment, the table is downloaded to the processor 103 by the operating system during boot time, and the processor 103 detects that the program is being executed. For example, the processor 103 can collect identification characteristics related to the program (such as memory configuration and/or the number of different instruction types used by the program) when the program is executed, and compare the identification characteristics with the items of the table compiled in step 1204 Compare and download to processor 103. The flow goes to step 1208 .

In step 1208, the hardware data prefetcher 122 performs hardware prefetching on the program measured in step 1206 using the prefetching characteristics associated with the measured program in the table entry. The process ends at step 1208.

Please refer to FIG. 13 , which depicts a block diagram of a plurality of range registers 1300 . The range register 1300 is included in the hardware data prefetcher 122 . In one embodiment, the hardware data prefetcher 122 includes a set of range registers 1300 associated with each core 102 , and each range register 1300 includes an address range field 1302 and a prefetch characteristic field 1304 . Each address range field 1302 can be programmed to indicate an address range within the address space of the processor 103 . Prefetch property 1304 indicates a prefetch property, either shared or exclusive. If the prefetch module 206 prefetches the data address predicted by the hardware, the prefetch module 206 judges whether the prefetch address is located in the address range of the indicated range register 1300. If correct, the prefetch module 206 generates the prefetch request 208 according to the prefetch characteristics indicated in the relevant prefetch characteristic field 1304; The prefetch request 208 is generated by fetching properties. In one embodiment, the default prefetch feature is shared, so the range register 1300 only needs to be used to indicate the address range required for exclusive hardware prefetch. In another embodiment, the preset prefetch feature is mutually exclusive, so the range register 1300 only needs to be used to indicate the address range required for shared hardware prefetch. In these embodiments, the prefetch characteristic field 1304 may not be required since it implies that the indicated prefetch characteristic is contrary to the preset prefetch characteristic.

Please refer to FIG. 14 , which depicts an operation flowchart of performing hardware prefetching using the prefetching characteristics determined by the range register 1300 of FIG. 13 . The flow starts at step 1402 .

In step 1402, a program is analyzed to determine which of the different programs have better execution performance when executed on the processor 103 when the processor uses the shared prefetch feature or the exclusive prefetch feature to perform hardware prefetch , which is similar to that described above in FIG. 12 , however the analysis performed at step 1402 includes a finer granularity than the analysis performed at step 1202 . More specifically, the analysis includes evaluating the implementation effectiveness of each program with the shared or exclusive prefetching feature relative to the address range programmed into the address register 1300 . For example, address ranges containing data accessed by multiple memory access agents 101 can be efficiently included in the table by sharing the prefetch feature; conversely, addresses containing data written by a single core 102 Ranges can be efficiently contained in tables via the exclusive prefetch feature. The flow goes to step 1404 .

In step 1404 , a table with one entry per program is compiled in a manner similar to that described for step 1204 . However, the table compiled at step 1404 contains address ranges and associated prefetch properties to be pushed into the range register 1300 . The flow goes to step 1406 .

In step 1406 , the programs in the table are checked to see if they are being executed on processor 103 , in a manner similar to that described in step 1206 . However, when a program is detected to be executing, the scope register 1300 is additionally programmed using information about the program in the table entry. In one embodiment, the range register 1300 is programmed by the operating system. In another embodiment, the processor 103 will itself program the range register 1300 in response to detecting execution of the program, for example, the microcode of the processor 103 can program the range register 1300 . The flow goes to step 1408 .

In step 1408 , the hardware data prefetcher 122 performs hardware prefetching on the program detected in step 1406 by using the prefetch feature of the range register 1300 in combination with the preset prefetch feature. The process ends at step 1408 .

Although many different embodiments of the dynamically updated prefetch feature 132 have been described above, other embodiments are also contemplated in the present invention without departing from the spirit of the present invention. For example, in one embodiment, each active The memory block 114 maintains a saturation count. When one of the memory access brokers 101 accesses the memory block 114 and intends to benefit from exclusive hardware prefetching (such as a store or load/store), the update module 204 increments the count value in a saturated manner; Conversely, when one of the memory access agents 101 makes an access to the memory block 114 and intends to benefit from a shared hardware prefetch (such as a load or instruction fetch), the update module 204 decrements the counter value in a saturated manner . Preferably, the prefetch feature 132 is the most significant bit of the saturation count value. For example, the update module 204 maintains a queue (such as a shift register) for storing the latest N Accessed information (eg store, load/store, instruction fetch), where N is greater than 1. The update module 204 dynamically updates the prefetch property 132 to be exclusive or shared based on information stored in the queue and wishing to benefit from exclusive or shared hardware prefetching. For example, if most of the last N accesses are stores, the update is exclusive, whereas if most of the last N accesses are fetches, the update is shared. In another example, for each hardware prefetch performed by prefetch module 206 from memory bank 114 , update module 204 maintains an indication of the prefetch characteristic 132 used. For each access that occurs on a prefetch cache line, if the memory access agent 101 that is doing the access writes to the cache line associated with the indication, the update module 204 will update the indication as an interactive If the cache line is snooped, the update module 204 updates the indication as shared. In this way, a cache line bitmap (bitmap) in memory bank 114 will be maintained to indicate the closest optimal prefetch characteristics that may be used for different cache lines in memory bank 114 Information. The update module 204 searches the pattern in the bitmap and determines whether the address of the next cache line is a hardware prefetch hit pattern, and uses the bitmap to dynamically determine whether the prefetch feature 132 is available for hardware prefetch Take that cache line. Finally, although an embodiment of a hardware data prefetcher included in a multi-core processor has been disclosed herein, other embodiments of a hardware data prefetcher included in a single core are within the scope of the invention.

The present invention has been described herein through various embodiments, and the above-mentioned embodiments should be understood as examples of the present invention and should not limit the present invention in any way. It should be obvious to those skilled in the art that any change or modification in form or detail can be made without departing from the spirit and scope of the present invention. For example, software may be used to implement, function, manufacture, model, simulate, describe and/or test the devices and methods as described herein. The above can be realized by using general programming languages (such as C, C++), hardware description languages (HDL) including Verilog HDL, VHDL, etc., or other available programs. The above software can be installed on any known computer-usable medium, such as magnetic tape, semiconductor, magnetic disk or optical disk (such as CD-ROM, DVD-ROM, etc.), a network, wired or wireless or other communication medium. Various embodiments of the apparatus and methods described herein may include a semiconductor intellectual property core, such as a processor core (implemented or specified, for example, by HDL) and converted to hardware by integrated circuit fabrication. In addition, the devices and methods described herein may be implemented by a combination of hardware and software. Therefore, the scope of the present invention should not be limited by any exemplary embodiments herein, but only by the scope of the claims of the present invention and their equivalents. It should be particularly noted that the present invention can be implemented in a processor device which can be used in a general computer. Finally, those skilled in the art should understand that based on the concepts and embodiments disclosed herein, any application that designs or modifies other structures to achieve the same purpose as the present invention is included in the scope of the present invention and is defined in the present invention within the scope of the claims.

Claims (21)

1. A processor, characterized in that it comprises: One core for: loading a first table for indicating a prefetch characteristic for a predetermined program, wherein the prefetch characteristic is exclusive or shared; detecting whether the predetermined program is executing on the processor from a second table for identifying the processing being executed; and query the prefetch characteristics associated with the scheduled program being executed on the processor; and a hardware data prefetcher performing hardware prefetching to the predetermined program using the prefetch feature, Wherein, the hardware data prefetcher analyzes memory accesses by the core that occur simultaneously with the hardware prefetch, and dynamically updates the prefetch characteristic according to the analysis. 2. The processor of claim 1, wherein the prefetch feature is confirmed before detecting whether the predetermined program is executing on the processor. 3. The processor according to claim 2, wherein the step of confirming the prefetching characteristic before detecting whether the predetermined program is being executed on the processor comprises: When the processor executes the predetermined program when using a shared prefetch feature to perform hardware prefetch, determine a first execution result; determining a second execution result under the condition that the predetermined program is executed when the processor executes hardware prefetching using a mutually exclusive prefetching feature; and When the first performance is better than the second execution performance, select the prefetching characteristic as shared, and when the second execution performance is better than the first execution performance, select the prefetching characteristic as exclusive. 4. The processor according to claim 1, wherein an operating system executing on the processor detects whether the identification code of the predetermined program exists in the executing program table of the operating system to detect Test whether the scheduled program is executing on the processor. 5. The processor of claim 4, wherein the processor receives the prefetch characteristic from the operating system. 6. The processor according to claim 1, wherein the processor is also used for: receiving information indicative of at least one identifying characteristic of the predetermined program and associated prefetch characteristics prior to detecting whether the predetermined program is executing on the processor; Wherein the processor compares at least one identification characteristic of the predetermined program in the received information with the identification characteristic determined when the predetermined program is executed, to detect whether the predetermined program is executing on the processor; and Wherein the hardware data prefetcher performs hardware prefetching on the predetermined program by using the prefetching characteristic in the received information related to the compared at least one identification characteristic, to use the prefetching characteristic to perform hardware prefetching on the predetermined program. Prefetching. 7. The processor of claim 1, wherein the first table is included in a device driver. 8. A method for performing hardware data prefetching by a processor, characterized in that the method comprises: loading a first table for indicating a prefetch characteristic for a predetermined program, wherein the prefetch characteristic is exclusive or shared; detecting whether the predetermined program is executing on the processor from a second table for identifying the processing being executed; query the prefetch characteristics associated with the scheduled program being executed on the processor; performing hardware prefetching of the predetermined program using the prefetching feature; and Memory accesses occurring concurrently with the hardware prefetch are analyzed, and the prefetch characteristics are dynamically updated based on the analysis. 9. The method for performing hardware data prefetching by a processor according to claim 8, wherein the prefetch feature is confirmed before detecting whether the predetermined program is being executed on the processor. 10. The method for performing hardware data prefetching by a processor according to claim 9, wherein the step of confirming the prefetching characteristics before detecting whether the predetermined program is being executed on the processor comprises: When the processor executes the predetermined program when using a shared prefetch feature to perform hardware prefetch, determine a first execution result; determining a second execution result under the condition that the predetermined program is executed when the processor executes hardware prefetching using a mutually exclusive prefetching feature; and When the first performance is better than the second execution performance, select the prefetching characteristic as shared, and when the second execution performance is better than the first execution performance, select the prefetching characteristic as exclusive. 11. The method for performing hardware data prefetching by a processor according to claim 8, wherein an operating system executing on the processor detects whether the identification code of the predetermined program exists in the operating system Executing program table to detect whether the predetermined program is being executed on the processor. 12. The method for performing hardware data prefetching by a processor according to claim 11, further comprising: The step of providing, by the operating system, the prefetch feature to the processor in response to detecting that the predetermined program is executing on the processor. 13. The method for performing hardware data prefetching by a processor according to claim 8, further comprising: receiving, by the processor, information indicative of at least one identifying characteristic of the predetermined program and an associated prefetch characteristic prior to detecting whether the predetermined program is executing on the processor; Wherein the step of detecting whether the predetermined program is executing on the processor includes: comparing at least one identification characteristic of the predetermined program in the received information with an identification characteristic determined when the predetermined program is executed; and The step of performing hardware prefetching on the predetermined program by using the prefetching characteristic includes: performing hardware prefetching on the predetermined program by using the prefetching characteristic in the received information related to the compared at least one identification characteristic . 14. A processor, characterized in that it comprises: One core for: detecting whether a predetermined program is executing on the processor; and In response to detecting that the predetermined program is being executed on the processor, loading the respective address ranges of the one or more range registers to the processor's one or more range registers, wherein one or more of the range registers each of the address ranges has an associated prefetch characteristic, the prefetch characteristic being exclusive or shared; and a hardware data prefetcher for performing hardware prefetching of the predetermined program using the prefetch characteristic relative to the address range loaded into the range register, Wherein, the hardware data prefetcher analyzes memory accesses by the core that occur simultaneously with the hardware prefetch, and dynamically updates the prefetch characteristic according to the analysis. 15. The processor according to claim 14, wherein the performing hardware prefetching of the predetermined program using the prefetching characteristic related to the address range loaded into the range register comprises: Predict the data addresses that may be used by the scheduled program in the future; judging whether the data address falls in one of the one or more address ranges; performing a hardware prefetch of data at the data address using the prefetch characteristic associated with the one of the one or more address ranges when the data address falls within the one of the one or more address ranges take; and When the data address does not fall in the one of the one or more address ranges, performing hardware prefetching of the data on the data address using a preset prefetch characteristic. 16. The processor of claim 15, wherein the prefetch characteristic associated with the one of the one or more address ranges implies the opposite of the preset prefetch characteristic. 17. The processor of claim 15, wherein the prefetch characteristic associated with the one of the one or more address ranges is maintained at the one of the one or more address ranges maintained address register. 18. A method for performing hardware data prefetching by a processor, characterized in that the method comprises: detecting whether a predetermined program is executing on the processor; In response to detecting that the predetermined program is being executed on the processor, loading the respective address ranges of the one or more range registers to the processor's one or more range registers, wherein one or more of the range registers each of the address ranges has an associated prefetch characteristic, the prefetch characteristic being exclusive or shared; and A hardware prefetch is performed on the predetermined program using the prefetch property associated with the address range loaded into the range register. 19. The method for performing hardware data prefetching by a processor according to claim 18, wherein the hardware prefetching is performed on the predetermined program using the prefetch characteristic related to the address range loaded into the range register The steps taken include: Predict the data addresses that may be used by the scheduled program in the future; judging whether the data address falls in one of the one or more address ranges; performing a hardware prefetch of data at the data address using the prefetch characteristic associated with the one of the one or more address ranges when the data address falls within the one of the one or more address ranges take; and When the data address does not fall in the one of the one or more address ranges, performing hardware prefetching of the data on the data address using a preset prefetch characteristic. 20. The method of performing hardware data prefetching by a processor according to claim 19, wherein the prefetch characteristic associated with the one of the one or more address ranges implies that the preset prefetch The characteristics are opposite. 21. The method of performing hardware data prefetching by a processor according to claim 19, wherein the prefetch characteristic associated with the one of the one or more address ranges is maintained to maintain the one or more address ranges address register in one of the address ranges.