CN105347289A - Enclosing structure suitable for chip scale package and manufacturing method thereof - Google Patents
Enclosing structure suitable for chip scale package and manufacturing method thereof Download PDFInfo
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- CN105347289A CN105347289A CN201510650210.XA CN201510650210A CN105347289A CN 105347289 A CN105347289 A CN 105347289A CN 201510650210 A CN201510650210 A CN 201510650210A CN 105347289 A CN105347289 A CN 105347289A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C3/00—Assembling of devices or systems from individually processed components
- B81C3/001—Bonding of two components
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Abstract
The invention discloses an enclosing structure suitable for chip scale package. A substrate chip unit is provided with annular sealing bumps for encircling semiconductor devices; a package substrate is also provided with annular sealing welding pads or sealing bumps which correspond to the sealing bumps on the substrate chip unit; the substrate chip unit is inversely arranged on the package substrate; the sealing bumps on the substrate chip unit are connected integrally with the sealing welding pads or the sealing bumps on the package substrate by welding; and enclosing structures are formed on the peripheries of the semiconductor devices. Compared with an existing enclosing structure adopting a wafer-level packaging technology, the enclosing structure disclosed by the invention is implemented through a chip scale package technology, and wafer etching, wafer bonding and a through silicon via technologies are omitted, so that the process cost is lowered remarkably, and the process period is shortened.
Description
Technical field
The application relates to a kind of wafer-level package technology of semiconductor devices.
Background technology
MEMS (MEMS) is a kind of industrial technology microelectronics and mechanical engineering merged.MEMS (device) size, usually between 20 microns to 1 millimeter, is made up of the assembly of size usually between 1 to 100 microns (component).MEMS generally includes the center cell (such as microprocessor, microprocessor) of process data and multiple with the interactional assembly of external environment (such as microsensor, microsensor).MEMS has the feature of microminiaturization, intellectuality, multi-functional, high integration, and common application comprises accelerometer (accelerometer), gyroscope (gyroscope), microphone, pressure sensor, wave filter etc.
MEMS manufacturing process grows up on the basis of semiconductor fabrication process, comprises the technology such as deposit, thermal oxide, photoetching, etching, deep electroforming model (LIGA), silicon micromachined, non-silicon micromachined and precision optical machinery processing.Described deposition technology comprises chemical vapor deposition (CVD) and physical vapor deposition (PVD).Described photoetching technique comprises electron beam exposure (Electronbeamlithography), ion beam exposure (Ionbeamlithography), Ion track (Iontrack), X-ray lithography (X-raylithography), diamond graphical (Diamondpatterning) etc.Described lithographic technique comprises dry etching and wet etching.
One wafer (wafer also claims silicon chip) can manufacture multiple semiconductor devices simultaneously, usually just enters through test and selection and assemble and encapsulated phase after these devices have manufactured on wafer.Emerging wafer-level packaging (WLP, wafer-levelpackaging) technology first encapsulates on whole wafer, again packaged chip (chip) is obtained to packaged wafer cutting, and packaged chip is consistent dimensionally with nude film (die).Wafer-level packaging meets the definition of chip size packages (CSP, chipscalepackage) usually, therefore also referred to as crystal wafer chip dimension encapsulation (WLCSP).Traditional encapsulation technology is then that first cutting crystal wafer obtains nude film, then carries out encapsulation to nude film and obtain packaged chip.In order to corresponding with Wafer level packaging, traditional encapsulation technology can be described as wafer-level package.Because MEMS is easily destroyed, adopt Wafer level packaging more suitable, but also can adopt wafer-level package technology.
For protection object, most of MEMS and part IC (integrated circuit) device need to be arranged in closed structure.Refer to Fig. 1, this is a kind of existing closed structure for carrying out wafer-level packaging to semiconductor devices.Substrate wafer (devicewafer) 1 has multiple semiconductor devices 2, and described semiconductor devices 2 comprises MEMS and the IC device except MEMS.The periphery of each semiconductor devices 2 forms annular sidewall by bonding material 5 and the protruding 4a of protection.Wafer (capwafer) 3 of blocking a shot carries out wafer bonding with substrate wafer 1.Base chip unit 1a and block chip unit 3a is obtained respectively after cutting substrate wafer 1, block wafer 3.Base chip unit 1a, bonding material 5 and protect protruding 4a, block chip unit 3a just constitutes the closed structure protecting each semiconductor devices 2.Preferably, described closed structure has air-tightness, and inside can be vacuum or blanketing gas.The input and output weld pad of each semiconductor devices 2 is externally drawn out to the weld pad projection 7 outside block chip unit 3a by the contact hole electrode 6 of bonding material 5 and connection bump 4b inside, then is drawn out to weld pad on base plate for packaging 8 or weld pad projection 9 further by metal wire 11.Substrate package unit 8a is obtained after cutting base plate for packaging 8.
In this document, weld pad refers to the electric connection point not protruding wafer or substrate surface, not illustrated in FIG. or only represent position at section.Weld pad projection then refers to the electric connection point protruding from wafer or substrate surface, in profile, have diagram.
The manufacture method of the above-mentioned closed structure for wafer-level packaging comprises each step following:
1st step, refers to Fig. 1 a, and substrate wafer 1 has manufactured semiconductor devices 2, and semiconductor devices 2 has input and output weld pad on substrate wafer 1.
2nd step, refers to Fig. 1 b, adopts photoetching and etching technics to etch block wafer 3, and block wafer 3 remains the protruding 4a and connection bump 4b of protection of silicon materials.Protect protruding 4a in the form of a ring, form a cavity in the protruding 4a inside of protection.This cavity correspondence is enclosed in the periphery of each semiconductor devices 2, and in the weld pad of each semiconductor devices 2 is enclosed in.Connection bump 4b corresponds to the bond pad locations of each semiconductor devices 2.
3rd step, refers to Fig. 1 c, adopts wafer bonding (waferbonding) technique that inverted block wafer 3 is connected as a single entity with the substrate wafer 1 just put.Wherein, protect protruding 4a and bonding material 5 to be connected as a single entity and form annular sidewall in the periphery of each semiconductor devices 2, this annular sidewall and two wafer together form the closed structure of each semiconductor devices 2 periphery.The weld pad of connection bump 4b and each semiconductor devices 2 is connected as a single entity.As required closed structure can be evacuated during wafer bonding, or blanketing gas.Bonding material 5 is such as glass, metal (being now eutectic bonding), high-molecular organic material etc., also can omit bonding material 5 (being now Direct Bonding, directbongding).
4th step, refers to Fig. 1 d, adopts photoetching and etching technics at the position etching through hole of the connection bump 4b of block wafer 3.If the bonding material at connection bump 4b place 5 is conductive material, then via bottoms is at the upper surface of bonding material 5 or more lower position.If the bonding material at connection bump 4b place 5 is insulating materials, then via bottoms is on the weld pad of semiconductor devices 2.Then form contact hole electrode 6 in through-holes, such as, adopt tungsten plug.Form electricity between contact hole electrode 6 and the weld pad of semiconductor devices 2 to be connected.
5th step, refers to Fig. 1 e, adopts metallization process (wafer 3 of now blocking a shot is be inverted) above block wafer 3 to form the weld pad projection 7 with contact hole electrode 6 with electric connection.
6th step, refers to Fig. 1 f, cuts to obtain each semiconductor device chip to substrate wafer 1 and block wafer 3, and every chips comprises the base chip unit 1a and block chip unit 3a that are connected as a single entity.
7th step, refers to Fig. 1 g, base plate for packaging 8 has weld pad or weld pad projection 9, adopts adhesive 10 to be adhered on base plate for packaging 8 bottom surface of base chip unit 1a.Adhesive 10 is such as epoxy resin, metal (being now eutectic weldering), glass solder etc.
8th step, refers to Fig. 1 h, adopts metal wire 11 to connect the weld pad protruding 7 on block chip unit 3a and the weld pad on base plate for packaging 8 or weld pad projection 9.Such as adopt lead key closing process, comprise thermocompression bonding, ultrasonic bond, Thermosonic-bonding etc.
9th step, refers to Fig. 1, adopts encapsulating material 12 to be encapsulated by each several part on base plate for packaging 8, and then cuts to obtain each packaged semiconductor device chip to base plate for packaging 8.Base plate for packaging 8 obtains substrate package unit 8a after cutting.Conventional encapsulating material 12 comprises plastics, pottery etc.
The above-mentioned closed structure for wafer-level packaging and manufacture method thereof are the airtight protections that the mode of employing two panels wafer bonding realizes to semiconductor devices; and also needed to etch to form cavity on block wafer before wafer bonding; adopt silicon through hole (TSV, ThroughSiliconVia) means to be extracted by the input and output weld pad of semiconductor devices simultaneously.Be wafer etching, wafer bonding, silicon through hole technology, wire bonding be all faced with that cost is high, the problem of process cycle length consuming time.Some MEMS and/or IC device are limited to above-mentioned technology, are also faced with low, the bulky problem of yields.
Except the above-mentioned closed structure for wafer-level packaging and manufacture method thereof, some technical literatures are also had to disclose other closed structures for wafer-level packaging and manufacture method thereof.
The Chinese invention patent application that publication number is CN1463911A, publication date is on December 31st, 2003 discloses a kind of chips level packaging apparatus of microcomputer electric component, and provides two embodiments.In a first embodiment, described packaging system comprises microcomputer electric component wafer and encapsulation wafer, and microcomputer electric component is produced on microcomputer electric component wafer.Microcomputer electric component wafer is arranged with multiple wafer (i.e. chip) unit, the input and output weld pad of wafer cell arranges the first solder projection, annular solder projection is set in wafer cell periphery as the first protection ring.Encapsulation wafer runs through multiple metal guide scapus is set, the second solder projection is all set at metal guide scapus two ends, at encapsulation crystal column surface, annular solder projection is set as the second protection ring.By the first solder projection, the first protection ring respectively corresponding bonding be arranged on the second solder projection, the second protection ring.Finally, microcomputer electric component is arranged in by two pieces of wafers as two bottom surfaces, by the first protection ring and the second protection ring closed structure as sidewall.The input and output weld pad of microcomputer electric component is drawn out to outside encapsulation wafer by the first solder projection, the second solder projection and metal guide scapus.In a second embodiment, described packaging system comprises substrate and encapsulation wafer, and microcomputer electric component is produced on encapsulation wafer, and all the other are identical with the first embodiment.The document is formed the closed structure of wafer-level packaging together with two wafer with the solder projection of metal material, technique is comparatively complicated and cost is higher, also needs to use silicon through hole technology and goes between.
The Chinese invention patent application that publication number is CN101123231A, publication date is on February 13rd, 2008 discloses a kind of wafer level chip scale package structure and manufacture method of MEMS, and provides two embodiments.In a first embodiment, described encapsulating structure comprises MEMS wafer and protection enclosing cover.MEMS wafer is manufactured with MEMS, and is provided with weld pad.Cavity wall is formed by benzocyclobutene (BCB) by photoetching process outer the covering of protection.Cavity wall is pressed together on weld pad, and MEMS is arranged in by two pieces of wafers as two bottom surfaces, by cavity wall and the weld pad closed structure as sidewall.With the outer lead of weld pad contacts side surfaces, the input and output weld pad of MEMS is drawn out to outside MEMS wafer.In a second embodiment, form cavity wall by glass cement by silk-screen printing technique outer the covering of protection, all the other are identical with the first embodiment.The document is formed the closed structure of wafer-level packaging together with two wafer with the cavity wall of macromolecular material, and pin configuration is comparatively complicated, and processing step is more and cost is higher.
The Chinese invention patent application that publication number is CN101533832A, publication date is on September 16th, 2009 discloses integrated chip and the integrated approach of a kind of mems device and integrated circuit.Described integrated chip comprises: the mems device generated on the first substrate, the first packaging ring generated around mems device, the integrated circuit corresponding with mems device that the second substrate generates, to generate and merge with the first packaging ring the second packaging ring docked around integrated circuit.Finally, mems device is arranged in by two pieces of substrates as two bottom surfaces, by the first packaging ring and the second packaging ring closed structure as sidewall together with integrated circuit.Be formed with necessary electricity between mems device and integrated circuit to connect, external electricity connects then is drawn by the through hole of the first substrate or the second substrate.The document is also the closed structure being formed wafer-level packaging with the packaging ring of metal material together with two wafer, and technique is comparatively complicated and cost is higher, also needs to use silicon through hole technology and goes between.
Summary of the invention
From recording above, existing scheme all adopts Wafer level packaging, and adopts wafer bonding mode, forms the closed structure of protection semiconductor devices using metal material or macromolecular material as bonding material.Described closed structure is all using two wafer as two bottom surfaces, using metal material or macromolecular material as sidewall, its manufacturing cost is higher, technique is more complicated.Technical problems to be solved in this application provide a kind of closed structure that can be used for semiconductor devices, no longer adopt Wafer level packaging, and use wafer-level package technology instead, and reduce process costs by special structural design, reduce processing step, the lead-in wire scheme being easy to realize is provided simultaneously.
For solving the problems of the technologies described above, the closed structure that the application is applicable to wafer-level package is that the seal convexity on base chip unit with annular surrounds semiconductor devices, base plate for packaging also has the sealing weld pad of annular or seal convexity and corresponds to seal convexity on base chip unit; By the upside-down mounting of base chip unit on base plate for packaging, the seal convexity on base chip unit is connected as a single entity by welding with the sealing weld pad on base plate for packaging or seal convexity, and forms a closed structure in the periphery of each semiconductor devices.
The manufacture method that the application is applicable to the closed structure of wafer-level package comprises the steps:
1st step, substrate wafer manufactures semiconductor devices, on substrate wafer, also grow weld pad projection and seal convexity; Formed between weld pad projection and the weld pad of semiconductor devices and be electrically connected; Seal convexity in the form of a ring, is enclosed in the periphery of semiconductor devices and weld pad projection;
2nd step, cutting substrate wafer obtains each base chip unit;
3rd step, base plate for packaging is arranged or growth weld pad or weld pad is protruding and multiple sealing weld pad or seal convexity; The position of the weld pad on base plate for packaging or weld pad projection corresponds to the position of the weld pad projection on each base chip unit; Sealing weld pad on base plate for packaging or seal convexity are also ring-type, and its position corresponds to the position of the seal convexity on each base chip unit;
4th step, by the upside-down mounting of base chip unit on base plate for packaging, the seal convexity on base chip unit projects through to weld with the sealing weld pad on base plate for packaging or weld pad and is connected as a single entity, thus constitutes the closed structure protecting each semiconductor devices; Weld pad projection on base chip unit also projects through to weld with the weld pad on base plate for packaging or weld pad and is connected as a single entity, and in this closed structure;
5th step, encapsulates, then cuts base plate for packaging and obtain packaged semiconductor devices.
Compared with the closed structure of existing employing Wafer level packaging, the closed structure of the application adopts wafer-level package technology to realize, and eliminates wafer etching, wafer bonding, silicon through hole technology, thus significantly reduces process costs, shorten process cycle.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the existing closed structure for wafer-level packaging.
Fig. 1 a to Fig. 1 h is each step schematic diagram of the manufacture method of the existing closed structure for wafer-level packaging.
Fig. 2 is the schematic diagram that the application is applicable to the embodiment one of the closed structure of wafer-level package.
Fig. 2 a to Fig. 2 d is each step schematic diagram of the embodiment one of the closed structure manufacture method of the application.
Fig. 3 is the schematic diagram that the application is applicable to the embodiment two of the closed structure of wafer-level package.
Fig. 3 a to Fig. 3 d is each step schematic diagram of the embodiment two of the closed structure manufacture method of the application.
Description of reference numerals in figure: 1 is substrate wafer; 1a is base chip unit; 2 is semiconductor devices; 3 is block wafer; 3a is block chip unit; 4a is protection projection; 4b is connection bump; 5 is bonding material; 6 is contact hole electrode; 6a is through hole; 7 is the weld pad projection on block wafer; 8 is base plate for packaging; 8a is substrate package unit; 9 is that weld pad on base plate for packaging or weld pad are protruding; 10 is adhesive; 11 is metal wire; 12 is encapsulating material; 13 is the weld pad projection on substrate wafer; 14 is the seal convexity on substrate wafer; 15 is that sealing weld pad on base plate for packaging or weld pad are protruding; 16 is solder.
Detailed description of the invention
Refer to Fig. 2, this is the embodiment one that the application is applicable to carry out semiconductor devices the closed structure of wafer-level package.Base chip unit 1a is cut by substrate wafer 1, and base chip unit 1a has a semiconductor devices 2, and described semiconductor devices 2 comprises MEMS and the IC device except MEMS.Base chip unit 1a has the weld pad projection 13 of metal material, also have annular seal convexity 14, weld pad projection 13 surround by the seal convexity 14 of annular.Base plate for packaging 8 has weld pad or the weld pad projection 9 of metal material, also have annular sealing weld pad or weld pad projection 15, weld pad or weld pad projection 9 by the sealing weld pad of annular or weld pad projection 15 surround.Base chip unit 1a upside-down mounting is on base plate for packaging 8, seal convexity 14 on base chip unit 1a is undertaken welding being connected as a single entity by solder 16 with the sealing weld pad on base plate for packaging 8 or weld pad projection 15, and forms a closed structure in the periphery of each semiconductor devices 2.This closed structure is made up of the seal convexity 14 on base chip unit 1a, substrate package unit 8a, base chip unit 1a, the seal convexity 15 on substrate package unit 8a and solder 15.Substrate package unit 8a is cut by base plate for packaging 8.Weld pad on base chip unit 1a protruding 13 is undertaken welding being connected as a single entity by solder 16 with the weld pad projection 9 on base plate for packaging 8, thus the weld pad of each semiconductor devices 2 is electrically connected weld pad on base plate for packaging 8 or weld pad projection 9 by weld pad projection 13, solder 16.Alternatively, solder 16 can omit.Preferably, described closed structure has air-tightness, and inside can be vacuum or blanketing gas.
The embodiment one that the application is applicable to the manufacture method of the closed structure of wafer-level package comprises each step following:
1st step, refers to Fig. 2 a, and substrate wafer 1 has manufactured multiple semiconductor devices 2, and semiconductor devices 2 has input and output weld pad on substrate wafer 1.Substrate wafer 1 grows weld pad protruding 13 and seal convexity 14, such as, be the materials such as gold, copper, scolding tin, can adopt sputtering and/or electroplating technology manufacture.Formed between weld pad protruding 13 and the weld pad of semiconductor devices 2 and be electrically connected, preferably weld pad projection 13 is on the weld pad of semiconductor devices 2.Seal convexity 14 in the form of a ring, is enclosed in the periphery of semiconductor devices 2 and weld pad projection 13.Preferably, seal convexity 14 is positioned at the outer rim one week of base chip unit 1a.
2nd step, refers to Fig. 2 b, cuts to obtain each base chip unit 1a to substrate wafer 1.Each base chip unit 1a has the seal convexity 14 of a semiconductor devices 2 and weld pad thereof, weld pad projection 13, ring-type.
3rd step, refers to Fig. 2 c, base plate for packaging 8 is arranged or growth weld pad or weld pad protruding 9 and multiple sealing weld pad or seal convexity 15, such as, be the materials such as gold, copper, scolding tin, can adopt and sputter and/or electroplating technology manufacture.The position of the weld pad on base plate for packaging 8 or weld pad projection 9 corresponds to the position of the weld pad projection 13 on each base chip unit 1a.Sealing weld pad on base plate for packaging 8 or seal convexity 15 are also ring-type, and its position corresponds to the position of the seal convexity 14 on each base chip unit 1a.
4th step; refer to Fig. 2 d; by base chip unit 1a upside-down mounting on base plate for packaging 8; seal convexity 14 on base chip unit 1a is undertaken welding being connected as a single entity by solder 16 with the sealing weld pad on base plate for packaging 8 or weld pad projection 15, thus constitutes the closed structure protecting each semiconductor devices 2.Weld pad on base chip unit 1a protruding 13 is also undertaken welding being connected as a single entity by solder 16 with the weld pad projection 9 on base plate for packaging 8, thus the weld pad of semiconductor devices 2 is electrically drawn out to weld pad or the weld pad projection 9 of base plate for packaging 8.Weld pad on base chip unit 1a protruding 13 and the weld pad projection 9 on base plate for packaging 8 are in this closed structure.Alternatively, solder 16 can be omitted during solder.
5th step, refers to Fig. 2, adopts encapsulating material 12 to be encapsulated by each several part on base plate for packaging 8, and then cuts to obtain packaged semiconductor devices to base plate for packaging 8.Base plate for packaging 8 obtains each substrate package unit 8a after cutting.Conventional encapsulating material 12 comprises plastics, pottery etc.
The embodiment one of the application provides a kind of novel closed structure for wafer-level package, using base chip unit as a bottom surface, using substrate package unit as another bottom surface, after welding using the seal convexity on base chip unit with the seal convexity on substrate package unit, (comprising solder alternatively) is as sidewall to form closed structure.First, this closed structure adopts wafer-level package technology to instead of Wafer level packaging, and thus eliminate wafer bonding, this can significantly reduce process costs and cycle.Secondly, this closed structure eliminates the thickness of another wafer (block wafer), therefore can reduce chip volume.Again, this closed structure mainly manufactures with welding procedure, and technique is simple and with low cost.Then, this closed structure eliminates wafer etching, silicon through hole technology, can improve the yields of Sensitive Apparatus.
Refer to Fig. 3, this is the embodiment two that the application is applicable to carry out semiconductor devices the closed structure of wafer-level package.Base chip unit 1a is cut by substrate wafer 1, and base chip unit 1a has a semiconductor devices 2, and described semiconductor devices 2 comprises MEMS and the IC device except MEMS.Base chip unit 1a has the weld pad projection 13 of metal material, and also have the seal convexity 14 of annular, weld pad projection 13 is in the outside of the seal convexity 14 of annular.Base plate for packaging 8 has weld pad or the weld pad projection 9 of metal material, also there is sealing weld pad or the weld pad projection 15 of annular, weld pad or the sealing weld pad of weld pad projection 9 in annular or the outside of weld pad projection 15.Base chip unit 1a upside-down mounting is on base plate for packaging 8, seal convexity 14 on base chip unit 1a is undertaken welding being connected as a single entity by solder 16 with the sealing weld pad on base plate for packaging 8 or weld pad projection 15, and forms a closed structure in the periphery of each semiconductor devices 2.This closed structure is made up of the seal convexity 14 on base chip unit 1a, substrate package unit 8a, base chip unit 1a, the seal convexity 15 on substrate package unit 8a and solder 15.Substrate package unit 8a is cut by base plate for packaging 8.Weld pad on base chip unit 1a protruding 13 is undertaken welding being connected as a single entity by solder 16 with the weld pad projection 9 on base plate for packaging 8, thus the weld pad of each semiconductor devices 2 is electrically connected weld pad on base plate for packaging 8 or weld pad projection 9 by weld pad projection 13, solder 16.Alternatively, solder 16 can omit.Preferably, described closed structure has air-tightness, and inside can be vacuum or blanketing gas.
The embodiment two that the application is applicable to the manufacture method of the closed structure of wafer-level package comprises each step following:
1st step, refers to Fig. 3 a, and substrate wafer 1 has manufactured multiple semiconductor devices 2, and semiconductor devices 2 has input and output weld pad on substrate wafer 1.Substrate wafer 1 grows weld pad protruding 13 and seal convexity 14, such as, be the materials such as gold, copper, scolding tin, can adopt sputtering and/or electroplating technology manufacture.Formed between weld pad protruding 13 and the weld pad of semiconductor devices 2 and be electrically connected, preferably weld pad projection 13 is on the weld pad of semiconductor devices 2.Seal convexity 14 in the form of a ring, is enclosed in the periphery of semiconductor devices 2.Weld pad projection 13 is in the outside of the seal convexity 14 of annular.
2nd step, refers to Fig. 3 b, cuts to obtain each base chip unit 1a to substrate wafer 1.Each base chip unit 1a has the seal convexity 14 of a semiconductor devices 2 and weld pad thereof, weld pad projection 13, ring-type.
3rd step, refers to Fig. 3 c, base plate for packaging 8 is arranged or growth weld pad or weld pad protruding 9 and multiple sealing weld pad or seal convexity 15, such as, be the materials such as gold, copper, scolding tin, can adopt and sputter and/or electroplating technology manufacture.The position of the weld pad on base plate for packaging 8 or weld pad projection 9 corresponds to the position of the weld pad projection 13 on each base chip unit 1a.Sealing weld pad on base plate for packaging 8 or seal convexity 15 are also ring-type, and its position corresponds to the position of the seal convexity 14 on each base chip unit 1a.
4th step; refer to Fig. 3 d; by base chip unit 1a upside-down mounting on base plate for packaging 8; seal convexity 14 on base chip unit 1a is undertaken welding being connected as a single entity by solder 16 with the sealing weld pad on base plate for packaging 8 or weld pad projection 15, thus constitutes the closed structure protecting each semiconductor devices 2.Weld pad on base chip unit 1a protruding 13 is also undertaken welding being connected as a single entity by solder 16 with the weld pad on base plate for packaging 8 or weld pad projection 9, thus the weld pad of semiconductor devices 2 is electrically drawn out to weld pad or the weld pad projection 9 of base plate for packaging 8.Weld pad on base chip unit 1a protruding 13 and the weld pad projection 9 on base plate for packaging 8 are outside this closed structure.Alternatively, solder 16 can be omitted during solder.
5th step, refers to Fig. 2, adopts encapsulating material 12 to be encapsulated by each several part on base plate for packaging 8, and then cuts to obtain packaged semiconductor devices to base plate for packaging 8.Base plate for packaging 8 obtains each substrate package unit 8a after cutting.Conventional encapsulating material 12 comprises plastics, pottery etc.
The embodiment two of the application provides a kind of novel closed structure for wafer-level package, using base chip unit as a bottom surface, using substrate package unit as another bottom surface, after welding using the seal convexity on base chip unit with the seal convexity on substrate package unit, (comprising solder alternatively) is as sidewall to form closed structure.Embodiment two is with the difference of embodiment one: in embodiment one, the weld pad of semiconductor devices and electric connection structure are positioned at the inside of this closed structure, and in embodiment two, the weld pad of semiconductor devices and electric connection structure are positioned at the outside of this closed structure, thus be applicable to different semiconductor devices.
These are only the preferred embodiment of the application, and be not used in restriction the application.For a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection domain that all should be included in the application.
Claims (10)
1. one kind is applicable to the closed structure of wafer-level package, it is characterized in that, the seal convexity that base chip unit has annular surrounds semiconductor devices, base plate for packaging also has the sealing weld pad of annular or seal convexity and corresponds to seal convexity on base chip unit; By the upside-down mounting of base chip unit on base plate for packaging, the seal convexity on base chip unit is connected as a single entity by welding with the sealing weld pad on base plate for packaging or seal convexity, and forms a closed structure in the periphery of each semiconductor devices.
2. the closed structure being applicable to wafer-level package according to claim 1, it is characterized in that, base chip unit also has the weld pad projection being formed with the weld pad of semiconductor devices and be electrically connected, base plate for packaging also has weld pad or the protruding weld pad projection corresponded on base chip unit of weld pad; By the upside-down mounting of base chip unit on base plate for packaging, the weld pad projection on base chip unit projects through to weld with the weld pad on base plate for packaging or weld pad and is connected as a single entity.
3. the closed structure being applicable to wafer-level package according to claim 1, it is characterized in that, weld pad on base chip unit protruding surround by the seal convexity of annular, the weld pad simultaneously on base plate for packaging or weld pad protruding also by the sealing weld pad of annular or weld pad protruding surround;
Or the weld pad on base chip unit is protruding in the outside of the seal convexity of annular, the weld pad simultaneously on base plate for packaging or weld pad projection are also in the sealing weld pad of annular or the outside of weld pad projection.
4. the closed structure being applicable to wafer-level package according to claim 1 and 2, it is characterized in that, weld pad on seal convexity on base chip unit, the sealing weld pad on base plate for packaging or seal convexity, base chip unit is protruding, weld pad on base plate for packaging or weld pad projection are metal material, comprises copper, gold, silver, tin and their alloys of forming.
5. the closed structure being applicable to wafer-level package according to claim 1, is characterized in that, described closed structure has air-tightness, and inside is vacuum or blanketing gas.
6. be applicable to a manufacture method for the closed structure of wafer-level package, it is characterized in that, comprise the steps:
1st step, substrate wafer manufactures semiconductor devices, on substrate wafer, also grow weld pad projection and seal convexity; Formed between weld pad projection and the weld pad of semiconductor devices and be electrically connected; Seal convexity in the form of a ring, is enclosed in the periphery of semiconductor devices and weld pad projection;
2nd step, cutting substrate wafer obtains each base chip unit;
3rd step, base plate for packaging is arranged or growth weld pad or weld pad is protruding and multiple sealing weld pad or seal convexity; The position of the weld pad on base plate for packaging or weld pad projection corresponds to the position of the weld pad projection on each base chip unit; Sealing weld pad on base plate for packaging or seal convexity are also ring-type, and its position corresponds to the position of the seal convexity on each base chip unit;
4th step, by the upside-down mounting of base chip unit on base plate for packaging, the seal convexity on base chip unit projects through to weld with the sealing weld pad on base plate for packaging or weld pad and is connected as a single entity, thus constitutes the closed structure protecting each semiconductor devices; Weld pad projection on base chip unit also projects through to weld with the weld pad on base plate for packaging or weld pad and is connected as a single entity, and in this closed structure;
5th step, encapsulates, then cuts base plate for packaging and obtain packaged semiconductor devices.
7. the manufacture method being applicable to the closed structure of wafer-level package according to claim 6, is characterized in that, in described method the 1st step, seal convexity is positioned at the outer rim one week of base chip unit.
8. the manufacture method being applicable to the closed structure of wafer-level package according to claim 6, is characterized in that,
In described method the 1st step, seal convexity changes the periphery being only enclosed in semiconductor devices into, and weld pad is protruding in the outside of the seal convexity of annular;
In described method the 4th step, the weld pad on base chip unit is protruding to be changed at this closed structure outside with the weld pad on base plate for packaging or weld pad projection.
9. the manufacture method being applicable to the closed structure of wafer-level package according to claim 6 or 8, is characterized in that, in described method the 2nd step, each base chip unit has a semiconductor devices and weld pad thereof, weld pad are protruding, the seal convexity of ring-type.
10. the manufacture method being applicable to the closed structure of wafer-level package according to claim 6 or 8, it is characterized in that, in described method the 1st step and the 3rd step, adopt sputtering and/or electroplating technology on substrate wafer or base plate for packaging, grow weld pad or weld pad is protruding, sealing weld pad or seal convexity.
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