CN105336628B - A kind of crystal column surface bonding technology and a kind of semiconductor device structure - Google Patents
A kind of crystal column surface bonding technology and a kind of semiconductor device structure Download PDFInfo
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- CN105336628B CN105336628B CN201510624214.0A CN201510624214A CN105336628B CN 105336628 B CN105336628 B CN 105336628B CN 201510624214 A CN201510624214 A CN 201510624214A CN 105336628 B CN105336628 B CN 105336628B
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- film layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/2954—Coating
- H01L2224/2957—Single coating layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8336—Bonding interfaces of the semiconductor or solid state body
- H01L2224/83375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The present invention relates to technical field of semiconductor device preparation, more particularly to a kind of crystal column surface bonding technology and a kind of semiconductor device structure, by in crystal column surface deposition film layer, then deposition one includes the dielectric layer of H+ ions, finally use Anneal techniques, promote the H+ ions in dielectric layer to be bonded with the interfaces wafer Si dangling bonds, improves the interfaces wafer Si dangling bonds and be bonded degree.By using the technical program, Dark Current and the BLC performances of device are obviously improved.
Description
Technical field
The present invention relates to technical field of semiconductor device preparation more particularly to a kind of crystal column surface bonding technology and a kind of half
Conductor device structure.
Background technology
In wafer manufacturing process, since the interfaces Si bonding Si atoms lack and the interface non-bonding electrons of Si atoms is deposited
, the interfaces Si formed with electrical activity dangling bonds (general crystal because lattice terminates suddenly at surface, surface most
Each atom of outer layer will there are one unpaired electronics, i.e., there are one unsaturated key, this key is known as dangling bonds, referred to as
Traps), the bonding degree of the dangling bonds is relatively low, and the atom source being bonded in the prior art with dangling bonds formation is less and lacks
It is bonded power, causes the bonding degree of dangling bonds between the interfaces Si relatively low, leads to the Dark Current (dark current) of device, BLC
Performances such as (backlight compensation functions) are poor.
Therefore, how bonded energy keeps the bonding degree of dangling bonds higher, while the Dark Current, BLC etc. for making device
The higher a great problem faced as those skilled in the art of performance.
Invention content
In view of the above problems, the present invention provides a kind of crystal column surface bonding technology and a kind of semiconductor device structure, passes through
A film layer is deposited in crystal column surface, a dielectric layer for including H+ ions is then deposited, finally uses Anneal techniques, promotes to be situated between
H+ ions in matter layer are bonded with the interfaces wafer Si dangling bonds, which is specially：
A kind of wafer Si surface bond techniques, wherein the technique includes：
A wafer is provided, the surface of the wafer includes dangling bonds；
Deposit the surface that a film layer covers the wafer；
Dielectric layer of the deposition one comprising H+ ions covers the upper surface of the film layer；
Using Anneal techniques, the H+ ions of the dielectric layer is made to be bonded with the dangling bonds on the surface of the wafer.
Above-mentioned wafer Si surface bond techniques, wherein the film layer includes the first film layer and the second film layer.
Above-mentioned wafer Si surface bond techniques, wherein the dielectric layer material is SiN.
A kind of semiconductor device structure, wherein the structure includes：
Wafer, remained on surface have dangling bonds；
Film layer covers the surface of the wafer；
Dielectric layer covers the upper surface of the film layer, and has H+ ions in the dielectric layer；And
Using annealing process, the H+ ions is made to be bonded with the dangling bonds, to improve the bonding journey of the crystal column surface
Degree.
Above-mentioned semiconductor device structure, wherein the film layer includes the first film layer and the second film layer；
The first film layer covers the surface of the wafer, and second film layer covers the table of the first film layer
Face, and the dielectric layer covers the surface of second film layer.
Above-mentioned semiconductor device structure, wherein the dielectric layer material is SiN.
Above-mentioned technical proposal has the following advantages that or advantageous effect：
Using the technical program, promote the Si of H+ ions and crystal column surface in SiN layer by SiN DEP and Anneal techniques
Dangling bonds be bonded, improve wafer Si interfaces dangling bonds and be bonded degree, Dark Current and the BLC performances of device are apparent
Improved.
Description of the drawings
With reference to appended attached drawing, more fully to describe the embodiment of the present invention.However, appended attached drawing be merely to illustrate and
It illustrates, and is not meant to limit the scope of the invention.
Fig. 1 is crystal column surface bonding technology flow chart in the embodiment of the present invention；
Fig. 2 a-2d are crystal column surface bonding technology structural schematic diagrams in the embodiment of the present invention；
Fig. 3 a-3d are a specific embodiment crystal column surface bonding technology structural schematic diagrams of the invention.
Specific implementation mode
Structure shown in Figure 1, the present invention provide a kind of crystal column surface bonding technology, which specifically includes：
First, a wafer 1 is provided, the material on 1 surface of wafer is Si, and the surface of wafer 1 includes dangling bonds, referring to Fig. 2 a institutes
Show.
Secondly, the surface of one film layer of deposition covering wafer 1, it is preferred that shown in Fig. 2 b, first deposit a first film
Layer 2, it is preferred that the first film layer 2 is high-K dielectric layer, wherein the first film layer 2 covers the upper surface of wafer 1；Referring to Fig. 2 c
It is shown, deposit one second film layer 3, it is preferred that the second film layer is silicon oxide layer, and the second film layer 3 covers the first film layer 2
Upper surface.
Continue the dielectric layer 4 that deposition one includes H+ ions, shown in Fig. 2 d, it is preferred that dielectric layer 4 is SiN layer, medium
Layer 4 covers the upper surface of the second film layer 3, includes H+ ions in dielectric layer.
Finally, using Anneal techniques, the H+ ions in dielectric layer is made to be bonded with the dangling bonds on the surface of wafer.
Referring to structure shown in Fig. 3 a, a wafer 1 for including the surfaces Si is provided, which is formed with electrical activity
The dangling bonds of Si, continuation covers a high-K dielectric layer 2 and one silica layer 3 on the surfaces Si of wafer, shown in Fig. 3 b, after
Continuous, shown in Fig. 3 c, SiN layer 4 of the covering one comprising H+ ions covers the upper surface of the second film layer silica, the SiN layer
In include H+ ions.Finally, using Anneal techniques, the H+ ions in SiN layer is promoted to be bonded with the dangling bonds at the interfaces Si,
Improve the bonding degree of crystal column surface Si dangling bonds.
Referring to structure shown in Fig. 3 d, the present invention provides a kind of semiconductor device structure, wherein the semiconductor device structure packet
Wafer, film layer and dielectric layer are included, wherein：
1 remained on surface of wafer has dangling bonds；Film layer, covers the surface of the wafer, and film layer includes that material is situated between for high K
The first film layer 2 and material of matter are the second film layer 3 of silica；Dielectric layer 4, the upper surface of cover layer, and medium
There is H+ ions in layer；Using annealing process, the H+ ions in dielectric layer is made to be bonded with the dangling bonds on 1 surface of wafer, to improve
The bonding degree of the crystal column surface.
Above-mentioned semiconductor device structure, wherein the film layer includes the first film layer and the second film layer；
In the present embodiment, the first film layer 2 covers the surface of wafer 1, and the second film layer 3 covers the first film layer 2
Surface, and dielectric layer 4 covers the surface of the second film layer 3.
In conclusion then the present invention is deposited a dielectric layer and is covered by the surface deposition film layer including Si in wafer
The upper surface of lid film layer finally uses Anneal techniques, promotes the H+ ions in the dielectric layer comprising H+ ions and wafer Si
The dangling bonds at interface are bonded, and using the technical program, Dark Current and the BLC performances of device are obviously improved, meanwhile,
Promote the interfaces Si of H+ ions and wafer in SiN layer by SiN DEP (deposition, deposition) and Anneal (annealing) technique
Dangling bonds be bonded, improve the bonding degree of wafer Si interfaces dangling bonds.
For a person skilled in the art, after reading above description, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard the whole variations and modifications for covering the true intention and range of the present invention as.It is weighing
The range and content of any and all equivalences within the scope of sharp claim, are all considered as still belonging to the intent and scope of the invention.
Claims (5)
1. a kind of wafer Si surface bond techniques, which is characterized in that the technique includes：
A wafer is provided, the surface of the wafer includes dangling bonds；
Deposit the surface that a film layer covers the wafer；
Dielectric layer of the deposition one comprising H+ ions covers the upper surface of the film layer；
Using Anneal techniques, the H+ ions of the dielectric layer is made to be bonded with the dangling bonds on the surface of the wafer；
The film layer includes the first film layer and the second film layer, and the first film layer is high-K dielectric layer, and the second film layer is oxygen
SiClx layer；
Wherein, the first film layer covers the upper surface of the wafer；Second film layer covers the first film layer
Upper surface.
2. wafer Si surface bond techniques as described in claim 1, which is characterized in that include the dielectric layer material of H+ ions
Matter is SiN.
3. a kind of semiconductor device structure, which is characterized in that the structure includes：
Wafer, remained on surface have dangling bonds；
Film layer covers the surface of the wafer；
Dielectric layer covers the upper surface of the film layer, and has H+ ions in the dielectric layer；And
Using annealing process, the H+ ions is made to be bonded with the dangling bonds, to improve the bonding degree of the crystal column surface；
The film layer includes the first film layer and the second film layer, and the first film layer is high-K dielectric layer, and the second film layer is oxygen
SiClx layer；
Wherein, the first film layer covers the upper surface of the wafer；Second film layer covers the first film layer
Upper surface.
4. semiconductor device structure as claimed in claim 3, which is characterized in that the first film layer covers the wafer
Surface, second film layer cover the surface of the first film layer, and include described in the dielectric layer covering of H+ ions
The surface of second film layer.
5. semiconductor device structure as claimed in claim 3, which is characterized in that the dielectric layer material comprising H+ ions is
SiN。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510624214.0A CN105336628B (en) | 2015-09-25 | 2015-09-25 | A kind of crystal column surface bonding technology and a kind of semiconductor device structure |
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| CN201510624214.0A CN105336628B (en) | 2015-09-25 | 2015-09-25 | A kind of crystal column surface bonding technology and a kind of semiconductor device structure |
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| Publication Number | Publication Date |
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| CN105336628A CN105336628A (en) | 2016-02-17 |
| CN105336628B true CN105336628B (en) | 2018-10-19 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106158676A (en) * | 2016-07-27 | 2016-11-23 | 武汉新芯集成电路制造有限公司 | The bonding technology of a kind of crystal column surface and semiconductor device structure |
| CN106531649B (en) * | 2016-12-19 | 2019-05-03 | 武汉新芯集成电路制造有限公司 | A method to improve the degree of wafer bonding |
| CN106981414A (en) * | 2017-03-30 | 2017-07-25 | 武汉新芯集成电路制造有限公司 | The bonding method and semiconductor devices of crystal column surface |
Citations (5)
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| CN1930668A (en) * | 2003-05-30 | 2007-03-14 | 东京毅力科创株式会社 | Method of modifying insulating film |
| CN101710580A (en) * | 2009-12-01 | 2010-05-19 | 杭州士兰集成电路有限公司 | Multi-layer compound passivation layer structure of Bipolar circuit and manufacturing process thereof |
| CN102136428A (en) * | 2011-01-25 | 2011-07-27 | 北京大学 | Preparation method of germanium-based Schottky N-type field effect transistor |
| CN102420194A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Integrated circuit passivation layer and manufacturing method thereof |
| CN103378003A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing CMOS device by means of stress memorization technique |
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2015
- 2015-09-25 CN CN201510624214.0A patent/CN105336628B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1930668A (en) * | 2003-05-30 | 2007-03-14 | 东京毅力科创株式会社 | Method of modifying insulating film |
| CN101710580A (en) * | 2009-12-01 | 2010-05-19 | 杭州士兰集成电路有限公司 | Multi-layer compound passivation layer structure of Bipolar circuit and manufacturing process thereof |
| CN102136428A (en) * | 2011-01-25 | 2011-07-27 | 北京大学 | Preparation method of germanium-based Schottky N-type field effect transistor |
| CN102420194A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | Integrated circuit passivation layer and manufacturing method thereof |
| CN103378003A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing CMOS device by means of stress memorization technique |
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Address after: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Xinxin Integrated Circuit Co.,Ltd. Country or region after: China Address before: 430205 No.18, Gaoxin 4th Road, Donghu Development Zone, Wuhan City, Hubei Province Patentee before: Wuhan Xinxin Semiconductor Manufacturing Co.,Ltd. Country or region before: China |
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