CN105335324B - The method of receiver and reception data for high-speed serial bus - Google Patents

Abstract

A kind of method of the receiver for high-speed serial bus and reception data is provided.The receiver includes：Decoder, for determining the type for receiving the control data cell in data；Counter is counted for the number of repetition to certain types of control data cell；Controller, according to the type of the control data cell determined by the decoder, the counter is controlled to count the number of repetition of certain types of control data cell, when the number of repetition reaches reference value, the certain types of control data cell of at least one repetition is abandoned from reception data；And buffer, for storing treated reception data.

Description

Receiver for high-speed serial bus and method for receiving data

technical field

The present invention relates to high-speed serial bus transmission technology, and more particularly, to a receiver for high-speed serial bus and a method for receiving data.

Background technique

With the wide application of digital devices in various fields, greater data storage capacity and higher bandwidth have been developed, such as Serial Advanced Technology Attachment (SATA), Peripheral Component Interconnect Express (PCIe), and ultra-high-speed High-speed serial bus technology of I (UHS-I) and Ultra High Speed II (UHS-II). Taking UHS-II as an example, a transfer rate of up to 156MB/s (full-duplex) or 312MB/s (half-duplex) can be achieved between the host and the memory card through two lanes.

In physical layer transmission, the two sides of the interface between the host and the memory card are in different clock domains. There is usually a phase difference between the clock sources of the sending and receiving sides in different clock domains, and there is even a slight difference in frequency. These differences between clock sources can be even more severe when spread spectrum clocking (SSC) techniques are used to reduce EMI.

For this reason, elastic buffers are usually used to solve the above problems. That is, the received data from the first clock domain is pushed (push) into the elastic buffer and popped (pop) to the second clock domain. However, if the clock frequency of the second clock domain is lower than the clock frequency of the first clock domain for a long time, the elastic buffer may overflow, making it impossible to receive further data. Currently, UHS-II does not specify how to solve the buffer overflow problem. Usually, additional hardware configuration needs to be designed to cope with buffer overflow. In addition, when using two lanes to transmit data at the same time in half-duplex mode, there will be another problem, that is, there are also differences between the clock sources of different lanes, resulting in the water level in the elastic buffer of each lane ( water mark), which is called data skew. Data skew can cause difficulty in merging data from each path. Thus, an additional hardware configuration such as a buffer for eliminating data skew between lanes is further required. The above additional hardware configuration increases the design complexity and makes the manufacturing cost more expensive.

Contents of the invention

Therefore, in order to solve the above-mentioned problems, the present invention provides a receiver for a high-speed serial bus and a method of receiving data capable of preventing buffer overflow and data skew.

According to one embodiment of the present invention, there is provided a receiver for a high-speed serial bus, comprising: a decoder for determining the type of control data unit in received data; a counter for controlling the specific type of control data unit Count the number of repetitions; the controller, according to the type of control data unit determined by the decoder, controls the counter to count the number of repetitions of the specific type of control data unit, and when the number of repetitions reaches a reference value, from discarding at least one repetition of the specific type of control data unit in the received data; and a buffer for storing the processed received data.

According to an embodiment, when the type of the control data unit belongs to the idle data unit, the controller may control the counter to count the repetition times of the above-mentioned specific type of control data unit belonging to the idle data unit.

According to an embodiment, the high-speed serial bus may be an Ultra High Speed II (UHS-II) bus, and the specific type of control data unit may include at least one of the following Link Symbol Sets (LSS): Synchronization (SYN) , Logical Idle (LIDL), Data Transfer Logical Idle (DIDL), and Direction Switching (DIR).

According to an embodiment, the receiver may further include a register for setting the reference value.

According to an embodiment, said reference value may be determined by the duration of said specific type of control data unit.

According to an embodiment, the reference value may be 16 to 256.

According to an embodiment, the receiver may include multiple data paths, each data path may include a separate counter and buffer.

According to an embodiment, the bumper may be an elastic bumper.

According to an embodiment, the receiver may receive the received data according to a first clock recovered from the received data, and may output said processed received data stored in the buffer according to a second clock, wherein said The reference value may be determined by a difference between the first clock and the second clock.

According to another embodiment of the present invention, there is provided a method for receiving data on a high-speed serial bus, including: determining the type of control data unit in the received data; counting the number of repetitions of the unit, and discarding at least one repetition of the specific type of control data unit from the received data when the number of repetitions reaches a reference value; and storing the processed received data.

According to an embodiment, when the type of the control data unit belongs to the free data unit, the number of repetitions of the above-mentioned specific type of control data unit belonging to the free data unit may be counted.

According to an embodiment, the high-speed serial bus may be an Ultra High Speed II (UHS-II) bus, and the specific type of control data unit may include at least one of the following Link Symbol Sets (LSS): Synchronization (SYN) , Logical Idle (LIDL), Data Transfer Logical Idle (DIDL), and Direction Switching (DIR).

According to an embodiment, the method may further include: setting the reference value.

According to an embodiment, said reference value may be determined by the duration of said specific type of control data unit.

According to an embodiment, the reference value may be 16 to 256.

According to an embodiment, the received data may be received according to a first clock recovered from the received data, and said processed received data stored in the buffer may be output according to a second clock, wherein said reference value may be Determined by the difference between the first clock and the second clock.

According to an embodiment of the present invention, when data is received across clock domains, buffering can be effectively controlled by counting the number of repetitions of a certain type of control data unit (e.g., an idle data unit) and discarding at least one duplicated control data unit The watermark in the buffer prevents the buffer from overflowing without adding hardware design complexity. In addition, in the case of receiving data through multiple paths, the problem of data skew due to clock frequency differences between different paths can be further solved.

Description of drawings

1 is a block diagram illustrating a receiver 100 for a high-speed serial bus according to an embodiment of the present invention;

Fig. 2 is a flowchart illustrating a method for receiving data for a high-speed serial bus according to an embodiment of the present invention;

3 is a block diagram illustrating an elastic buffer 300 for a high-speed serial bus according to an embodiment of the present invention; and

FIG. 4 is a flowchart illustrating a method for elastic buffering of a high-speed serial bus according to an embodiment of the present invention.

Detailed ways

Exemplary embodiments according to the present invention are described in detail below with reference to the accompanying drawings. In the drawings, the same or similar reference numerals are assigned to components having substantially the same structure and function, and redundant descriptions about the components that are substantially the same are omitted in order to make the description more concise.

Hereinafter, embodiments of the present invention will be described taking Ultra High Speed II (UHS-II) as an example of a high-speed serial bus. However, the present invention is not limited thereto. The solution of the present invention can also be applied to other high-speed serial bus (such as SATA or PCIe bus) technologies using elastic buffers between different clock domains.

FIG. 1 is a block diagram illustrating a receiver 100 for a high-speed serial bus according to an embodiment of the present invention.

Referring to FIG. 1 , a receiver 100 may include a decoder 101 , a counter 102 , a controller 103 , and a buffer 104 . In an embodiment, the receiver 100 may be disposed in a physical layer of a host or a memory card. The receiver 100 receives data from a first clock domain and outputs processed received data to a second clock domain. For example, one side of the receiver 100 generates a recovered clock source from the data received from the transmitter (not shown) through clock data recovery (CDR), and pushes the received data to the In the receiver 100, the other side of the receiver 100 pops the processed received data into the second clock domain, and the second clock domain is, for example, a local clock source of the host or the memory card.

The decoder 101 may determine the type of control data unit in the received data. For example, in UHS-II, the control data unit can be a link symbol set (LLS), including: synchronization (SYN), bootstrap synchronization (BSYN), direction switch (DIR), logic idle (LIDL), data transmission logic Idle (DIDL), Start of Data Burst (SDB), End of Data Burst (EDB), Start of Packet (SOP), End of Packet (EOP), etc. Each LLS has its own signal pattern, and the decoder 101 determines its type through the signal pattern of the LLS. For example, LIDL can consist of two symbols, the first symbol is a comma (COM) (K28.5), and the second symbol can be a symbol randomly selected from LIDL0 (K28.3) and LIDL1 (D16.7). The signal styles and functions of various LLS are specified in UHS-II Physical Layer Specification 4.0 in detail, and will not be repeated here.

Counter 102 may count the number of repetitions of a particular type of control data unit. According to an embodiment of the present invention, when the type of the control data unit is determined to belong to the idle data unit by the decoder 101, the controller 103 may control the counter 102 to count the number of repetitions of the control data unit whose type is determined to belong to the idle data unit . In UHS-II, an idle data unit may be at least one or all of the following LLSs: SYN, DIR, LIDL, and DIDL. However, this is just an example, and the present invention is not limited thereto. In addition, according to an embodiment, the number of repetitions of other control data units other than idle data units may also be counted.

When the number of repetitions reaches the reference value, the controller 103 may discard at least one repetition of the aforementioned specific type of control data unit from the received data, and store the processed received data in the buffer 104, so as to send to the second clock domain supply. According to an embodiment, the bumper 104 may be a resilient bumper. Since only a small fraction of control data units of a particular type in the input data are discarded, the water level of the buffer 104 can be effectively controlled in order to prevent the buffer 104 from overflowing. In order to avoid affecting transmission signaling, only idle data units may be discarded.

In UHS-II, LLS such as SYN, DIR, LIDL, and DIDL as idle data units are usually sent repeatedly in large numbers, so discarding repeated LLS properly will not cause subsequent decoding errors on received data. The present invention controls the frequency of discarding repeated LLSs based on a reference value, so that the water level of the elastic buffer is neither too high to be nearly full nor too low to be empty. To this end, according to an embodiment, the receiver 100 may further include a register (not shown) for setting the reference value for a specific type of idle data unit. In an embodiment, the reference value is determined by the duration of the idle data unit, in particular, by the duration of the idle data unit with the shortest duration among the idle data units. For example, the duration of DIR is the shortest, which is N_LSS_DIR*8 (for example, N_LSS_DIR can be equal to 8), and the reference value can be set to 16, that is, whenever 16 repeated idle data units (including SYN, DIR, LIDL, and all or part of DIDL types), discarding a DIR with the shortest duration is sufficient to maintain the water level of the buffer 104 at a low level without overflowing, and does not affect subsequent decoding of received data, then Discarding one free data unit of any type must then be sufficient to lower the watermark of the buffer 104 to a lower level without causing decoding errors. On the other hand, the reference value is also determined by the clock source difference (including phase difference and/or frequency difference) between the first clock domain and the second clock domain. Source differences have little effect. In other embodiments, the reference value can even be set as high as 256, that is, every 256 repeated idle data units are discarded, which is still enough to quickly reduce the water level to a lower level without causing Decoding error.

According to an embodiment, the receiver 100 may include multiple data paths, in which case each data path may include a separate counter 102 and buffer 104 . In the half-duplex mode, idle data units can be discarded in each buffer 104 to eliminate data skew, so that the water levels of the buffers 104 of each path are aligned to facilitate data merging.

FIG. 2 is a flowchart illustrating a method for receiving data for a high-speed serial bus according to an embodiment of the present invention.

Referring to FIG. 2, in step S201, a type of a control data unit in received data may be determined. As mentioned above, in UHS-II, the control data unit can be LLS, including: SYN, BSYN, DIR, LIDL, DIDL, SDB, EDB, SOP, EOP, etc. The type of LLS can be determined by its signal pattern.

In step S202, if the type of the control data unit belongs to a specific type of control data unit, the number of repetitions of the specific type of control data unit may be counted in step S203, otherwise, go to step S206. As mentioned above, taking UHS-II as an example, a specific type of control data unit may include at least one or all of the following LSSs: SYN, LIDL, DIDL, and DIR. However, this is just an example, and the present invention is not limited thereto. In addition, according to an embodiment, the number of repetitions of other specific types of control data units other than idle data units may also be counted.

In step S204, if the number of repetitions reaches the reference value, at least one repeated specific type of control data unit (or other control data units) may be discarded from the received data in step S205, otherwise, it may return to step S203 to continue counting.

In step S206, the processed received data is stored so as to be provided to the second clock domain.

As mentioned above, in order to accurately control the water level in the buffer, it can be based on the duration of a specific type of control data unit (including, for example, SYN, DIR, LIDL, and DIDL) and the difference between the first clock domain and the second clock domain. The clock source difference is used to determine the reference value. The reference value may range from 16 to 256.

Furthermore, according to an embodiment, when transmitting over multiple data lanes, counting and buffering may be performed separately for each data lane. In the half-duplex mode, idle data units can be discarded in each data channel to eliminate data skew, so that the water level is even, so that the data can be merged.

FIG. 3 is a block diagram illustrating an elastic buffer 300 for a high-speed serial bus according to an embodiment of the present invention. The elastic buffer 300 in FIG. 3 is different from the buffer 104 in FIG. 1 in that it has the function of counting and discarding idle data units.

Referring to FIG. 3 , the elastic buffer 300 may include an input interface 301 , a controller 302 , a memory 303 , and an output interface 304 .

The controller 302 may identify idle data units in the data received from the first clock domain through the input interface 301, and count the number of repetitions of the identified idle data units, and when the number of repetitions reaches a reference value, start from Discard at least one repeated idle data unit in the received data, and store the processed received data in the memory 303 . In one embodiment, the memory 303 is a first-in-first-out buffer (FIFO buffer).

The output interface 304 may output the received data stored in the memory 303 and processed by the controller 302 to the second clock domain.

As mentioned above, the high-speed serial bus may be a UHS-II bus, and the idle data unit may include at least one or all of the following LSSs: SYN, LIDL, DIDL, and DIR.

In addition, according to an embodiment, in order to precisely control the water level, the elastic buffer 300 may further include a register (not shown) for setting the reference value. Specifically, the reference value may be determined according to the duration of idle data units (including SYN, DIR, LIDL, and DIDL) and/or the clock source difference between the first clock domain and the second clock domain. The reference value may range from 16 to 256.

FIG. 4 is a flowchart illustrating a method for elastic buffering of a high-speed serial bus according to an embodiment of the present invention.

Referring to FIG. 4, in step S401, data from a first clock domain is received.

In step S402, identify idle data units in the received data, and count the number of repetitions of the identified idle data units. For the UHS-II bus, the idle data unit may include at least one or all of the following LSSs: SYN, LIDL, DIDL, and DIR.

In step S403, if the number of repetitions reaches the reference value, discard at least one repeated idle data unit from the received data in step S404, otherwise, go back to step S402 to continue counting.

In step S405, the processed received data is stored.

In step S406, output the stored and processed received data to the second clock domain.

According to an embodiment, the reference value may be determined according to the duration of the idle data unit and/or the clock source difference between the first clock domain and the second clock domain. The reference value may range from 16 to 256.

As described above, the various embodiments of the present invention have been specifically described above, but the present invention is not limited thereto. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations or substitutions may be made depending on design requirements or other factors, and they are within the scope of the appended claims and the equivalents thereof.

Claims (10)

1. A receiver for a high-speed serial bus, comprising: a decoder for determining the type of control data unit in the received data; a counter for counting the number of repetitions of a specific type of control data unit; a controller, controlling the counter to count the number of repetitions of the specific type of control data unit according to the type of the control data unit determined by the decoder, and when the number of repetitions reaches a reference value, from the received data discarding at least one repetition of said specific type of control data unit; and The buffer is used to store the processed received data. 2. The receiver as claimed in claim 1, wherein, when the type of the control data unit belongs to an idle data unit, the controller controls the counter to repeat the number of times of the above-mentioned specific type of control data unit belonging to the idle data unit to count. 3. The receiver of claim 1 , wherein the high-speed serial bus is an Ultra High Speed II (UHS-II) bus, and the specific type of control data unit includes the following Link Symbol Set (LSS) At least one of: Synchronization (SYN), Logical Idle (LIDL), Data Transfer Logical Idle (DIDL), and Direction Switching (DIR). 4. The receiver of claim 1, further comprising: register for setting the reference value. 5. The receiver of claim 1, wherein the reference value is determined by a duration of the specific type of control data unit. 6. The receiver of claim 1, wherein the reference value is 16 to 256. 7. The receiver of claim 1, comprising a plurality of data paths, each data path comprising a separate said counter and said buffer. 8. The receiver of claim 1, wherein the bumper is an elastic bumper. 9. The receiver of claim 1, wherein the receiver receives the received data according to a first clock recovered from the received data, and outputs the processed clock stored in the buffer according to a second clock The received data, wherein the reference value is determined by the difference between the first clock and the second clock. 10. A method for receiving data on a high-speed serial bus, comprising: determining the type of control data unit in the received data; Counting the number of repetitions of a control data unit of a specific type according to the type of the control data unit, and discarding at least one repeated control data unit of the specific type from the received data when the number of repetitions reaches a reference value; as well as The processed received data is stored.