CN105335299B - Data storage method, memory control circuit unit and memory storage device - Google Patents

Abstract

The present invention provides a data storage method, a memory control circuit unit and a memory storage device. The method includes: generating parity information according to first data. The method also includes: when programming the first data to a first physical programming unit, programming at least one mark to a redundant bit area in the first physical programming unit. The method also includes: programming the parity information to at least one second physical programming unit arranged after the first physical programming unit, wherein the at least one mark indicates that the parity information is programmed to the at least one second physical programming unit.

Description

Data storage method, memory control circuit unit and memory storage device

technical field

The present invention relates to a data storage method, and in particular to a data storage method for a rewritable non-volatile memory, a memory control circuit unit and a memory storage device.

Background technique

The rapid growth of digital cameras, mobile phones, and MP3 players has led to a rapid increase in consumer demand for storage media. Since rewritable non-volatile memory (rewritable non-volatile memory) has the characteristics of data non-volatility, power saving, small size, no mechanical structure, fast read and write speed, etc., in recent years, rewritable non-volatile memory The memory industry has become a very popular part of the electronics industry. For example, a solid-state drive using flash memory as a storage medium has been widely used as a hard disk of a computer host to improve the access performance of the computer.

Because the data stored in the rewritable non-volatile memory may generate error bits due to various factors (such as leakage of memory cells, programming failure, damage, etc.), therefore, configuration errors are generally encountered in memory storage systems. The checking and correcting circuit generates error checking and correcting codes for the stored data to ensure the correctness of the data. However, when the number of erroneous bits in the data exceeds the number of erroneous bits that can be detected and corrected by the ECC circuit, the data containing the erroneous bits cannot be corrected, resulting in data loss. Generally, when this situation occurs, the data can be corrected according to the parity corresponding to the data to be corrected stored in the rewritable non-volatile memory. Traditionally, the data in the data bit area and the redundant bit area of the entity programming unit where the parity information is located is also calculated from other protected data, that is, the information in the redundant bit area cannot be obtained. It is known that these physical programming units are the physical programming units where the parity information is located. Therefore, the traditional method places the parity information in a fixed position.

For example, assuming a memory storage system has eight memory dies, the last memory die among them is used to store parity information. If the data from the host system only needs to be written into one physical programming unit, it is necessary to fill the corresponding physical programming unit in the middle six memory dies with dummy data to generate the data to be stored. Parity information in the corresponding physical programming unit in the eighth memory die. That is to say, this approach will result in a waste of storage space in the memory storage device. Based on this, how to increase and improve the correction capability and efficiency of error correction without wasting the storage space in the memory storage device is the goal that those skilled in the art are working on.

Contents of the invention

The present invention provides a data storage method, a memory control circuit unit and a memory storage device, which can effectively avoid the waste of storage space in the memory storage device and when the error bit of the data cannot be corrected by the error checking and correction code, the error bit can be corrected by the error checking and correction code. The stored parity information is used to correct the erroneous bits of this data, thereby improving the ability of error correction.

An exemplary embodiment of the present invention provides a data storage method for a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of physical erasing units, and each physical erasing The division unit includes a plurality of physical programming units, and each physical programming unit includes a data bit area and a redundant bit area. The data storage method includes: generating a parity information according to the first data; programming the data to In a first physical programming unit among the physical programming units; and programming the parity information into at least one second physical programming unit among the physical programming units, wherein the at least one The second physical programming unit is arranged behind the first physical programming unit. The above step of programming the data into the first physical programming unit among the physical programming units includes: programming at least one tag into a redundancy in the first physical programming unit A bit field, wherein the at least one flag indicates that the parity information is programmed into the at least one second physical programming unit.

In an embodiment of the present invention, the above-mentioned first data includes user data and management information corresponding to the user data, wherein the user data is programmed into the first entity programming unit The data bit area of , wherein the management information corresponding to the user data is programmed into the redundant bit area in the first physical programming unit.

In an embodiment of the present invention, the above-mentioned first data includes user data, management information corresponding to the user data, and an error checking and correction code corresponding to the user data. Wherein the ECC code is generated according to the user data. Wherein the user data is programmed into the data bit area of the first physical programming unit, wherein the management information corresponding to the user data is programmed into the first physical programming unit The redundant bit area in the first physical programming unit, wherein the error checking and correction code corresponding to the user data is programmed into the redundant bit area in the first physical programming unit.

In an embodiment of the present invention, the above-mentioned step of programming the at least one flag into the redundant bit area in the programming unit of the first entity includes: programming the first flag into the first entity The redundant bit area of the last physical programming unit among the programming units, wherein the at least one second physical programming unit is the last physical programming unit arranged among the first physical programming units After the unit, wherein the first flag instructs the at least one second physical programming unit to store the parity information; and programming the second flag to at least one third physical programming unit in the physical programming unit A redundant bit area of a unit, wherein the at least one third physical programming unit is arranged after the at least one second physical programming unit, wherein the second flag indicates the at least one second physical programming unit The parity information is stored.

In an embodiment of the present invention, the step of programming the at least one flag into the redundant bit area in the first physical programming unit further includes: establishing a parity information address correspondence table; and adding a A third flag is recorded in the parity information address correspondence table, wherein the third flag instructs the at least one second physical programming unit to store the parity information.

In an embodiment of the present invention, the step of programming the at least one flag into the redundant bit area in the first physical programming unit includes: counting the number of the first physical programming unit ; and according to the number of the first physical programming unit, record a flag value in the redundant bit area of each of the first physical programming unit, wherein the value recorded in the first physical programming unit The tag value is sequentially decremented according to the arrangement of the first physical programming unit.

In an embodiment of the present invention, the first flag value among the above flag values is 1, and the first flag value is recorded in the last entity programming unit among the first entity programming units In the redundant bit area, and the at least one second physical programming unit is arranged after the last physical programming unit among the first physical programming units, wherein the first physical programming unit among the tag values The second flag value is 2, and the second flag value is recorded in the redundant bit area of the physical programming unit adjacent to the first physical programming unit and arranged before the last physical programming unit , wherein the third tag value among the tag values is 3, and the third tag value is recorded adjacent to and arranged in the first entity programming unit where the second tag value is recorded In the redundant bit area of the physical programming unit before the physical programming unit.

In an embodiment of the present invention, the above-mentioned first data includes a second data and an error checking and correction code, and the above data storage method further includes: when the error checking and correction code cannot be used to correct the For the second data, obtain the address of the at least one second physical programming unit that records the parity information according to the at least one mark, read the parity information from the at least one second physical programming unit and Correcting the second data according to the read parity information.

An exemplary embodiment of the present invention provides a data storage method for a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of physical erasing units, and each physical erasing The division unit includes a plurality of physical programming units, and each physical programming unit includes a data bit area and a redundant bit area. The data storage method includes: establishing a parity information address correspondence table; generating a parity information according to the first data ; programming the data into a first physical programming unit among the physical programming units; programming the parity information into at least one second physical programming unit among the physical programming units , and record at least one mark in the parity information address correspondence table, wherein the mark indicates that the parity information is programmed into the at least one second physical programming unit.

An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module includes a plurality of physical erasing units, and each A physical erasing unit includes a plurality of physical programming units, and each physical programming unit includes a data bit area and a redundant bit area. The memory control circuit unit includes a host interface, a memory interface and a memory management circuit. The host interface is used for coupling to the host system, the memory interface is used for coupling to the rewritable non-volatile memory module, and the memory management circuit is coupled to the host interface and the memory interface. The memory management circuit is used for generating parity information according to the first data and programming the first data into the first physical programming unit among the physical programming units, wherein the memory management circuit is also used for The parity information is programmed into at least one second physical programming unit among the physical programming units, wherein the at least one second physical programming unit is arranged after the first physical programming unit. In the above operation of programming the data into the first physical programming unit among the physical programming units, the memory management circuit programs at least one flag into the first physical programming unit , wherein the at least one flag indicates that the parity information is programmed into the at least one second physical programming unit.

In an embodiment of the present invention, the above-mentioned first data includes user data and management information corresponding to the user data, wherein the user data is programmed into the first entity programming unit The data bit area of , wherein the management information corresponding to the user data is programmed into the redundant bit area in the first physical programming unit.

In an embodiment of the present invention, the above-mentioned first data includes user data, management information corresponding to the user data, and an error checking and correction code corresponding to the user data. Wherein the ECC code is generated according to the user data. Wherein the user data is programmed into the data bit area of the first physical programming unit, wherein the management information corresponding to the user data is programmed into the first physical programming unit The redundant bit area in the first physical programming unit, wherein the error checking and correction code corresponding to the user data is programmed into the redundant bit area in the first physical programming unit.

In an embodiment of the present invention, in the above-mentioned operation of programming the at least one flag into the redundant bit area in the first physical programming unit, the memory management circuit programs the first flag into the The redundant bit area of the last physical programming unit among the first physical programming units, wherein the at least one second physical programming unit is the last physical programming unit arranged among the first physical programming units After the physical programming unit, wherein the first flag instructs the at least one second physical programming unit to store the parity information, wherein the memory management circuit is also used to program the second flag to the physical programming unit A redundant bit area of at least one third physical programming unit, wherein the third physical programming unit is arranged after the at least one second physical programming unit, and the second flag indicates that the at least A second physical programming unit stores the parity information.

An exemplary embodiment of the present invention provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used for coupling to the host system. The rewritable non-volatile memory module includes a plurality of physical erasing units, and each physical erasing unit includes a plurality of physical programming units, wherein each physical programming unit includes a data bit area and a redundant bit area. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module, and is used for generating parity information according to the first data, and programming the first data to the physical programming unit In a first entity programming unit in . In addition, the memory control circuit unit is also used to program the parity information into at least one second physical programming unit among the physical programming units, wherein the at least one second physical programming unit is arranged in The first entity is programmed after the unit. In the above operation of programming the first data into the first physical programming unit among the physical programming units, the memory control circuit unit programs at least one flag into the first physical programming unit A redundant bit field in a unit, wherein the at least one flag indicates that the parity information is programmed into the at least one second physical programming unit.

In an embodiment of the present invention, the above-mentioned first data includes user data and management information corresponding to the user data, wherein the user data is programmed into the first entity programming unit The data bit area of , wherein the management information corresponding to the user data is programmed into the redundant bit area in the first physical programming unit.

In an embodiment of the present invention, the above-mentioned first data includes user data, management information corresponding to the user data, and an error checking and correction code corresponding to the user data. Wherein the ECC code is generated according to the user data. Wherein the user data is programmed into the data bit area of the first physical programming unit, wherein the management information corresponding to the user data is programmed into the first physical programming unit The redundant bit area in the first physical programming unit, wherein the error checking and correction code corresponding to the user data is programmed into the redundant bit area in the first physical programming unit.

In an embodiment of the present invention, in the above-mentioned operation of programming the at least one flag into the redundant bit area in the first physical programming unit, the memory control circuit unit programs a first flag into The redundant bit area of the last physical programming unit among the first physical programming units, wherein the at least one second physical programming unit is the After the last physical programming unit, wherein the first flag instructs the at least one second physical programming unit to store the parity information, wherein the memory control circuit unit is also used to program the second flag to the physical program The redundant bit area of at least one third physical programming unit among the programming units, wherein the at least one third physical programming unit is arranged after the at least one second physical programming unit, and the second The flag instructs the at least one second physical programming unit to store the parity information.

In an embodiment of the present invention, in the above-mentioned operation of programming the at least one flag into the redundant bit area in the first physical programming unit, the memory control circuit unit establishes a parity information address correspondence table and Recording a third mark in the parity information address correspondence table, wherein the third mark instructs the at least one second entity programming unit to store the parity information.

In an embodiment of the present invention, in the above-mentioned operation of programming the at least one flag into the redundant bit area in the first physical programming unit, the memory control circuit unit counts the first physical programming The number of units, and according to the number of the first physical programming unit, record a flag value in the redundant bit area of each first physical programming unit, wherein the value recorded in the first physical programming unit The tag values in are sequentially decremented according to the arrangement of the first entity programming unit.

In an embodiment of the present invention, the first flag value among the above flag values is 1, and the first flag value is recorded in the last entity programming unit among the first entity programming units In the redundant bit area, the at least one second physical programming unit is arranged after the last physical programming unit among the first physical programming units. Among the tag values, the second tag value is 2, and the second tag value is recorded in the entity program adjacent to the first entity programming unit and arranged before the last entity programming unit in the redundant bit area of the unit. Wherein the third tag value among the tag values is 3, and the third tag value is recorded in the first entity programming unit adjacent and arranged in the entity program recording the second tag value In the redundant bit area of the physical programming unit before the programming unit.

In an embodiment of the present invention, the above-mentioned first data includes a second data and an error checking and correcting code, and when the second data cannot be corrected by using the error checking and correcting code, the memory control circuit unit It is also used to obtain the address of the at least one second physical programming unit that records the parity information according to the at least one mark, read the parity information from the at least one second physical programming unit and according to the The read parity information is used to correct the second data.

Based on the above, when there is an error in the data bits read from the rewritable non-volatile memory module, an exemplary embodiment of the present invention can quickly obtain parity information according to at least one mark recorded in the physical programming unit The entity programmatic unit address where it is located. Accordingly, the data storage method, the memory control circuit unit and the memory storage device proposed by the exemplary embodiments of the present invention can effectively increase the correction capability and efficiency of error correction.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A is a schematic diagram of a host system and a memory storage device according to a first exemplary embodiment of the present invention;

1B is a schematic diagram of a computer, an input/output device and a memory storage device according to a first exemplary embodiment of the present invention;

FIG. 1C is a schematic diagram of a host system and a memory storage device according to a first exemplary embodiment of the present invention;

FIG. 2 is a schematic block diagram illustrating the memory storage device shown in FIG. 1A;

3 is a schematic block diagram of a memory control circuit unit according to a first exemplary embodiment of the present invention;

FIG. 4A and FIG. 4B are exemplary schematic diagrams of a management entity erasing unit shown according to the first exemplary embodiment;

5A to FIG. 5B show writing data, error checking and correction codes corresponding to the writing data, and at least one mark for recording parity information into the physical programming device according to the first exemplary embodiment of the present invention. An example schematic diagram of the unit;

6 is another example of writing write data, error checking and correction codes corresponding to the write data, and at least one mark for recording parity information into the physical programming unit according to the first exemplary embodiment of the present invention. An example schematic diagram;

FIG. 7 is a flowchart of a data storage method according to a first exemplary embodiment of the present invention;

8A to FIG. 8B show writing data, error checking and correction codes corresponding to the writing data, and at least one mark for recording parity information into the physical programming device according to the second exemplary embodiment of the present invention. An example schematic diagram of the unit;

FIG. 9 is a schematic diagram showing an example of arranging and recording tag values according to the number of each physical programming unit to be written into data according to the third exemplary embodiment of the present invention;

FIG. 10 shows another method for writing write data, error checking and correction codes corresponding to the write data, and at least one mark for recording parity information into the physical programming unit according to the third exemplary embodiment of the present invention. A schematic diagram of an example;

FIG. 11 shows programming of write data, error checking and correction codes corresponding to the write data to the physical programming unit, and recording at least one mark for recording parity information according to a fourth exemplary embodiment of the present invention. An example schematic diagram of the parity information address correspondence table;

Fig. 12 is a flowchart of a data storage method according to a fourth exemplary embodiment of the present invention.

Explanation of reference signs:

1000: host system;

1100: computer;

1102: microprocessor;

1104: random access memory (RAM);

1106: input/output device;

1108: system bus;

1110: data transmission interface;

1202: mouse;

1204: keyboard;

1206: display;

1208: printer;

1212: U disk;

1214: memory card;

1216: SSD;

1310: digital camera;

1312: SD card;

1314: MMC card;

1316: memory stick;

1318: CF card;

1320: embedded storage device;

100: memory storage device;

102: connect the interface unit;

104: memory control circuit unit;

106: a rewritable non-volatile memory module;

410(0)～410(N): Entity erasing unit;

202: memory management circuit;

204: host interface;

206: memory interface;

208: buffer memory;

210: power management circuit;

212: error checking and correction circuit;

502: data area;

504: idle area;

506: system area;

508: Replacement area;

510(0)～510(D): logical address;

520: data bit area;

540: redundant bit area;

542: the first recording area;

544: the second recording area;

800, 110: parity information address correspondence table;

602, 702, 802: the first entity programming unit;

604, 704, 804: the second entity programming unit;

606, 706, 806: third entity programming unit;

808: The fourth entity programming unit;

810: The fifth entity programming unit;

812: The sixth entity programming unit;

900: sort;

D1, D1-1～D1-4: first user data;

D2, D2-1, D2-2: second user data;

D3, D3-1, D3-2: third user data;

S1, S1-1～S1-4: management information of the first user data;

S2, S2-1, S2-2: management information of the second user data;

S3-1, S3-2: management information of third user data;

M1: first mark;

M2: second mark;

M3: third mark;

ECC1-1～ECC1-4, ECC2, ECC2-1, ECC2-2, ECC3-1, ECC3-2: error checking and correction codes;

P: parity information;

P1: first parity information;

P2: second parity information;

P3: third parity information;

S701, S703, S705, S707, S1201, S1203, S1205, S1207, S1209: steps of the data storage method.

Detailed ways

[First Exemplary Embodiment]

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module and a controller (also called a control circuit). Typically memory storage devices are used with a host system such that the host system can write data to or read data from the memory storage device.

FIG. 1A is a schematic diagram of a host system and a memory storage device according to a first exemplary embodiment of the present invention.

Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (input/output, I/O for short) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM for short) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

In the embodiment of the present invention, the memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into or read from the memory storage device 100 through the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the memory storage device 100 may be a rewritable non-volatile memory storage device such as a USB flash drive 1212, a memory card 1214, or a solid state drive (Solid State Drive, SSD for short) 1216 as shown in FIG. 1B.

In general, host system 1000 is any system that can cooperate substantially with memory storage device 100 to store data. Although in this exemplary embodiment, the host system 1000 is described as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host computer system is the digital camera (video camera) 1310 in FIG. CF card 1318 or embedded storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (Embedded MMC, eMMC for short). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 2 is a schematic block diagram showing the memory storage device shown in FIG. 1A.

Referring to FIG. 2 , the memory storage device 100 includes a connection interface unit 102 , a memory control circuit unit 104 and a rewritable non-volatile memory module 106 .

In this exemplary embodiment, the connection interface unit 102 complies with the Serial Advanced Technology Attachment (SATA) standard. However, it must be understood that the present invention is not limited thereto, and the connection interface unit 102 may also be in compliance with the Parallel Advanced Technology Attachment (PATA for short) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE for short) 1394 standard, Peripheral Component Interconnect Express (PCI Express for short) standard, Universal Serial Bus (USB for short) standard, Ultra High Speed-I (UHS-I for short) interface standard , Ultra High Speed-II (UHS-II for short) interface standard, Secure Digital (SD for short) interface standard, Memory Stick (MS for short) interface standard, Multi Media Card (Multi MediaCard for short) interface standard , MMC for short) interface standard, Compact Flash (CF for short) interface standard, Integrated Device Electronics (IDE for short) standard, or other suitable standards. In this exemplary embodiment, the connector can be packaged with the memory control circuit unit in a chip, or arranged outside a chip including the memory control circuit unit.

The memory control circuit unit 104 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and write and read data in the rewritable non-volatile memory module 106 according to the instructions of the host system 1000. Fetch, erase, and merge operations.

The rewritable non-volatile memory module 106 is coupled to the memory control circuit unit 104 and used for storing data written by the host system 1000 . The rewritable non-volatile memory module 106 has physical erasing units 410(0)˜410(R). For example, the physical erasing units 410(0)˜410(R) may belong to the same memory die or belong to different memory dies. Each physical erasing unit has a plurality of physical programming units, wherein the physical programming units belonging to the same physical erasing unit can be written independently and erased simultaneously. In addition, each physical erasing unit can be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

In more detail, the entity erasing unit is the smallest unit of erasing. That is, each physical erase unit contains the minimum number of memory cells to be erased together. Entity programming unit is the smallest unit of programming. That is, the entity programming unit is the smallest unit for writing data. Each physical programming unit generally includes a data bit area and a redundant bit area. The data bit area contains a plurality of physical access addresses for storing user data, and the redundant bit area is used for storing system data (eg, control information and error correction code). In this exemplary embodiment, the data bit area of each physical programming unit includes 4 physical access addresses, and the size of one physical access address is 512 bytes. However, in other exemplary embodiments, the data bit area may also include more or less physical access addresses, and the present invention does not limit the size and number of physical access addresses. For example, in an exemplary embodiment, the physical erasing unit is a physical erasing unit, and the physical programming unit is a physical programming unit or a physical sector, but the invention is not limited thereto.

In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell (Multi LevelCell, MLC for short) NAND flash memory module (that is, a flash memory that can store 2 bits of data in a storage unit) memory module). However, the present invention is not limited thereto, and the rewritable non-volatile memory module 106 may also be a single-level cell (Single Level Cell, SLC for short) NAND flash memory module (that is, one bit of data can be stored in one storage unit). flash memory module), triple-level cell (Trinary Level Cell, TLC for short) NAND flash memory module (that is, a flash memory module that can store 3 bits of data in a storage unit), other flash memory modules or Other memory modules with the same characteristics.

FIG. 3 is a schematic block diagram of a memory control circuit unit according to a first exemplary embodiment of the present invention.

Referring to FIG. 3 and FIG. 2 , the memory control circuit unit 104 includes a memory management circuit 202 , a host interface 204 and a memory interface 206 .

The memory management circuit 202 is used to control the overall operation of the memory control circuit unit 104 . Specifically, the memory management circuit 202 has a plurality of control instructions, and when the memory storage device 100 is operating, these control instructions are executed to perform operations such as writing, reading, and erasing data.

In this exemplary embodiment, the control instructions of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are written into the read-only memory. When the memory storage device 100 is in operation, these control instructions will be executed by the microprocessor unit to perform operations such as writing, reading and erasing data.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be stored in a specific area of the rewritable non-volatile memory module 106 in the form of program codes (for example, a system dedicated to storing system data in the memory module) area). In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the read-only memory has a driver code, and when the memory control circuit unit 104 is enabled, the microprocessor unit will first execute the driver code segment to store the data stored in the rewritable non-volatile memory module 106 The control instructions are loaded into the random access memory of the memory management circuit 202 . Afterwards, the microprocessor unit will execute these control instructions to perform operations such as writing, reading and erasing data.

The host interface 204 is coupled to the memory management circuit 202 and configured to be coupled to the connection interface unit 102 for receiving and identifying instructions and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 conforms to the SATA standard. However, it must be understood that the present invention is not limited thereto, and the host interface 204 may also be compatible with PATA standard, IEEE1394 standard, PCI Express standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 206 is coupled to the memory management circuit 202 and used for accessing the rewritable non-volatile memory module 106 . That is to say, the data to be written into the rewritable nonvolatile memory module 106 will be converted into a format acceptable to the rewritable nonvolatile memory module 106 via the memory interface 206 .

In an exemplary embodiment of the present invention, the memory control circuit unit 104 further includes a buffer memory 208 , a power management circuit 210 and an error checking and correction circuit 212 .

The buffer memory 208 is coupled to the memory management circuit 202 and used for storing data and instructions from the host system 1000 or data from the rewritable non-volatile memory module 106 .

The power management circuit 210 is coupled to the memory management circuit 202 and used for controlling the power of the memory storage device 100 .

The error checking and correcting circuit 212 is coupled to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. Specifically, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correcting circuit 212 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code) for the data corresponding to the write command. , ECC Code for short), and the memory management circuit 202 will write the data corresponding to the write command and the corresponding ECC code into the rewritable non-volatile memory module 106 . Afterwards, when the memory management circuit 202 reads data from the rewritable non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 212 will read the error checking and correction code according to the error checking and correction code. The correction code performs error checking and correction procedures on the read data.

FIG. 4A and FIG. 4B are exemplary schematic diagrams of a management entity erasing unit according to the first exemplary embodiment.

It must be understood that when describing the operation of the physical erasing unit of the rewritable non-volatile memory module 106, words such as "extract", "group", "divide", and "associate" are used to operate the physical erase. A unit is a logical concept. That is to say, the actual position of the physical erasing unit of the rewritable non-volatile memory module is not changed, but the physical erasing unit of the rewritable non-volatile memory module is logically operated.

Please refer to FIG. 4A, the memory control circuit unit 104 (or the memory management circuit 202) will logically group the entity erasing units 410(0)-410-(N) into a data area 502, an idle area 504, a system area 506, and a replacement area. District 508.

The physical erase units logically belonging to the data area 502 and the free area 504 are used to store data from the host system 1000 . Specifically, the physical erasing unit of the data area 502 is a physical erasing unit regarded as stored data, and the physical erasing unit of the spare area 504 is a physical erasing unit used to replace the data area 502 . That is to say, when receiving the write command and the data to be written from the host system 1000, the memory management circuit 202 will extract the physical erase unit from the spare area 504, and write the data into the extracted physical erase unit. In the unit, replace the physical erasing unit of the data area 502.

The physical erase unit logically belonging to the system area 506 is used to record system data. For example, the system data includes the manufacturer and model of the rewritable non-volatile memory module, the number of physical erasing units of the rewritable non-volatile memory module, the number of physical programming units of each physical erasing unit, etc. .

The physical erase units logically belonging to the replacement area 508 are used in the bad physical erase unit replacement process to replace the damaged physical erase units. Specifically, if there are still normal physical erasing units in the replacement area 508 and the physical erasing units in the data area 502 are damaged, the memory management circuit 202 will extract normal physical erasing units from the replacement area 508 to replace the damaged ones. The physical erasing unit.

In particular, the number of physical erasing units in the data area 502 , the spare area 504 , the system area 506 and the replacement area 508 will vary according to different memory specifications. In addition, it must be understood that during the operation of the memory storage device 100 , the grouping relationship of the physical erasing unit associated with the data area 502 , the spare area 504 , the system area 506 and the replacement area 508 will change dynamically. For example, when the physical erasing unit in the spare area 504 is damaged and replaced by the physical erasing unit in the replacement area 508 , the original physical erasing unit in the replacement area 508 will be associated with the spare area 504 .

Referring to FIG. 4B , as mentioned above, the physical erasing units of the data area 502 and the spare area 504 store the data written by the host system 1000 in an alternate manner. In this exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) configures logical addresses 510(0)-510(D) to the host system 1000 to map to some physical erase units in the data area 502 414(0)-410(F-1), to facilitate data access in the physical erasing units that store data in the aforementioned alternate manner. In particular, the host system 1000 accesses the data in the data area 502 through logical addresses 510(0)˜510(D). In addition, the memory control circuit unit 104 (or the memory management circuit 202) will establish a logical address-physical erasing unit mapping table (logical address-physical erasing unit mapping table) to record the mapping relationship between the logical address and the physical erasing unit . The logical address-physical erasing unit mapping table can also, for example, record the mapping relationship between the logical address and the physical programming unit, the logical programming unit and the physical programming unit, and/or the logical programming unit and the physical erasing unit, etc. The correspondence between various logics and entities is not limited by the present invention.

5A to FIG. 5B show writing data, error checking and correction codes corresponding to the writing data, and at least one mark for recording parity information into the physical programming device according to the first exemplary embodiment of the present invention. An example schematic of a unit.

Please refer to FIG. 5A , in this exemplary embodiment, each physical programming unit includes a data bit area 520 and a redundant bit area 540 . Wherein, the redundant bit area 540 includes a first recording area 542 and a second recording area 544 . For example, when the capacity of a physical programming unit is 8 kilobytes (Kilobyte, KB for short), the capacity of the redundant bit area 540 is 22 bytes.

Specifically, when the host system 1000 sends the write command and the first user data D1 corresponding to the write command to the memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) will determine that the first user The size of the data D1, and according to the size of the first user data D1, the number of physical programming units required to write the first user data D1 is obtained. Here, it is assumed that two entity programming units are required to write the first user data D1. Therefore, as shown in FIG. 5A, the memory control circuit unit 104 (or the memory management circuit 202) will generate error checking and correction codes ECC1-1 and ECC1-2 corresponding to the first user data D1-1 and D1-2 and corresponding The management information S1-1 and S1-2 of the first user data D1-1 and D1-2 (for example, the good and bad marks of the entity programming unit, etc.), and extract the entity erasing unit 410 (F) from the spare area 504 Erasing unit as a replacement entity. Afterwards, the memory control circuit unit 104 (or the memory management circuit 202) will check these first user data, management information corresponding to these first user data, and multiple error checks corresponding to these first user data The calibration code and the correction code are sequentially written into the 0th and 1st physical programming units of the physical erasing unit 410(F). It is assumed here that the entity programming unit in which the first user data is written is the first entity programming unit 602, that is, the first user data D1-1 and D1-2 are programmed into the first entity programming unit 602. In the data bit area 520 of the physical programming unit 602, the error checking and correction codes ECC1-1 and ECC1-2 corresponding to the first user data are programmed to the redundancy ratio in the first physical programming unit 602 The second recording area 544 of the special zone 540 . Especially, when the host system 1000 intends to read the first user data D1 from the memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) will read the error checking data from the first physical programming unit 602 and correction codes ECC1-1 and ECC1-2, and the error checking and correction circuit 212 will perform the first user data D1-1 and D1-2 according to the error checking and correction codes ECC1-1 and ECC1-2 respectively Error checking and correction procedures. Based on this, within the scope of the error correction capability of the ECC circuit 212 , the ECC circuit 212 can correct erroneous bits in the data, thereby ensuring the correctness of the data.

In this exemplary embodiment, it is assumed that a first data includes first user data and management information corresponding to the first user data. Therefore, when the memory storage device 100 receives the first user data and generates the corresponding first user data After the management information S1-1 and S1-2 of user data D1-1 and D1-2, the memory control circuit unit 104 (or memory management circuit 202) will and D1-2 and management information S1-1 and S1-2 corresponding to the first user data D1-1 and D1-2) to generate a parity information P. In addition, in another exemplary embodiment, the first data includes user data, management information corresponding to the user data, and error checking and correction codes corresponding to the user data, that is, the memory control circuit unit 104 (or memory The management circuit 202) will generate parity information according to the entire physical programming unit, for example, the memory control circuit unit 104 (or the memory management circuit 202) will correspond to the first user according to the first user data D1-1 and D1-2 The management information S1-1 and S1-2 of the data D1-1 and D1-2 and the error checking and correction codes ECC1-1 and ECC1-2 corresponding to the first user data D1-1 and D1-2 generate parity information. It is worth mentioning that, in this exemplary embodiment, the first data is composed of two pieces of first user data and management information corresponding to these first user data (that is, the first user data D1-1 and D1-2 and management information S1-1 and S1-2 corresponding to the first user data D1-1 and D1-2), however, the present invention does not limit the size of the first data, for example, in another example In an embodiment, the first data may be composed of one or more first user data and management information corresponding to the first user data, or may be composed of one or more first user data, corresponding to the first user data The user data management information and the error checking and correction code corresponding to the first user data. It is worth noting that the present invention does not limit the generation time and method of parity information. Specifically, in this exemplary embodiment, the generated parity information can be parity checking code (parity checking code), channel coding ( channel coding) or other types. For example, Hamming code (hamming code), low density parity check code (low density parity check code, LDPC code for short), turbo code (turbo code) or Reed-Solomon code (Reed-solomon code, RS code for short). In particular, in another exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202 ) may also use an exclusive OR (XOR) operation to generate the parity information for the first data.

Please refer to FIG. 5A again, the memory control circuit unit 104 (or the memory management circuit 202) will program the parity information P to the second physical programming unit ( That is, the second entity programming unit 604). It is worth mentioning that, in the above-mentioned programming of the first user data, the management information corresponding to the first user data, and the error checking and correction code corresponding to the first user data into the first entity in the entity programming unit During the operation of the programming unit 602, the memory control circuit unit 104 (or the memory management circuit 202) will program at least one flag into the redundant bit area of the first physical programming unit of the physical erasing unit 410(F). The first recording area 542 (ie, the first mark M1 shown in FIG. 5A ), and this first mark M1 will indicate that the parity information P is programmed to the second physical programming unit 604 of the physical erasing unit 410 (F) middle.

In particular, the second physical programming unit 604 is arranged after the last physical programming unit of the first physical programming unit 602 , and the first marker M1 indicates the second physical programming unit 604 to store the parity information P.

Referring to FIG. 5B, when the host system 1000 sends another write command and the second user data D2 corresponding to the write command to the memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) will also judge The size of the second user data D2, and according to the size of the second user data D2, the number of physical programming units required to write the second user data D2 is obtained. Here, it is assumed that a physical programming unit is required to write the second user data D2. Therefore, as shown in FIG. 5B , the memory management circuit 202 generates the error checking and correction code ECC2 corresponding to the second user data D2 and the management information S2 corresponding to the second user data D2 . Afterwards, the memory control circuit unit 104 (or the memory management circuit 202) will write the second user data, the management information corresponding to the second user data, and the error checking and correction code corresponding to the second user data to the third physical programming unit (ie, the third physical programming unit 606 ) of the physical erasing unit 410 (F). When the memory control circuit unit 104 (or the memory management circuit 202) writes the management information S2 corresponding to the second user data D2 into the third physical programming unit 606 of the physical erasing unit 410(F), the memory The control circuit unit 104 (or the memory management circuit 202) will program a second mark M2 into the first recording area 542 of the redundant bit area 540 of the third physical programming unit 606, wherein the third physical programming unit 606 is arranged after the second physical programming unit 604, and the second mark M2 also indicates that the second physical programming unit 604 stores the parity information P.

Thereafter, when the memory control circuit unit 104 (or the memory management circuit 202) receives the read instruction to read the first user data D1 sent by the host system 1000, the memory control circuit unit 104 (or the error checking and correction The circuit 212) performs the above-mentioned error checking and correction procedure on the read first user data D1-1 and D1-2 according to the read error checking and correction code. For example, in an exemplary embodiment of the present invention, the above-mentioned first data includes a second data and an error checking and correction code, wherein the second data may only include the first user data, or include the first user data at the same time The data and the management information corresponding to the first user data, and the error checking and correction code is the error checking and correction code corresponding to the first user data. When the second data cannot be corrected by using the error checking and correction code corresponding to the first user data, the memory control circuit unit 104 (or the memory management circuit 202) will obtain at least one piece of record parity information according to the above-mentioned at least one mark The addresses of the second physical programming units are read, parity information is read from at least one second physical programming unit, and the second data is corrected according to the read parity information. For example, if the first user data D1-1 and D1-2 cannot be corrected by using the error checking and correction codes (ie, ECC1, ECC2) of the first user data D1-1 and D1-2, the memory control circuit The unit 104 (or the memory management circuit 202) will obtain the address of the second physical programming unit 604 that records the parity information P according to the above-mentioned at least one mark, and read the parity information P from the second physical programming unit 604 and Correct the first user data D1 according to the read first parity information P. For example, when the first user data D1-1 cannot be corrected by using the error checking and correction code ECC1 of the first user data D1-1, the memory control circuit unit 104 (or the memory management circuit 202) will first The physical programming unit adjacent to the 0th physical programming unit in the physical programming unit 602 where the first user data D1-1 is located (for example, the 1st physical programming unit of the physical erasing unit 410(F)) Obtain the first mark M1 in, and thus identify the address where the parity information P is stored. In another exemplary embodiment, if the first user data D1-2 cannot be corrected by using the error checking and correction code ECC2 of the first user data D1-2 and cannot be obtained from the error code corresponding to the first user data D1-2 When the first recording area of the redundant bit area obtains the first mark value M1, the memory control circuit unit 104 (or the memory management circuit 202) will start from the first entity program adjacent to the first user data D1-2. In the physical programming unit of the physical erasing unit (for example, the 0th physical programming unit of the physical erasing unit 410(F), the second physical programming unit 604 and the third physical programming unit 606) to obtain the The second mark M2 in the physical programming unit 606 identifies the address of the physical programming unit storing the parity information P.

In this exemplary embodiment, the rewritable non-volatile memory module 106 is a multi-level cell MLC NAND flash memory module, so each memory cell can store multiple bits. Specifically, when programming the memory cells of the SLC NAND flash memory module, only a single layer of programming can be performed, so each memory cell can only store one bit. The programming of the physical erasing unit of the MLC NAND flash memory module can be divided into multiple layers. For example, taking a 2-layer storage unit as an example, the programming of the entity programming unit can be divided into two stages. The first stage is the writing part of the lower entity programming unit. Its physical characteristics are similar to single-layer storage unit SLC NAND flash memory. After the first stage is completed, the upper entity programming unit will be programmed. The lower entity programming unit The writing speed of the unit will be faster than that of the programmatic unit above. Therefore, the physical programming units of each physical erase unit can be divided into slow physical programming units (ie, upper physical programming units) and fast physical programming units (ie, lower physical programming units).

6 is another example of writing write data, error checking and correction codes corresponding to the write data, and at least one mark for recording parity information into the physical programming unit according to the first exemplary embodiment of the present invention. An example schematic.

In another exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202 ) may also convert the first user data D1-1 and D1-2, and the data corresponding to the first user data D1-1 and D1-2 The management information S1-1 and S1-2 and the error checking and correcting codes ECC1-1 and ECC1-2 are programmed into a plurality of physical programming units among the physical programming units. For example, the memory control circuit unit 104 (or the memory management circuit 202) will store the first user data D1-1 and D1-2, and the management information S1-1 and S1 corresponding to the first user data D1-1 and D1-2 -2 and the ECC codes ECC1-1 and ECC1-2 corresponding to the first user data D1-1 and D1-2 are only programmed to the fast physical programming unit in the first physical programming unit 702. Therefore, as shown in FIG. 6, the memory control circuit unit 104 (or the memory management circuit 202) will program the first user data D1-1, the management information S1-1 and the error checking and correction code ECC1-1 to the physical memory. The 0th entity programming unit of the division unit 410(F), and program the first user data D1-2, the management information S1-2, the first mark M1 and the error checking and correction code ECC1-2 to the entity wipe The second physical programming unit of the division unit 410(F). In addition, the memory control circuit unit 104 (or memory management circuit 202) will generate corresponding to the first user data D1-1, D1-2 and management information S1-1 corresponding to the first user data D1-1, D1-2 1. The parity information P of S1-2, and write this parity information P into the fast physical programming unit in the second physical programming unit 704 (that is, the fourth physical program of the physical erasing unit 410 (F) unit). Afterwards, when the host system 1000 sends another write command and the second user data D2 corresponding to the write command to the memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) will send the generated The error checking and correction code ECC2 corresponding to the second user data D2, the management information S2 corresponding to the second user data D2, and a second mark M2 are written into the third physical programming unit of the physical erasing unit 410(F). The fast physical programming unit in 706 (ie, the 6th physical programming unit of the physical erasing unit 410(F)). Here, similar to the example shown in FIG. 5A and FIG. 5B , both the first mark M1 and the second mark M2 indicate that the fast physical programming unit in the second physical programming unit 704 stores parity information P.

That is to say, in this exemplary embodiment, if the first user data D1-1 cannot be corrected by using the error checking and correction code ECC1 of the first user data D1-1, the memory control circuit unit 104 (or the memory The management circuit 202) first selects the fast physical programming unit (for example, the physical erasing unit 410 (F ) in the second physical programming unit) to obtain the first mark M1, and thereby identify the address where the parity information P is stored. In another exemplary embodiment, if the first user data D1-2 cannot be corrected by using the error checking and correction code ECC1-2 of the first user data D1-2 and cannot be obtained from the error code corresponding to the first user data D1 When the first recording area of the redundant bit area of -2 obtains the first mark value M1, the memory control circuit unit 104 (or the memory management circuit 202) will start from the second one close to the first user data D1-2. Fast physical programming unit of physical programming unit (for example, 0th physical programming unit of physical erasing unit 410(F), 4th physical programming unit of physical erasing unit 410(F) and physical erasing In the 6th physical programming unit of unit 410 (F), search to obtain the second mark M2 in the fast physical programming unit of the third physical programming unit 706, and thus identify the address for storing the parity information P .

It is worth mentioning that, in this exemplary embodiment, since the physical programming unit used to record the address of the physical programming unit to which the parity information belongs is the physical program located before and after the physical programming unit to which the parity information belongs, respectively Therefore, if one of the physical programming units used to record the address of the physical programming unit to which the parity information belongs is damaged (that is, the data recorded in the data bit area and the redundant bit area in the physical erasing unit When the recorded marks and error checking and correction codes are lost or damaged), the memory control circuit unit 104 (or the memory management circuit 202) can also be programmed by another entity adjacent to or close to the data read by this pen Unit to identify the address of the physical programming unit to which the parity information belongs. Accordingly, when the data cannot be corrected by the error checking and correction code, the address of the parity information storing the data can be effectively identified and the parity information is obtained through the mark stored in the physical programming unit, thereby using the The acquired parity information is used to correct erroneous bits in the data.

Fig. 7 is a flowchart of a data storage method according to the first exemplary embodiment of the present invention.

Please refer to FIG. 7 , in step S701 , the memory control circuit unit (or memory management circuit) generates parity information according to a first data. In step S703, the memory control circuit unit (or memory management circuit) programs the first data to the first physical program unit. Next, in step S705, the memory control circuit unit (or memory management circuit) will program at least one flag to the redundant bit area in the first physical programming unit, and in step S707, the memory control circuit The unit (or memory management circuit) programs the parity information into at least one second physical programming unit arranged after the first physical programming unit, wherein the at least one flag indicates that the parity information is programmed into the at least one second entity programming unit.

[Second Exemplary Embodiment]

The memory storage device and the host system of the second exemplary embodiment of the present invention are essentially the same as the memory storage device and the host system of the first exemplary embodiment, wherein the difference lies in the memory control circuit unit (or memory management circuit) of the second exemplary embodiment ) will establish a parity information address correspondence table, and simultaneously use the physical programming unit and parity information address correspondence table to record a physical programming unit address to which the parity information belongs. The differences between the second exemplary embodiment and the first exemplary embodiment will be described below using the device structures of FIG. 1A , FIG. 2 and FIG. 3 .

8A and FIG. 8B show writing data, error checking and correction codes corresponding to the writing data, and at least one mark for recording parity information into the physical programming device according to the second exemplary embodiment of the present invention. An example schematic of a unit.

Please refer to FIG. 8A and FIG. 8B, wherein the first user data shown in FIG. 8A, the error checking and correction code corresponding to the first user data, the first mark for recording the address of the parity information, and the first mark corresponding to the first user data The method for writing the parity information of user data and its management information into the physical programming unit is the same as that shown in FIG. 5A , and will not be repeated here. The difference is that in this exemplary embodiment, the first user data D1-1 and D1-2 and the error checking and correction code ECC1-1 corresponding to the first user data D1-1 and D1-2 and ECC1-2 are programmed into the first entity programming unit 602 among the entity programming units, and will correspond to the first user data D1-1 and D1-2 and the first user data D1-1 and D1-2 The management information S1-1 and the parity information P of S1-2 are programmed into the operation of the second physical programming unit 604 among the physical programming units, the memory control circuit unit 104 (or the memory management circuit 202) will establish a Parity information address correspondence table 800 (as shown in FIG. 8B ). For example, the parity information address correspondence table 800 will be stored in the buffer memory 208 or the random access memory 1104 . In particular, the memory control circuit unit 104 (or the memory management circuit 202) will record the third mark M3 in the parity information address correspondence table 800, wherein the third mark M3 will also indicate that the second entity programming unit 604 stores the parity information p.

In this exemplary embodiment, the first user data D1-1 and D1-2 and the error checking and correction code ECC1-1 corresponding to the first user data D1-1 and D1-2 are combined as shown in FIG. 8A ECC1-2 is programmed to the first physical programming unit 602 among the physical programming units, and the parity information P corresponding to the first user data D1-1 and D1-2 and its management information S1-1 and S1-2 After being programmed into the operation of the second physical programming unit 604 among the physical programming units, the host system 1000 sends another write command and the second user data D2 corresponding to the write command to the memory storage device 100 . At this time, if the memory control circuit unit 104 (or the memory management circuit 202) puts the second user data, the management information corresponding to the second user data, and the indicating parity information P in the second physical programming unit 604 Before the three-mark M3 and the error checking and correction code corresponding to the second user data are written into the third physical programming unit 606, when the host system 1000 or the memory storage device 100 is powered off, it will cause the location where the parity information P is recorded. The third tag M3 of the address cannot be written into the third physical programming unit 606 , or the data in the first physical programming unit 602 is lost or damaged.

In the case that the above-mentioned third entity programming unit 606 arranged after the second entity programming unit 604 is an empty entity unit or the data in the first entity programming unit 602 is lost or damaged due to power failure, and when When the memory control circuit unit 104 (or the memory management circuit 202) receives the read instruction to read the first user data D1-1 and D1-2 sent by the host system 1000, the memory management circuit 202 (or the error checking The AND correction circuit 212) performs the above error checking and correction procedure on the read first user data D1-1 and D1-2 according to the read ECC code. If the first user data D1-1 and D1-2 cannot be corrected by using the error checking and correction codes (ie, ECC1-1, ECC1-2) of the first user data D1-1 and D1-2, the memory The control circuit unit 104 (or the memory management circuit 202) will also be used to obtain the address of the second physical programming unit 604 that records the parity information P according to the above at least one flag, and read from the second physical programming unit 604 The parity information P and the first user data D1-1 and D1-2 are corrected according to the read parity information P. For example, the memory management circuit 202 will first determine whether the first recording area corresponding to the redundant bit area of the first user data D1-2 in the read physical erasing unit 410(F) has the first mark M1 , if the first mark M1 exists and the address of the parity information P can be known through it, the memory control circuit unit 104 (or the memory management circuit 202) will correct the first user data D1-1 according to the parity information P or D1-2. Conversely, if the first mark M1 does not exist or the redundant bit area for recording the first mark M1 is damaged, the memory management circuit 202 will read the above parity information address correspondence table 800 and according to the first parity information address correspondence table 800 The three-mark M3 obtains the address of the physical programming unit where the parity information P is located.

[Third Exemplary Embodiment]

The memory storage device and the host system of the third exemplary embodiment of the present invention are essentially the same as the memory storage device and the host system of the first exemplary embodiment, wherein the difference lies in the memory control circuit unit (or memory management circuit) of the third exemplary embodiment ) will record the tag value in these physical programming units according to the number of physical programming units that need to be written for each write data, and use these tag values to obtain the physical programming unit to which the parity information belongs address. The differences between the third exemplary embodiment and the first exemplary embodiment will be described below using the device structures of FIG. 1A , FIG. 2 and FIG. 3 .

Similar to the first exemplary embodiment, when the host system 1000 sends the write command and the first user data D1 corresponding to the write command to the memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) will determine The size of the first user data D1, and according to the size of the first user data D1, the number of physical programming units required to write the first user data D1 is obtained. Here, it is assumed that four physical programming units are required to write the first user data D1. In this example, the memory control circuit unit 104 (or the memory management circuit 202) generates error checking and correction codes ECC1-1˜ECC1-4 corresponding to the first user data D1-1˜D1-4 and corresponding to the first user data D1-1˜ECC1-4. management information S1-1 to S1-4 of user data D1-1 to D1-4. In particular, when the memory control circuit unit 104 (or the memory management circuit 202 ) receives the first user data D1, it will not immediately write the first user data D1 into the physical erasing unit. For example, the memory control circuit unit 104 (or the memory management circuit 202) will continue to wait for the host system 1000 to send other write commands and the second user data D2 and third user data D3 corresponding to these commands to the memory storage device 100, and count the number of physical programming units that need to be written into the second user data D2 and the third user data D3. It is assumed here that the memory control circuit unit 104 (or the memory management circuit 202 ) in this exemplary embodiment will generate a parity information for the data in the three physical programming units after every three physical programming units are written. In this exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) will determine that the number of physical programming units required to write the second user data D2 and the third user data D3 is two. , and the memory control circuit unit 104 (or the memory management circuit 202) will also write each piece of data according to the number of physical programming units that need to be written into each piece of data and the order in which each piece of data is received. Such data of the entity programmatic units are sorted in the order shown as sorting 900 in FIG. 9 .

In another exemplary embodiment, after writing more than three or less than three physical programming units, a parity information may be generated for the data in more than three or less than three physical programming units. The invention is not limited. In addition, the memory control circuit unit 104 (or the memory management circuit 202 ) waits for other write commands sent by the host system 1000 and the number of data corresponding to these commands is not limited to three.

FIG. 9 is an example of arranging and recording tag values according to the number of each physical programming unit to be written in according to the third exemplary embodiment of the present invention, and FIG. 10 is an example according to the third exemplary embodiment of the present invention. Another exemplary schematic diagram of writing write data, ECC codes corresponding to the write data, and at least one mark for recording parity information into the physical programming unit shown in the three exemplary embodiments.

Please refer to FIG. 9, as mentioned above, since the memory control circuit unit 104 (or the memory management circuit 202) will generate a parity information for the data in every three physical programming units after writing every three physical programming units Therefore, the memory control circuit unit 104 (or the memory management circuit 202 ) will further record a tag value for the data to be written into each physical programming unit according to the sorting 900 . Specifically, the tag value of the first user data D1-1 will be recorded as 3, the tag value of the first user data D1-2 will be recorded as 2, and the tag value of the first user data D1-3 will be is recorded as 1, the tag value of the first user data D1-4 will be recorded as 3, and the tag value of the second user data D2-1 will be recorded as 2 and the tag value of the second user data D2-2 The value will be recorded as 1. In particular, there are only two physical programming units to be written into the rest of the third user data D3, therefore, the memory management circuit 202 will record the flag value of the third user data D3-1 as 2 and The flag value of the third user data D3-2 is recorded as 1.

Afterwards, the memory control circuit unit 104 (or the memory management circuit 202) will extract the physical erasing unit 410 (F+1) from the free area 504 as a replacement physical erasing unit, and according to the sequence shown in FIG. Data, management information corresponding to the data, and error checking and correction codes corresponding to the data are sequentially written into the physical erasing unit 410 (F+1).

Please refer to FIG. 10, the memory control circuit unit 104 (or the memory management circuit 202) will combine the first user data D1-1~D1-3 with the management information S1-1~S1-3 corresponding to these first user data , and a plurality of error checking and correction codes ECC1-1~ECC1-3 corresponding to the first user data are sequentially written into the 0th to 2nd entities of the physical erasing unit 410 (F+1) In the programming unit, the memory control circuit unit 104 (or the memory management circuit 202) writes the management information S1-1～S1-3 corresponding to the first user data D1-1～D1-3 into the physical erasing unit 410 At the same time as the first recording area in the redundant bit area of the 0th to the 2nd entity programming unit in (F+1), the memory control circuit unit 104 (or the memory management circuit 202) will also The tag values recorded in user data D1-1~D1-3 are recorded in the first recording area corresponding to the redundant bit area of the physical programming unit of the first user data D1-1~D1-3 value. In addition, the memory control circuit unit 104 (or the memory management circuit 202) will generate the management information S1- The first parity information P1 of 1 to S1-3. For example, it is assumed here that the 0th to 2nd physical programming units in the physical erasing unit 410 (F+1) written by the first user data D1-1˜D1-3 are the first physical program unit 802, then the memory management circuit 202 will write the parity information P1 corresponding to the first user data D1-1～D1-3 and its management information S1-1～S1-3 into the physical erasing unit 410 (F +1) in the third physical programming unit, here it is assumed that the third physical programming unit in the physical erasing unit 410 (F+1) is the second physical programming unit 804, that is, the memory control circuit unit 104 (or the memory management circuit 202) will write and arrange the first parity information P1 corresponding to the first user data D1-1~D1-3 and its management information S1-1~S1-3 in the first entity programming unit The second physical programming unit 804 after the last physical programming unit in 802 (ie, the second physical programming unit in the physical erasing unit 410 (F+1)). And, by analogy, the memory control circuit unit 104 (or the memory management circuit 202) will successively use the first user data D1-4, the second user data D2-1 and the second user data according to the sequence 900 in FIG. The data D2-2 is a group, and the three management information, three error checking and correction codes and parity information corresponding to the data to be written into the three physical programming units are respectively and sequentially written into the physical erasing In the third entity programming unit 806 and the fourth entity programming unit 808 in the unit 410 (F+1). In particular, since the number of physical programming units to be written into the rest of the third user data D3 is 2, the memory control circuit unit 104 (or the memory management circuit 202) only uses the third user data D3-1 It is a group with the third user data D3-2, and two management information, two error checking and correction codes and parity information corresponding to the data to be written into the two entity programming units are separately and sequentially Write into the fifth physical programming unit 810 and the sixth physical programming unit 812 in the physical erasing unit 410 (F+1).

Specifically, the value of the first flag in the first physical programming unit 802, the third physical programming unit 806, and the fifth physical programming unit 810 respectively located in the physical erasing unit 410 (F+1) is 1. The second flag has a value of 2 and the third flag has a value of 3. Please refer to FIG. 10 again, the first tag value will be recorded in the last physical programming unit in the first physical programming unit 802 (that is, the second physical program in the physical erasing unit 410 (F+1) programming unit), the second tag value will be recorded in the physical programming unit adjacent to and arranged before the last physical programming unit in the first physical programming unit 802 (i.e. , in the redundant bit area of the first physical programming unit in the physical erasing unit 410 (F+1), and the third mark value will be recorded in the first physical programming unit 802 adjacent and arranged In the redundant bit area of the physical programming unit (that is, the 0th physical programming unit in the physical erasing unit 410(F+1)) before the physical programming unit recording the second tag value. And, by analogy, the tag values in the third entity programming unit 806 will be sorted in the arrangement shown in FIG. 10 . It is worth mentioning that the third user data D3 only needs to be written into two physical programming units, therefore, there are only the first tag value and the second tag value in the fifth physical programming unit 810 .

Afterwards, if the memory control circuit unit 104 (or the memory management circuit 202) receives the read command sent by the host system 1000 to read the above-mentioned first user data D1, the memory management circuit 202 (or the error checking and correction circuit) 212) Perform the above error checking and correction procedure on the read first user data D1 according to the read error checking and correction code. If the first user data D1-1 to D1-4 cannot be corrected by using the error checking and correction codes (that is, ECC1-1 to ECC1-4) of the first user data D1-1 to D1-4, the memory The control circuit unit 104 (or the memory management circuit 202 ) will obtain the address of the physical programming unit recording the first parity information P1 and the second parity information P2 according to the above at least one flag value. It is assumed here that when the first user data D1-2 cannot be corrected by using the error checking and correction code ECC1-2 of the first user data D1-2 and cannot be obtained from the redundancy corresponding to the first user data D1-2 When the first recording area of the bit area obtains the second mark value, the memory control circuit unit 104 (or the memory management circuit 202) will obtain the second mark value from the first physical programming unit 802 adjacent to the first user data D1-2. At least one flag value is obtained in the physical programming unit of the physical programming unit (for example, the 0th or the 2nd physical programming unit of the physical erasing unit 410 (F+1)). Assuming that the memory control circuit unit 104 (or the memory management circuit 202) obtains the flag value of its redundant bit area from the second physical programming unit in the first physical programming unit 802, then the memory control circuit unit 104 (or the memory management circuit 202) will determine that the address of the first parity information P1 corresponding to the first user data D1-1˜D1-3 is the last one adjacent to the first physical programming unit 802 The physical programming unit of the physical programming unit (that is, the second physical programming unit 804), and the memory control circuit unit 104 (or the memory management circuit 202) will read the first parity information P1 and according to the read first parity information P1 A parity information P1 is used to correct the first user data D1. In addition, assuming that the memory control circuit unit 104 (or the memory management circuit 202) can also obtain the flag value of its redundant bit area from the 0th physical programming unit 802 in the first physical programming unit 802, then the memory control circuit The unit 104 (or the memory management circuit 202) will determine that the address where the first parity information P1 corresponding to the first user data D1-1˜D1-3 is located is the distance itself (that is, the address in the first entity programming unit 802 The second entity programming unit 804 of the 0th entity programming unit) of the 3 entity programming units. Next, the memory control circuit unit 104 (or the memory management circuit 202 ) reads the first parity information P1 and corrects the first user data D1 according to the read first parity information P1 . Accordingly, if the data corresponding to each materialized program unit cannot be corrected through the respective error checking and correction codes, or the area part for recording the tag value corresponding to the data in each materialized program unit When damaged, the memory control circuit unit 104 (or the memory management circuit 202) can obtain the tag value used to indicate the address of the parity information according to the adjacent entity programming unit, thereby effectively preventing the read data from occurring. Conditions that cannot be corrected.

[Fourth Exemplary Embodiment]

The memory storage device and the host system of the fourth exemplary embodiment of the present invention are essentially the same as the memory storage device and the host system of the first exemplary embodiment, wherein the difference lies in the memory control circuit unit (or memory management circuit) of the fourth exemplary embodiment ) will establish a parity information address correspondence table, and use the parity information address correspondence table to record the physical programming unit address to which each parity information belongs. The differences between the fourth exemplary embodiment and the first exemplary embodiment will be described below using the device structures of FIG. 1A , FIG. 2 and FIG. 3 .

FIG. 11 shows programming of write data, error checking and correction codes corresponding to the write data to the physical programming unit, and recording at least one mark for recording parity information according to a fourth exemplary embodiment of the present invention. An example schematic diagram of the parity information address correspondence table.

Please refer to FIG. 11 , the method shown in FIG. 11 for writing the first user data, the error checking and correction code corresponding to the first user data, and the parity information corresponding to the first user data into the entity programming unit It is the same as the method shown in FIG. 5A and FIG. 5B in the first exemplary embodiment, and will not be repeated here. The difference is that, in this exemplary embodiment, the memory control circuit unit 104 (or the memory management circuit 202) will first establish a parity information address correspondence table 110, and the parity information address correspondence table 110 will be stored in the buffer memory 208 or random access memory 1104. And in the memory control circuit unit 104 (or memory management circuit 202), the first user data D1-1 and D1-2, the management information S1-1 and S1-2 corresponding to the first user data D1-1 and D1-2 2 and the error checking and correction codes ECC1-1 and ECC1-2 corresponding to the first user data D1-1 and D1-2 are programmed into the first physical programming unit 602 among the physical programming units, and the corresponding second A user data D1-1 and D1-2 and the first parity information P1 of the management information S1-1 and S1-2 are programmed into the operation of the second physical programming unit 604 among the physical programming units, the memory The control circuit unit 104 (or the memory management circuit 202) will not program the first mark M1 for recording the address of the first parity information P1 to at least one of the physical programming units in the first physical programming unit 602, but It is to record the first mark M1 in the previously created parity information address correspondence table 110 . In another exemplary embodiment, if the host system 1000 sends a write command and the second user data D2 corresponding to the write command to the memory storage device 100, the memory control circuit unit 104 (or the memory management circuit 202) will Write the second user data D2 and its generated error checking and correction code ECC2 corresponding to the second user data D2 and the management information S2 corresponding to the second user data D2 into the physical erasing unit 410 (F) In the third physical programming unit 606, in particular, the memory control circuit unit 104 (or the memory management circuit 202) can additionally extract a physical erasing unit 410 (F+1), and will correspond to the second user data D2 The second parity information P2 of its management information S2 is programmed to the first physical programming unit 802 in the physical erasing unit 410 (F+1). In addition, the memory control circuit unit 104 (or memory management circuit 202) will The second mark M2 used to record the address of the second parity information P2 is also recorded in the parity information address correspondence table 110 . It is worth mentioning that, in this exemplary embodiment, there is no restriction on the physical erasing unit where the parity information is stored, that is, the memory control circuit unit 104 (or memory management circuit 202 ) extracts the unit for recording the parity information. The physical erasing unit may also be different from the memory die corresponding to the physical erasing unit where the write data corresponding to the parity information is located. In other words, when the first user data D1-1 or D1-2 cannot be corrected by using the error checking and correction codes ECC1-1, ECC1-2 of the first user data D1-1 and D1-2, the memory control circuit The unit 104 (or the memory management circuit 202) can obtain the first mark M1 of the address recording the first parity information P1 according to the parity information address correspondence table 110, or when the error checking and correction using the second user data D2 cannot be passed When the code ECC2 is used to correct the second user data D2, the memory control circuit unit 104 (or the memory management circuit 202) can obtain the second mark M2 of the address recording the second parity information P2 according to the parity information address correspondence table 110, according to which The memory control circuit unit 104 (or the memory management circuit 202 ) can quickly obtain which physical programming unit the parity information belongs to according to the parity information address correspondence table 110 .

Fig. 12 is a flowchart of a data storage method according to a fourth exemplary embodiment of the present invention.

Please refer to FIG. 12 , in step S1201 , the memory control circuit unit (or memory management circuit) creates a parity information address correspondence table. In step S1203, the memory control circuit unit (or memory management circuit) generates parity information according to the first data. Next, in step S1205, the memory control circuit unit (or memory management circuit) programs the first data into the data bit area of the first physical programming unit. In step S1207, the memory control circuit unit (or memory management circuit) programs the parity information into at least one second physical programming unit. And in step S1209, the memory control circuit unit (or memory management circuit) records at least one mark in the parity information address correspondence table, wherein the at least one mark will indicate that the parity information is programmed into the second Entity programmatic unit.

To sum up, the data storage method, the memory control circuit unit and the memory storage device of the exemplary embodiments of the present invention record the address of the parity information corresponding to the written data in at least one mark while writing the data and Write the at least one mark into at least one physical programming unit where the received data is to be written, so that when there is an error in the data bit read from the rewritable non-volatile memory module, the At least one mark is used to quickly obtain which physical programming unit the parity information belongs to, thereby effectively increasing the correction capability and efficiency of error correction. In addition, the physical programming unit for correcting the parity information of the read data in the exemplary embodiment of the present invention is arranged after the physical programming unit where the written data is located. Based on this, through the exemplary embodiment of the present invention The data storage method does not need to place parity information corresponding to multiple pieces of written data in a fixed memory die in the system, so as to effectively avoid waste of storage space in the memory storage device.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (21)

1. A data storage method, characterized in that, for a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of entity erasing units, and each of these entities erases The unit includes a plurality of physical programming units, wherein each of the physical programming units includes a data bit area and a redundant bit area, and the data storage method includes: generating parity information according to the first data; programming the first data into a first physical programming unit among the physical programming units; and programming the parity information into at least one second physical programming unit among the physical programming units, wherein the at least one second physical programming unit is arranged after the first physical programming unit; Wherein the step of programming the first data into the first physical programming unit among the physical programming units includes: programming at least one tag into the redundancy of the first physical programming unit A bit field, wherein the at least one flag indicates that the parity information is programmed into the at least one second physical programming unit. 2. The data storage method according to claim 1, wherein the first data includes user data and management information corresponding to the user data; Wherein the user data is programmed into the data bit area in the first physical programming unit, wherein the management information corresponding to the user data is programmed into the redundancy ratio in the first physical programming unit sar. 3. The data storage method according to claim 1, wherein the first data includes user data, management information corresponding to the user data, and error checking and correction codes corresponding to the user data; Wherein the error checking and correction code is generated according to the user data; Wherein the user data is programmed into the data bit area in the first physical programming unit, wherein the management information corresponding to the user data is programmed into the redundancy ratio in the first physical programming unit A special zone, wherein the ECC code corresponding to the user data is programmed into a redundant bit area in the first physical programming unit. 4. The data storage method according to claim 2 or 3, wherein the step of programming the at least one flag into the redundant bit area in the first physical programming unit comprises: programming a first flag into a redundant bit area of the last physical programming unit of the first physical programming unit, wherein the at least one second physical programming unit is arranged before the first physical programming unit after the last physical programming unit in , wherein the first flag instructs the at least one second physical programming unit to store the parity information; and programming the second flag into the redundant bit area of at least one third physical programming unit among the physical programming units, wherein the at least one third physical programming unit is arranged in the at least one second physical programming unit After the programming unit, wherein the second flag instructs the at least one second physical programming unit to store the parity information. 5. The data storage method according to claim 4, wherein the step of programming the at least one flag into the redundant bit area in the first physical programming unit further comprises: Establishing a parity information address correspondence table; and A third mark is recorded in the parity information address correspondence table, wherein the third mark instructs the at least one second physical programming unit to store the parity information. 6. The data storage method according to claim 1, wherein the step of programming the at least one flag into the redundant bit area in the first physical programming unit comprises: counting the number of the first physical programming unit; and According to the number of the first physical programming unit, record a flag value in the redundant bit area of each first physical programming unit, wherein the flag value recorded in the first physical programming unit is based on the The arrangement of the first entity programming units is sequentially decreased. 7. The data storage method according to claim 6, wherein the first tag value among the tag values is 1, and the first tag value is recorded in the last In a redundant bit area of a physical programming unit, and the at least one second physical programming unit is arranged after the last physical programming unit of the first physical programming unit; Wherein the second tag value among the tag values is 2, and the second tag value is recorded in the entity programming adjacent among the first entity programming units and arranged before the last entity programming unit In the redundant bit area of the unit; Wherein the third tag value among the tag values is 3, and the third tag value is recorded adjacent to and arranged before the entity programming unit recording the second tag value among the first entity programming units In the redundant bit area of the entity programming unit. 8. The data storage method according to claim 1, wherein the first data comprises second data and error checking and correction codes, and the data storage method further comprises: When the second data cannot be corrected by using the error checking and correcting code, the address of the at least one second physical programming unit recording the parity information is obtained according to the at least one mark, and the at least one second physical programming unit is programmed from the at least one second physical programming unit The parity information is read in the unit and the second data is corrected according to the read parity information. 9. A data storage method, characterized in that it is used for a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of entity erasing units, and each of these entities erases The unit includes a plurality of physical programming units, wherein each of the physical programming units includes a data bit area and a redundant bit area, and the data storage method includes: Establish a parity information address correspondence table; generating parity information according to the first data; programming the first data into a first physical programming unit among the physical programming units; programming the parity information into at least one second physical programming unit among the physical programming units; and At least one mark is recorded in the parity information address correspondence table, wherein the at least one mark indicates that the parity information is programmed into the at least one second physical programming unit. 10. A memory control circuit unit, characterized in that it is used to control a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of entity erasing units, and each of these The physical erasing unit includes a plurality of physical programming units, wherein each of the physical programming units includes a data bit area and a redundant bit area, and the memory control circuit unit includes: a host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module; and a memory management circuit coupled to the host interface and the memory interface; Wherein the memory management circuit is used to generate parity information according to the first data; Wherein the memory management circuit is also used to program the first data into the first physical programming unit among the physical programming units; The memory management circuit is also used to program the parity information into at least one second physical programming unit among the physical programming units, wherein the at least one second physical programming unit is arranged in the first After the entity programmatic unit; Wherein in the above operation of programming the first data to the first physical programming unit among the physical programming units, the memory management circuit programs at least one flag to the first physical programming unit In the redundant bit field, the at least one flag indicates that the parity information is programmed into the at least one second physical programming unit. 11. The memory control circuit unit according to claim 10, wherein the first data includes user data and management information corresponding to the user data; Wherein the user data is programmed into the data bit area of the first physical programming unit, wherein the management information corresponding to the user data is programmed into the redundancy of the first physical programming units bit area. 12. The memory control circuit unit according to claim 10, wherein the first data includes a user data, a management information corresponding to the user data, and an error checking and correction code corresponding to the user data ; Wherein the error checking and correction code is generated according to the user data; Wherein the user data is programmed into the data bit area in the first physical programming unit, wherein the management information corresponding to the user data is programmed into the redundancy ratio in the first physical programming unit A special zone, wherein the ECC code corresponding to the user data is programmed into a redundant bit area in the first physical programming unit. 13. The memory control circuit unit according to claim 11 or 12, wherein the memory management The circuit programs the first flag to the redundant bit area of the last physical programming unit of the first physical programming unit, wherein the at least one second physical programming unit is arranged in the first physical programming unit After the last physical programming unit, wherein the first flag instructs the at least one second physical programming unit to store the parity information; Wherein the memory management circuit is also used to program the second flag to the redundant bit area of at least one third physical programming unit among the physical programming units, wherein the at least one third physical programming unit is an array After the at least one second physical programming unit, and the second flag instructs the at least one second physical programming unit to store the parity information. 14. A memory storage device, comprising: connecting the interface unit for coupling to the host system; The rewritable non-volatile memory module includes a plurality of physical erasing units, and each of the physical erasing units includes a plurality of physical programming units, wherein each of the physical programming units includes data bit areas and redundancy Yubit area; and a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module; Wherein the memory control circuit unit is used to generate parity information according to the first data; Wherein the memory control circuit unit is also used to program the first data into the first physical programming unit among the physical programming units; The memory control circuit unit is also used to program the parity information into at least one second physical programming unit among the physical programming units, wherein the at least one second physical programming unit is arranged in the first physical programming unit After an entity programming unit; Wherein in the operation of programming the first data to the first physical programming unit among the physical programming units, the memory control circuit unit programs at least one flag to the first physical programming unit In the redundant bit field, the at least one flag indicates that the parity information is programmed into the at least one second physical programming unit. 15. The memory storage device according to claim 14, wherein each of the first data includes user data and management information corresponding to the user data; Wherein the user data is programmed into the data bit area of the first physical programming unit, wherein the management information corresponding to the user data is programmed into the redundancy of the first physical programming units bit area. 16. The memory storage device according to claim 14, wherein the first data comprises user data, management information corresponding to the user data, and error checking and correction code corresponding to the user data; Wherein the error checking and correction code is generated according to the user data; Wherein the user data is programmed into the data bit area in the first physical programming unit, wherein the management information corresponding to the user data is programmed into the redundancy ratio in the first physical programming unit A special zone, wherein the ECC code corresponding to the user data is programmed into a redundant bit area in the first physical programming unit. 17. The memory storage device according to claim 15 or 16, characterized in that, in the operation of programming the at least one flag into the redundant bit area among the first physical programming units, the memory control circuit The unit programs the first flag to the redundant bit area of the last physical programming unit of the first physical programming unit, wherein the at least one second physical programming unit is arranged in the first physical programming unit After the last physical programming unit, wherein the first flag instructs the at least one second physical programming unit to store the parity information; The memory control circuit unit is also used to program the second flag to the redundant bit area of at least one third physical programming unit among the physical programming units, wherein the at least one third physical programming unit is Arranged after the at least one second physical programming unit, wherein the second flag instructs the at least one second physical programming unit to store the parity information. 18. The memory storage device according to claim 17, characterized in that, in the operation of programming the at least one flag into the redundant bit area in the first physical programming unit, the memory control circuit unit establishes parity The information address correspondence table records a third mark in the parity information address correspondence table, wherein the third mark instructs the at least one second physical programming unit to store the parity information. 19. The memory storage device according to claim 14, characterized in that, in the operation of programming the at least one flag into the redundant bit area among the first physical programming units, the memory control circuit unit counts The number of the first physical programming unit, and according to the number of the first physical programming unit, record a flag value in the redundant bit area of each first physical programming unit, wherein the value recorded in the first physical programming unit The tag value in a physical programming unit is sequentially decremented according to the arrangement of the first physical programming unit. 20. The memory storage device according to claim 19, wherein the first tag value among the tag values is 1, and the first tag value is recorded in the last of the first entity programming unit In a redundant bit area of a physical programming unit, and the at least one second physical programming unit is arranged after the last physical programming unit of the first physical programming unit; Wherein the second tag value among the tag values is 2, and the second tag value is recorded in the entity programming adjacent among the first entity programming units and arranged before the last entity programming unit In the redundant bit area of the unit; Wherein the third tag value among the tag values is 3, and the third tag value is recorded in the first physical programming unit adjacent to and arranged in the physical programming unit recording the second tag value In the redundant bit area of the previous entity programming unit. 21. The memory storage device according to claim 14, wherein the first data comprises second data and an ECC code, wherein when the second data cannot be corrected by using the ECC code The memory control circuit unit is also used to obtain the address of the at least one second physical programming unit recording the parity information according to the at least one mark, read the parity information from the at least one second physical programming unit and according to The read parity information is used to correct the second data.