CN105304784A - LED chip packaging structure and LED chip packaging method - Google Patents

Abstract

The invention discloses an LED chip packaging structure and a packaging method thereof. The LED chip includes a substrate, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and an N electrode and a P electrode. On the MESA line where MESA photolithography is performed, the P-type semiconductor layer, light-emitting layer and part of the N-type semiconductor layer are etched along the MESA line to form an N step, and a supporting platform is provided on the N step, and the N electrode wraps the The supporting platform is electrically connected with the N-type semiconductor layer, the distance between the upper edge of the N electrode and the MESA line is greater than the distance between the lower edge of the N electrode and the MESA line, and the solder ball and the MESA line are connected on the N electrode Welding wires are electrically connected. In the present invention, a support platform is arranged on the N steps, and the N electrodes are arranged on the top and side of the support platform. The support platform can effectively release the surface stress of the solder balls on the upper surface of the N electrodes, reducing the deformation of the N electrodes during welding, and effectively The stability of the LED device is improved.

Description

LED chip packaging structure and packaging method thereof

technical field

The invention relates to the technical field of semiconductor light emitting devices, in particular to an LED chip packaging structure and a packaging method thereof.

Background technique

A light-emitting diode (Light-EmittingDiode, LED) is a semiconductor electronic component that can emit light. This electronic component appeared as early as 1962. In the early days, it could only emit red light with low luminosity. Later, other monochromatic light versions were developed. Today, the light that can be emitted has covered visible light, infrared rays and ultraviolet rays, and the luminosity has also increased to a considerable extent. of luminosity. The use has also been used as indicator lights, display panels, etc. from the beginning; with the continuous advancement of technology, light-emitting diodes have been widely used in displays, TV lighting decoration and lighting.

LED chip packaging structures are currently divided into three packaging structures: front-mount, flip-chip, and vertical. At present, the front-mount packaging structure is the most used. The LED chip with the front package structure needs to use the wire bonding process in the packaging process. In view of the particularity of the P electrode and the N electrode of the LED chip with the front package structure on the same side, it is required that the bonding area of the solder ball and the electrode during the wire bonding process should not be large. Beyond the preset MESA line of the chip process.

With the development of LED technology, the area of the N electrode and P electrode of the LED chip becomes smaller and smaller, and the material used for bonding has changed from gold wire to alloy wire; resulting in the existing wire bonding process as shown in Figure 1. Problem: The N electrode deforms seriously during the bonding process of the solder ball and the N electrode, which will affect the stability of the LED chip. When the deformed part of the N electrode exceeds the MESA line, the LED chip will fail.

Therefore, in view of the above technical problems, it is necessary to provide an LED chip packaging structure and a packaging method thereof.

Contents of the invention

The object of the present invention is to provide an LED chip packaging structure and a packaging method thereof.

In order to achieve the above object, the technical solutions provided by the embodiments of the present invention are as follows:

An LED chip packaging structure, the LED chip includes a substrate, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and an N electrode and a P electrode, and the LED chip is preset with a MESA line for performing MESA photolithography , the P-type semiconductor layer, light-emitting layer and part of the N-type semiconductor layer are etched along the MESA line to form an N step, the N step is provided with a supporting platform, and the N electrode wraps the supporting platform and is connected with the N-type semiconductor The layers are electrically connected, the distance between the upper edge of the N electrode and the MESA line is greater than the distance between the lower edge of the N electrode and the MESA line, and the N electrode is electrically connected to the welding wire through solder balls.

As a further improvement of the present invention, the distance between the lower edge of the N electrode and the MESA line is 5-15 μm, and the distance between the upper edge of the N electrode and the MESA line is 10-30 μm.

As a further improvement of the present invention, the thickness of the N electrode on the side of the support platform is 0.5-3 μm, and the thickness of the N electrode above the support platform is 0.5-3 μm.

As a further improvement of the present invention, the thickness of the N electrode above the support platform is equal to the thickness of the N electrode at the side of the support platform.

As a further improvement of the present invention, the area of the solder ball is smaller than the area of the upper surface of the N electrode.

As a further improvement of the present invention, the support platform is insulated or electrically conductively connected to the N-type semiconductor layer.

Correspondingly, a packaging method of an LED chip packaging structure, the packaging method comprising:

Epitaxial growth of N-type semiconductor layer, light-emitting layer and P-type semiconductor layer on the substrate in sequence to form LED epitaxial structure;

Form MESA lines on the LED epitaxial structure, and use MESA photolithography to form the N electrode area;

Etching the N electrode area to form an N step, and a supporting platform is formed on the N step;

An N-electrode electrically connected to the N-type semiconductor layer is formed above and on the side of the support platform, and the distance between the upper edge of the N-electrode and the MESA line is greater than the distance between the lower edge of the N-electrode and the MESA line;

A P electrode electrically connected to the P-type semiconductor layer is formed on the P-type semiconductor layer.

As a further improvement of the present invention, "etching the N electrode region to form an N step, and forming a supporting platform on the N step" specifically includes:

Etching the entire N electrode region up to the N-type semiconductor layer, and then epitaxially growing a supporting platform on the N-type semiconductor layer.

As a further improvement of the present invention, "etching the N electrode region to form an N step, and forming a supporting platform on the N step" specifically includes:

A mask is used to partially etch the N-electrode region up to the N-type semiconductor layer, and a part of the epitaxial layer in the middle of the N-electrode region is reserved to form a supporting platform.

As a further improvement of the present invention, the N step is formed by ICP etching.

The beneficial effects of the present invention are:

In the present invention, a support platform is arranged on the N steps, and the N electrodes are arranged on the top and side of the support platform. The support platform can effectively release the surface stress of the solder balls on the upper surface of the N electrodes, reducing the deformation of the N electrodes during welding, and effectively The stability of the LED device is improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is an electron microscope image of the N electrode welding place on the LED chip in the prior art.

Fig. 2a is a schematic diagram of the side structure of an LED chip in a specific embodiment of the present invention.

Fig. 2b is a schematic top view structure diagram of an LED chip in a specific embodiment of the present invention.

detailed description

In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described The embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

The invention discloses an LED chip packaging structure. The LED chip includes a substrate, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and an N electrode and a P electrode. engraved MESA line, the P-type semiconductor layer, light-emitting layer and part of the N-type semiconductor layer are etched along the MESA line to form an N step, the N step is provided with a support platform, the N electrode wraps the support platform and It is electrically connected with the N-type semiconductor layer, the distance between the upper edge of the N electrode and the MESA line is greater than the distance between the lower edge of the N electrode and the MESA line, and the N electrode is electrically connected to the welding line through the solder ball. connect.

Referring to Fig. 2a, in a specific embodiment of the present invention, the LED chip packaging structure includes from bottom to top:

Substrate 10, the substrate can be sapphire, Si, SiC, GaN, ZnO, etc.;

N-type semiconductor layer 20, the N-type semiconductor layer can be N-type GaN, etc.;

A light-emitting layer 30, the light-emitting layer can be GaN, InGaN, etc.;

P-type semiconductor layer 40, the P-type semiconductor layer can be P-type GaN, etc.;

The N electrode 60 and the P electrode 70, the N electrode 60 is arranged on the N step 50, and is electrically connected with the N-type semiconductor layer 20, and the P electrode 70 is arranged above the P-type semiconductor layer 40, and is electrically connected with the P-type semiconductor layer 40 connect.

Wherein, as shown in FIG. 2 b , MESA lines 1 for performing MESA lithography are preset on the LED chip, and MESA layers 2 can be formed after MESA lithography.

In this embodiment, the P-type semiconductor layer 40, the light-emitting layer 30 and part of the N-type semiconductor layer 20 are etched along the MESA line 1 to form an N step 50, and a support platform 51 is provided on the N step 50, and the N electrode 60 wraps the support platform 51 And it is electrically connected with the N-type semiconductor layer 20 , and the N electrode 60 is electrically connected with the welding wire through the solder ball.

As shown in FIG. 2b, the N electrode 60 in this embodiment includes two parts, namely the N electrode part located on the side of the support platform 51 and the N electrode part located above the support platform 51, wherein the N electrode part located above the support platform 51 The distance between the upper edge of the N electrode and the MESA line is greater than the distance between the lower edge of the N-electrode portion on the side of the support platform 51 and the MESA line.

In a preferred embodiment of the present invention, the distance between the lower edge of the N electrode and the MESA line is 5-15 μm, and the distance between the upper edge of the N electrode and the MESA line is 10-30 μm;

In a preferred embodiment of the present invention, the thickness of the N electrode 60 above the support platform 51 is 0.5-3 μm, and the thickness of the N electrode 60 on the side of the support platform 51 is 0.5-3 μm.

In a preferred embodiment of the present invention, the thickness of the N electrode 60 above the support platform 51 is equal to the thickness of the N electrode 60 at the side of the support platform 51 .

During soldering, the area of the solder ball is smaller than the area of the upper surface of the N electrode 60 .

Preferably, in a specific embodiment shown in FIGS. The distance is 18-20 μm; the thickness of the N electrode 60 on the side of the support platform 51 is 2 μm, and the thickness of the N electrode 60 above the support platform 51 is equal to the thickness of the N electrode 60 on the side of the support platform 51 .

Wherein, the support platform 51 may be insulated or electrically connected to the N-type semiconductor layer.

During the welding process of the LED chip in this embodiment, the solder balls can cover the N electrodes above the support platform, but the solder balls and the N electrodes on the side of the support platform are not in the same plane, and the deformed part of the solder balls will not interfere with the N electrodes on the side. The extrusion caused by the electrode effectively releases the surface stress of the solder ball on the upper surface of the N electrode, reduces the deformation of the N electrode, reduces the failure of the LED device, and effectively improves the stability of the LED device.

In addition, the packaging method of the LED chip packaging structure in this embodiment specifically includes:

Epitaxially grow the N-type semiconductor layer 20, the light emitting layer 30 and the P-type semiconductor layer 40 on the substrate 10 in order to form an LED epitaxial structure;

Form a MESA line 1 on the LED epitaxial structure, and use MESA photolithography 1 to form an N electrode region;

Etching the N electrode region to form an N step 50, and a supporting platform 51 is formed on the N step 50;

An N-electrode 60 electrically connected to the N-type semiconductor layer is formed above and on the side of the support platform 50;

A P electrode 70 electrically connected to the P-type semiconductor layer is formed on the P-type semiconductor layer.

Among them, in a preferred embodiment of the present invention, "etching the N electrode region to form an N step, and forming a supporting platform on the N step" specifically includes:

Etching the entire N electrode region up to the N-type semiconductor layer, and then epitaxially growing a supporting platform on the N-type semiconductor layer.

In this method, all the epitaxial layer at the N electrode region is firstly etched away, this step is completely the same as the prior art, and then the support platform 51 is regrown in the corresponding region of the N step 50 .

In another preferred embodiment of the present invention, "etching the N electrode region to form an N step, and forming a supporting platform on the N step" specifically includes:

A mask is used to partially etch the N-electrode region up to the N-type semiconductor layer, and a part of the epitaxial layer in the middle of the N-electrode region is reserved to form a supporting platform.

In the method, during the etching process, a mask is used at the corresponding position of the support platform to retain part of the epitaxial layer to form the support platform, without the need for epitaxial growth of the support platform.

The etching in this embodiment adopts the ICP etching process, and the ICP etching is gas etching, and the reaction gases mainly include chlorine, argon, carbon tetrafluoride, and oxygen. The etching principle of chlorine gas, carbon tetrafluoride and oxygen is to generate high-energy plasma under the action of radio frequency, react with GaN to achieve etching effect, and generate volatile Ga, GaCl _x , Ga ⁺ , GaCl _x ⁺ , N ₂ , GaF, etc. , to generate volatile gallium chloride, gallium fluoride, etc., which are pumped out of the reaction chamber; argon mainly has the effect of physical bombardment, and Cl ₂ also has the effect of physical bombardment, the principle is as follows:

GaN+Cl→Ga, GaCl _x , Ga ⁺ , GaCl _x ⁺ , N ₂ (x=1, 2, 3).

Certainly, in other implementation manners, other etching processes may also be used to form the N step and the supporting platform, which will not be illustrated here one by one.

When the above-mentioned LED chip packaging structure is soldered, the solder ball is soldered to the N electrode, and the gold wire is electrically connected to the solder ball. The shape of the solder ball is roughly circular, and the area of the solder ball is smaller than that of the upper surface of the N electrode. area, so as to prevent the solder ball from protruding from the outside of the N electrode during soldering, and avoiding the contact between the solder ball and the MESA line. At the same time, the setting of the supporting platform can reduce the surface stress of the solder ball on the N electrode during the welding process, and prevent the deformation of the N electrode and the contact with the MESA line to cause failure.

It can be seen from the above technical solutions that, compared with the prior art, the present invention provides a supporting platform on the N step, and the N electrode is arranged on the top and side of the supporting platform, and the supporting platform can effectively release solder balls on the upper surface of the N electrode. The surface stress reduces the deformation of the N electrode during welding and effectively improves the stability of the LED device.

It will be apparent to those skilled in the art that the invention is not limited to the details of the above-described exemplary embodiments, but that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Accordingly, the embodiments should be regarded in all points of view as exemplary and not restrictive, the scope of the invention being defined by the appended claims rather than the foregoing description, and it is therefore intended that the scope of the invention be defined by the appended claims rather than by the foregoing description. All changes within the meaning and range of equivalents of the elements are embraced in the present invention. Any reference sign in a claim should not be construed as limiting the claim concerned.

In addition, it should be understood that although this specification is described according to implementation modes, not each implementation mode only contains an independent technical solution, and this description in the specification is only for clarity, and those skilled in the art should take the specification as a whole , the technical solutions in the various embodiments can also be properly combined to form other implementations that can be understood by those skilled in the art.

Claims (10)

1. a LED chip encapsulating structure, described LED chip comprises substrate, n type semiconductor layer, luminescent layer, p type semiconductor layer and N electrode and P electrode, it is characterized in that, described LED chip is preset with the MESA line for carrying out MESA photoetching, described p type semiconductor layer, luminescent layer and part n type semiconductor layer are formed with N step along MESA line etching, described N step is provided with support platform, described N electrode is wrapped up described support platform and is electrically connected with n type semiconductor layer, distance between the top edge of described N electrode and MESA line is greater than the distance between the lower limb of N electrode and MESA line, described N electrode is electrically connected by soldered ball and sealing wire.

2. LED chip encapsulating structure according to claim 1, is characterized in that, the distance between the lower limb edge of described N electrode and MESA line is 5 ~ 15 μm, and the distance between the top edge of N electrode and MESA line is 10 ~ 30 μm.

3. LED chip encapsulating structure according to claim 1, is characterized in that, described N electrode is 0.5 ~ 3 μm at the thickness of support platform side, and the thickness of described N electrode above support platform is 0.5 ~ 3 μm.

4. LED chip encapsulating structure according to claim 3, is characterized in that, the thickness of described N electrode above support platform is equal at the thickness of support platform side with N electrode.

5. LED chip encapsulating structure according to claim 1, is characterized in that, the area of described soldered ball is less than the area of N electrode upper surface.

6. LED chip encapsulating structure according to claim 1, is characterized in that, described support platform connects for insulating to be connected or to electrically conduct with n type semiconductor layer.

7. a method for packing for LED chip encapsulating structure, is characterized in that, described method for packing comprises:

Epitaxial growth n type semiconductor layer, luminescent layer and p type semiconductor layer successively on substrate, form LED epitaxial structure;

LED epitaxial structure is formed MESA line, and adopts MESA photoetching to form N electrode region;

N step is formed to N electrode region etch, N step is formed with support platform;

Above support platform, be formed at the N electrode that n type semiconductor layer is electrically connected with side, the distance between the top edge of described N electrode and MESA line is greater than the distance between the lower limb of N electrode and MESA line;

P type semiconductor layer is formed at the P electrode that p type semiconductor layer is electrically connected.

8. method for packing according to claim 7, is characterized in that, " form N step to N electrode region etch, N step is formed with support platform " specifically comprises:

All n type semiconductor layer is etched to N electrode region, then in n type semiconductor layer Epitaxial growth support platform.

9. method for packing according to claim 7, is characterized in that, " form N step to N electrode region etch, N step is formed with support platform " specifically comprises:

Adopt mask to be etched to n type semiconductor layer to N electrode area part, retain the portion of epi layer in the middle of N electrode region, form support platform.

10. method for packing according to claim 7, is characterized in that, described N step is formed by ICP etching.