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CN105283962B - Semiconductor device - Google Patents

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CN105283962B
CN105283962B CN201380077391.0A CN201380077391A CN105283962B CN 105283962 B CN105283962 B CN 105283962B CN 201380077391 A CN201380077391 A CN 201380077391A CN 105283962 B CN105283962 B CN 105283962B
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layer
negative electrode
semiconductor device
electrode layer
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CN105283962A (en
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增冈史仁
中村胜光
西井昭人
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
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Abstract

At n－The top surface of the drift layer (1) is provided with a p-type positive electrode layer (2). At n－An n-type negative electrode layer (3) is arranged on the bottom surface of the type drift layer (1). At n－An n-type buffer layer (4) is arranged between the n-type drift layer (1) and the n-type negative electrode layer (3). The peak concentration of the n-type buffer layer (4) is higher than n－And the type drift layer (1) is lower than the n-type negative electrode layer (3). n is－The gradient of the carrier concentration at the connecting part of the type drift layer (1) and the n-type buffer layer (4) is 20-2000 cm‑4。

Description

半导体装置Semiconductor device

技术领域technical field

本发明涉及一种在高耐压功率模块(≥600V)中使用的二极管等半导体装置。The present invention relates to a semiconductor device such as a diode used in a high withstand voltage power module (≥600V).

背景技术Background technique

在20世纪50年代的半导体初期以后，针对Si基p-i-n二极管中的高频振荡现象(例如参照非专利文献1)和击穿现象(例如参照非专利文献2)进行了各种研究。近年来，在高速动作化得到发展的功率器件中，会导致周边电路的误动作和器件自身的浪涌击穿，这些现象再次受到了关注(例如参照非专利文献3)。Since the early days of semiconductors in the 1950s, various studies have been conducted on the high-frequency oscillation phenomenon (for example, see Non-Patent Document 1) and the breakdown phenomenon (for example, see Non-Patent Document 2) in Si-based p-i-n diodes. In recent years, power devices operating at higher speeds have attracted renewed attention to malfunctions of peripheral circuits and surge breakdown of the devices themselves (see, for example, Non-Patent Document 3).

已知在快速恢复二极管中，这些现象在高Vcc、高配线电感(Ls)、低动作温度、以及低电流密度(JA)等硬恢复条件下变得显著(例如参照非专利文献5、11)。在快速恢复二极管中，通过采用厚的n－型漂移层或厚的n型缓冲层、以及应用寿命控制技术等(例如参照非专利文献5～7)所谓的“软恢复化”，解决了上述课题。但是，在这些方法中，存在EMI(Electromagnetic Compatibility)噪声、击穿耐量、以及总损耗之间的折衷关系，难于以高水平同时兼顾。It is known that in fast recovery diodes, these phenomena become significant under hard recovery conditions such as high Vcc, high wiring inductance (Ls), low operating temperature, and low current density (JA) (for example, refer to non-patent documents 5, 11 ). In the fast recovery diode, by adopting thick n - type drift layer or thick n-type buffer layer, and applying lifetime control technology (for example, refer to non-patent documents 5~7) so-called "soft recovery" solves the above-mentioned problems. topic. However, in these methods, there is a trade-off relationship between EMI (Electromagnetic Compatibility) noise, breakdown resistance, and total loss, and it is difficult to achieve a high level of both.

另一方面，通过以RFC二极管(例如参照非专利文献10～14)为代表的、在背面形成p+型层的二极管(例如参照非专利文献4、8、9)，显著地提高了二极管的主要特性。但是，作为进一步的开发课题，遗留有下述课题，即，通过降低泄漏电流而使动作温度范围向高温侧扩展、通过降低高电流密度区域的VF(二极管的导通时的压降)而提高最大切断电流密度、以及通过增强缓冲构造而提高雪崩耐量。On the other hand, by forming a p + -type layer on the back surface of a diode represented by RFC diodes (for example, see Non-Patent Documents 10 to 14) (for example, see Non-Patent Documents 4, 8, and 9), the performance of the diode has been significantly improved. main features. However, as further development issues, the following issues remain, that is, to expand the operating temperature range to the high temperature side by reducing the leakage current, and to improve the VF (voltage drop when the diode is turned on) by reducing the Maximum cut-off current density and improved avalanche resistance through enhanced cushioning structure.

另外，提出了在n－型漂移层与n型负极层之间设置了具有两者中间的杂质浓度的n型缓冲层的二极管(例如参照专利文献1、2)。虽然专利文献1中未记载n型缓冲层的浓度梯度的具体数值，但从专利文献1的图3能够估计出浓度梯度为8×103cm-4。另外，专利文献2的n型缓冲层是非专利文献10中记载的结构，其浓度梯度为1×105cm-4。Also, a diode has been proposed in which an n-type buffer layer having an intermediate impurity concentration is provided between an n − -type drift layer and an n-type negative electrode layer (for example, refer to Patent Documents 1 and 2). Although the specific numerical value of the concentration gradient of the n-type buffer layer is not described in Patent Document 1, it can be estimated from FIG. 3 of Patent Document 1 that the concentration gradient is 8×10 3 cm −4 . In addition, the n-type buffer layer in Patent Document 2 has the structure described in Non-Patent Document 10, and its concentration gradient is 1×10 5 cm -4 .

专利文献1：日本特开2007－158320号公报Patent Document 1: Japanese Unexamined Patent Publication No. 2007-158320

专利文献2：日本特开2010－283132号公报Patent Document 2: Japanese Unexamined Patent Publication No. 2010-283132

非专利文献1：W.T.READ,JR,“A Proposed High-Frequency,Negative-Resistance Diode,”The Bell system technical journal,pp.401-446(March 1958)Non-Patent Document 1: W.T. READ, JR, "A Proposed High-Frequency, Negative-Resistance Diode," The Bell system technical journal, pp. 401-446 (March 1958)

非专利文献2：H.Egawa,“Avalanche Characteristics and Failure Mechanismof High Voltage Diodes,”IEEE Trans.Electron Devices,vol.ED-13,No.11,pp.754-758(1966)Non-Patent Document 2: H. Egawa, "Avalanche Characteristics and Failure Mechanism of High Voltage Diodes," IEEE Trans. Electron Devices, vol. ED-13, No. 11, pp. 754-758 (1966)

非专利文献3：R.Siemieniec,P.Mourick,J.Lutz,M.Netzel,“Analysis ofPlasma Extraction Transit Time Oscillations in Bipolar Power Devices,”Proc.ISPSD’04,pp.249-252,Kitakyushu,Japan(2004)Non-Patent Document 3: R.Siemieniec, P.Mourick, J.Lutz, M.Netzel, "Analysis of Plasma Extraction Transit Time Oscillations in Bipolar Power Devices," Proc.ISPSD'04, pp.249-252, Kitakyushu, Japan ( 2004)

非专利文献4：K.Satoh,K.Morishita,Y.Yamaguchi,N.Hirano,H.Iwamoto andA.Kawakami,“A Newly Structured High Voltage Diode Highlighting OscillationFree Function in Recovery Process,”Proc.ISPSD’2000,pp.249-252,Toulouse,France(2000)Non-Patent Document 4: K. Satoh, K. Morishita, Y. Yamaguchi, N. Hirano, H. Iwamoto and A. Kawakami, "A Newly Structured High Voltage Diode Highlighting Oscillation Free Function in Recovery Process," Proc.ISPSD'2000, pp .249-252, Toulouse, France (2000)

非专利文献5：M.T.Rahimo and N.Y.A.Shammas,“Optimization of the ReverseRecovery Behavior of Fast Power Diodes Using Injection Efficiency AndLifetime Control Techniques,”Proc.EPE’97,pp.2.099-2.104,Trondheim,Norway(1997)Non-Patent Document 5: M.T.Rahimo and N.Y.A.Shammas, "Optimization of the Reverse Recovery Behavior of Fast Power Diodes Using Injection Efficiency And Lifetime Control Techniques," Proc.EPE'97, pp.2.099-2.104, Trondheim, Norway (1997)

非专利文献6：M.Nemoto,T.Naito,A.Nishihara,K.Ueno,“MBBL diode:a novelsoft recovery diode,”Proc.ISPSD’04,pp.433-436,Kitakyushu,JapanNon-Patent Document 6: M.Nemoto, T.Naito, A.Nishihara, K.Ueno, "MBBL diode: a novelsoft recovery diode," Proc.ISPSD'04, pp.433-436, Kitakyushu, Japan

非专利文献7：H.Fujii,M.Inoue,K.Hatade and Y.Tomomatsu,“A Novel BufferStructure and lifetime control Technique with Poly-Si for Thin Wafer Diode,”Proc.ISPSD’09,pp.140-143,Barcelona,Spain(2009)Non-Patent Document 7: H. Fujii, M. Inoue, K. Hatade and Y. Tomomatsu, "A Novel Buffer Structure and lifetime control Technique with Poly-Si for Thin Wafer Diode," Proc.ISPSD'09, pp.140-143 , Barcelona, Spain (2009)

非专利文献8：A.Kopta and M.Rahimo,“The Field Charge Extraction(FCE)Diode A Novel Technology for Soft Recovery High Voltage Diodes,”Proc.ISPSD’05,pp.83-86,Santa Barbara,California,USA(2005)Non-Patent Document 8: A.Kopta and M.Rahimo, "The Field Charge Extraction (FCE) Diode A Novel Technology for Soft Recovery High Voltage Diodes," Proc.ISPSD'05, pp.83-86, Santa Barbara, California, USA (2005)

非专利文献9：H.P.Felsl,M.Pfaffenlehner,H.Schulze,J.Biermann,Th.Gutt,H.-J.Schulze,M.Chen and J.Luts,“The CIBH Diode-Great Improvement forRuggedness and Softness of High Voltage Diodes,”Proc.ISPSD’08,pp.173-176,Orlando,Florida,USA(2008)Non-Patent Document 9: H.P.Felsl, M.Pfaffenlehner, H.Schulze, J.Biermann, Th.Gutt, H.-J.Schulze, M.Chen and J.Luts, "The CIBH Diode-Great Improvement for Ruggedness and Softness of High Voltage Diodes,"Proc.ISPSD'08,pp.173-176,Orlando,Florida,USA(2008)

非专利文献10：K.Nakamura,Y.Hisamoto,T.Matsumura,T.Minato andJ.Moritani,“The Second Stage of a Thin Wafer IGBT Low Loss 1200V LPT-CSTBTTMwith a Backside Doping Optimization Process,”Proc.ISPSD’06,pp.133-136,Naples,Italy(2006)Non-Patent Document 10: K. Nakamura, Y. Hisamoto, T. Matsumura, T. Minato and J. Moritani, "The Second Stage of a Thin Wafer IGBT Low Loss 1200V LPT-CSTBTTM with a Backside Doping Optimization Process," Proc.ISPSD' 06, pp.133-136, Naples, Italy (2006)

非专利文献11：K.Nakamura,H.Iwanaga,H.Okabe,S.Saito and K.Hatade,“Evaluation of Oscillatory Phenomena in Reverse Operation for High VoltageDiodes,”Proc.ISPSD’09,pp.156-159,Barcelona,Spain(2009)Non-Patent Document 11: K. Nakamura, H. Iwanaga, H. Okabe, S. Saito and K. Hatade, "Evaluation of Oscillatory Phenomena in Reverse Operation for High Voltage Diodes," Proc.ISPSD'09, pp.156-159, Barcelona, Spain (2009)

非专利文献12：K.Nakamura,F.Masuoka,A.Nishii,K.Sadamatsu,S.Kitajima andK.Hatade,“Advanced RFC Technology with New Cathode Structure of FieldLimiting Rings for High Voltage Planar Diode,”Proc.ISPSD’10,pp.133-136,Hiroshima,Japan(2010)Non-Patent Document 12: K. Nakamura, F. Masuoka, A. Nishii, K. Sadamatsu, S. Kitajima and K. Hatade, "Advanced RFC Technology with New Cathode Structure of FieldLimiting Rings for High Voltage Planar Diode," Proc.ISPSD' 10, pp.133-136, Hiroshima, Japan (2010)

非专利文献13：A.Nishii,K.Nakamura,F.Masuoka and T.Terashima,“Relaxation of Current Filament due to RFC Technology and Ballast Resistorfor Robust FWD Operation,”Proc.ISPSD’11,pp.96-99,San Diego,California,USA(2011)Non-Patent Document 13: A. Nishii, K. Nakamura, F. Masuoka and T. Terashima, "Relaxation of Current Filament due to RFC Technology and Ballast Resistor for Robust FWD Operation," Proc.ISPSD'11, pp.96-99, San Diego, California, USA (2011)

非专利文献14：F.Masuoka,K.Nakamura,A.Nishii and T.Terashima,“GreatImpact of RFC Technology on Fast Recovery Diode towards 600V for Low Loss andHigh Dynamic Ruggedness,”Proc.ISPSD’12,pp.373-376,Bruges,Belgium(2012)Non-Patent Document 14: F. Masuoka, K. Nakamura, A. Nishii and T. Terashima, "Great Impact of RFC Technology on Fast Recovery Diode towards 600V for Low Loss and High Dynamic Ruggedness," Proc.ISPSD'12, pp.373- 376, Bruges, Belgium (2012)

发明内容Contents of the invention

在现有的半导体装置中，n－型漂移层与n型缓冲层的连接部分处的载流子浓度的梯度是陡峭的，为8×103cm-4或1×105cm-4，因此，由于连接部分的电场强度的增高而产生阶跃(snap off)。此外，存在以阶跃作为触发而产生高频振荡的问题。In existing semiconductor devices, the gradient of the carrier concentration at the junction of the n - type drift layer and the n-type buffer layer is steep, 8×10 3 cm -4 or 1×10 5 cm -4 , Therefore, a snap off occurs due to an increase in electric field intensity at the connection portion. In addition, there is a problem of high-frequency oscillation using a step as a trigger.

另外，通过使用重金属扩散、电子或离子的照射实现的寿命控制方法，对现有的二极管的VF和恢复损耗EREC的折衷特性进行了调整。但是，根据电子或离子照射时的与被照射体之间的照射角度、温度等的不同，VF、EREC的波动较大。另外，由于芯片通电动作时的自发热，因而晶格缺陷发生变化，电气特性发生变动。此外，由于由晶格缺陷产生的泄漏电流较大，所以在高温动作时发生热失控。因此，需要确立一种不依赖于寿命控制方法的、VF-EREC折衷特性的控制方法。In addition, the trade-off characteristics of VF and recovery loss EREC of existing diodes have been adjusted by using a lifetime control method realized by diffusion of heavy metals and irradiation of electrons or ions. However, VF and EREC fluctuate greatly depending on the irradiation angle to the irradiated object, temperature, etc. during electron or ion irradiation. In addition, due to self-heating when the chip is energized, lattice defects change and electrical characteristics fluctuate. In addition, since the leakage current due to lattice defects is large, thermal runaway occurs during high-temperature operation. Therefore, it is necessary to establish a control method for VF-EREC trade-off characteristics that does not depend on the lifetime control method.

功率器件在各种用途中得到使用，对IGBT、二极管等也要求雪崩耐量。但是，在具有寄生双极型晶体管构造的半导体装置中，与不具有这种构造的半导体装置相比，雪崩耐量减少。另外，如果以VF-EREC特性的改善为目标而使n－型漂移层的厚度变薄，则雪崩耐量显著降低。另外，在具有寄生双极型晶体管构造的半导体装置中，与不具有这种构造的半导体装置相比，最大可控电流密度降低。Power devices are used in various applications, and avalanche resistance is also required for IGBTs, diodes, and the like. However, in a semiconductor device having a parasitic bipolar transistor structure, the avalanche withstand capacity is reduced compared to a semiconductor device not having such a structure. In addition, if the thickness of the n - -type drift layer is reduced for the purpose of improving the VF-EREC characteristics, the avalanche resistance will decrease significantly. In addition, in a semiconductor device having a parasitic bipolar transistor configuration, the maximum controllable current density is lowered compared to a semiconductor device not having such a configuration.

本发明就是为了解决上述课题而提出的，第1目的是得到一种能够实现高振荡耐量的半导体装置。第2目的是得到一种能够不依赖于寿命控制方法而改善VF-EREC折衷特性、提高雪崩耐量和最大可控电流密度的半导体装置。The present invention was made in order to solve the above-mentioned problems, and the first object is to obtain a semiconductor device capable of achieving high oscillation tolerance. The second object is to obtain a semiconductor device capable of improving the VF-EREC trade-off characteristics, improving the avalanche tolerance and the maximum controllable current density independently of the lifetime control method.

本发明所涉及的半导体装置的特征在于，具备：n型漂移层；p型正极层，其设置在所述n型漂移层的顶面；负极层，其设置在所述n型漂移层的底面；以及n型缓冲层，其设置在所述n型漂移层与所述负极层之间，所述n型缓冲层的峰值浓度高于所述n型漂移层，低于所述负极层，所述n型漂移层与所述n型缓冲层的连接部分处的载流子浓度的梯度为20～2000cm-4。The semiconductor device according to the present invention is characterized in that it comprises: an n-type drift layer; a p-type positive electrode layer disposed on the top surface of the n-type drift layer; and a negative electrode layer disposed on the bottom surface of the n-type drift layer. and an n-type buffer layer, which is arranged between the n-type drift layer and the negative electrode layer, the peak concentration of the n-type buffer layer is higher than the n-type drift layer and lower than the negative electrode layer, so The gradient of the carrier concentration at the connection portion between the n-type drift layer and the n-type buffer layer is 20-2000 cm −4 .

发明的效果The effect of the invention

根据本发明，能够实现高振荡耐量。According to the present invention, high vibration tolerance can be realized.

附图说明Description of drawings

图1是表示本发明的实施方式1所涉及的半导体装置的俯视图。FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention.

图2是表示本发明的实施方式1所涉及的半导体装置的仰视图。2 is a bottom view showing the semiconductor device according to Embodiment 1 of the present invention.

图3是沿图1及图2的I-II的剖视图。Fig. 3 is a sectional view taken along line I-II of Fig. 1 and Fig. 2 .

图4是表示相对于深度的载流子浓度的图。Fig. 4 is a graph showing carrier concentration with respect to depth.

图5是表示相对于载流子浓度梯度▽nbuffer的VF、EREC、Vsnap-off、JA(break)的图。Fig. 5 is a graph showing V F , E REC , V snap-off , and J A(break) with respect to the carrier concentration gradient ▽n buffer .

图6是表示本发明的实施方式2所涉及的半导体装置的剖视图。6 is a cross-sectional view showing a semiconductor device according to Embodiment 2 of the present invention.

图7是表示本发明的实施方式3所涉及的半导体装置的剖视图。7 is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention.

图8是表示对比例所涉及的半导体装置的剖视图。8 is a cross-sectional view showing a semiconductor device according to a comparative example.

图9是表示用于模拟的n型缓冲层的峰值浓度和扩散深度的图。Fig. 9 is a graph showing the peak concentration and diffusion depth of the n-type buffer layer used in the simulation.

图10是表示对比例和实施方式3中的耐压波形的缓冲层厚度依赖性的模拟结果的图。10 is a graph showing simulation results of buffer layer thickness dependence of withstand voltage waveforms in Comparative Example and Embodiment 3. FIG.

图11是表示对比例和实施方式3中的活跃恢复(snappy recovery)波形的Vcc依赖性的模拟结果的图。FIG. 11 is a graph showing simulation results of Vcc dependence of a snappy recovery waveform in a comparative example and Embodiment 3. FIG.

图12是表示对比例和实施方式3中的活跃恢复波形的Vcc依赖性的模拟结果的图。FIG. 12 is a graph showing simulation results of the Vcc dependence of the active recovery waveform in the comparative example and the third embodiment.

图13是表示本发明的实施方式4所涉及的半导体装置的后视图。13 is a rear view showing a semiconductor device according to Embodiment 4 of the present invention.

图14是沿图13的I-II的剖视图。Fig. 14 is a sectional view taken along line I-II of Fig. 13 .

图15是沿图13的III-IV的剖视图。Fig. 15 is a sectional view along line III-IV of Fig. 13 .

图16是表示本发明的实施方式4所涉及的半导体装置的变形例1的仰视图。16 is a bottom view showing Modification 1 of the semiconductor device according to Embodiment 4 of the present invention.

图17是表示本发明的实施方式4所涉及的半导体装置的变形例2的仰视图。17 is a bottom view showing Modification 2 of the semiconductor device according to Embodiment 4 of the present invention.

图18是表示本发明的实施方式5所涉及的半导体装置的剖视图。18 is a cross-sectional view showing a semiconductor device according to Embodiment 5 of the present invention.

图19是表示本发明的实施方式6所涉及的半导体装置的剖视图。19 is a cross-sectional view showing a semiconductor device according to Embodiment 6 of the present invention.

图20是表示本发明的实施方式7所涉及的半导体装置的剖视图。20 is a cross-sectional view showing a semiconductor device according to Embodiment 7 of the present invention.

图21是表示本发明的实施方式8所涉及的半导体装置的剖视图。21 is a cross-sectional view showing a semiconductor device according to Embodiment 8 of the present invention.

图22是表示本发明的实施方式9所涉及的半导体装置的剖视图。22 is a cross-sectional view showing a semiconductor device according to Embodiment 9 of the present invention.

图23是表示本发明的实施方式10所涉及的半导体装置的剖视图。23 is a cross-sectional view showing a semiconductor device according to Embodiment 10 of the present invention.

图24是表示本发明的实施方式11所涉及的半导体装置的剖视图。24 is a cross-sectional view showing a semiconductor device according to Embodiment 11 of the present invention.

图25是表示本发明的实施方式12所涉及的半导体装置的剖视图。25 is a cross-sectional view showing a semiconductor device according to Embodiment 12 of the present invention.

图26是表示本发明的实施方式13所涉及的半导体装置的剖视图。26 is a cross-sectional view showing a semiconductor device according to Embodiment 13 of the present invention.

具体实施方式Detailed ways

参照附图，对本发明的实施方式所涉及的半导体装置进行说明。对相同或相对应的结构要素标注相同标号，有时省略重复的说明。A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same reference numerals are attached to the same or corresponding structural elements, and overlapping descriptions may be omitted.

实施方式1Embodiment 1

图1以及图2分别是表示本发明的实施方式1所涉及的半导体装置的俯视图以及仰视图。图3是沿图1及图2的I-II的剖视图。在n－型漂移层1的顶面设置有p型正极层2。在n－型漂移层1的底面设置有n型负极层3。1 and 2 are a plan view and a bottom view showing a semiconductor device according to Embodiment 1 of the present invention, respectively. Fig. 3 is a sectional view taken along line I-II of Fig. 1 and Fig. 2 . A p-type anode layer 2 is provided on the top surface of the n − -type drift layer 1 . An n-type negative electrode layer 3 is provided on the bottom surface of the n − -type drift layer 1 .

在n－型漂移层1与n型负极层3之间设置有n型缓冲层4。n型缓冲层4的杂质的峰值浓度高于n－型漂移层1，低于n型负极层3。正极电极5与p型正极层2欧姆接触，负极电极6与n型负极层3欧姆接触。An n-type buffer layer 4 is provided between the n − -type drift layer 1 and the n-type negative electrode layer 3 . The peak concentration of impurities in the n-type buffer layer 4 is higher than that of the n − -type drift layer 1 and lower than that of the n-type negative electrode layer 3 . The positive electrode 5 is in ohmic contact with the p-type positive electrode layer 2 , and the negative electrode 6 is in ohmic contact with the n-type negative electrode layer 3 .

图4是表示相对于深度的载流子浓度的图。将n型缓冲层4的深度设为Dbuffer，将n型漂移层与n型缓冲层的连接部分处的载流子浓度的梯度设为浓度梯度▽nbuffer[cm-4]，将n型缓冲层4中的有效剂量设为φeff[cm-2]，将n－型漂移层1的载流子浓度设为n0[cm-3]。它们之间的关系用下面的公式表示。Fig. 4 is a graph showing carrier concentration with respect to depth. The depth of the n-type buffer layer 4 is set as D buffer , the gradient of the carrier concentration at the junction of the n-type drift layer and the n-type buffer layer is set as the concentration gradient ▽n buffer [cm -4 ], and the n-type The effective dose in the buffer layer 4 is φ eff [cm −2 ], and the carrier concentration of the n − -type drift layer 1 is n 0 [cm −3 ]. The relationship between them is expressed by the following formula.

公式1Formula 1

图5是表示相对于载流子浓度梯度▽nbuffer的VF、EREC、Vsnap-off、JA(break)的图。VF是导通状态下的压降，EREC是恢复损耗，Vsnap-off是恢复时的过冲电压，JA(break)是最大可控电流密度。基于该数据，为了降低VF、EREC、Vsnap-off、提高JA(break)，将浓度梯度▽nbuffer设为20～2000cm-4。此外，在现有技术中，浓度梯度为105cm-4左右，比本实施方式陡峭。Fig. 5 is a graph showing V F , E REC , V snap-off , and J A(break) with respect to the carrier concentration gradient ▽n buffer . V F is the voltage drop in the on-state, E REC is the recovery loss, V snap-off is the overshoot voltage during recovery, and J A(break) is the maximum controllable current density. Based on this data, in order to reduce V F , E REC , V snap-off and increase J A(break) , the concentration gradient ▽n buffer was set to 20 to 2000 cm -4 . In addition, in the prior art, the concentration gradient is about 10 5 cm -4 , which is steeper than that of the present embodiment.

如本实施方式所示，将n－型漂移层1与n型缓冲层4的连接部分的载流子浓度缓且宽地进行了分布的深缓冲构造称为CPL(Controlling Plasma Layer)缓冲构造。利用该CPL缓冲构造，能够抑制恢复时的该边界部分处的电场强度的增高。其结果，能够防止由负极侧的电场强度的增高而产生的阶跃、以及以该阶跃作为触发而产生的高频振荡，因此能够实现高振荡耐量。As shown in this embodiment, the deep buffer structure in which the carrier concentration of the connection portion between the n - -type drift layer 1 and the n-type buffer layer 4 is distributed gently and broadly is called a CPL (Controlling Plasma Layer) buffer structure. With this CPL buffer structure, it is possible to suppress an increase in the electric field intensity at the boundary portion at the time of recovery. As a result, it is possible to prevent a step caused by an increase in the electric field intensity on the negative electrode side and high-frequency oscillation triggered by the step, thereby realizing high oscillation tolerance.

另外，将n型缓冲层4的有效剂量φeff设定为比n－型漂移层1的有效剂量高的1×1012～5×1012cm-2。由此，n型缓冲层4的总剂量变为与n－型漂移层1的总剂量同等程度，因此能够利用n－型漂移层1和n型缓冲层4这两者保持耐压。因此，与不存在n型缓冲层4的情况相比，能够使保持同等耐压所需的n－型漂移层1的厚度变薄，能够减少总损耗。In addition, the effective dose φ eff of the n-type buffer layer 4 is set to be 1×10 12 to 5×10 12 cm −2 higher than the effective dose of the n − -type drift layer 1 . Thereby, the total dose of the n-type buffer layer 4 becomes approximately the same as the total dose of the n − type drift layer 1 , and thus the breakdown voltage can be maintained by both the n − type drift layer 1 and the n type buffer layer 4 . Therefore, compared with the case where there is no n-type buffer layer 4, the thickness of the n − -type drift layer 1 required to maintain the same withstand voltage can be reduced, and the total loss can be reduced.

此外，n－型漂移层1的载流子浓度n0依赖于耐压等级而决定。作为一个例子，在600～6500V等级的情况下，载流子浓度n0为1×1012～1×1015cm-3。n型负极层3的表面浓度为1×1019～5×1020cm3，扩散深度为0.5～2μm。n型缓冲层4的厚度Dbuffer如上述公式所示，是n0、▽nbuffer、φeff的函数。In addition, the carrier concentration n 0 of the n - -type drift layer 1 is determined depending on the breakdown voltage level. As an example, in the case of a 600 to 6500 V class, the carrier concentration n 0 is 1×10 12 to 1×10 15 cm -3 . The surface concentration of the n-type negative electrode layer 3 is 1×10 19 -5×10 20 cm 3 , and the diffusion depth is 0.5-2 μm. The thickness D buffer of the n-type buffer layer 4 is a function of n 0 , ▽n buffer , and φ eff as shown in the above formula.

另外，n型缓冲层4的峰值浓度与n－型漂移层1的峰值浓度之比为1×10-4～1×10-1。n型缓冲层4与n－型漂移层1的深度之比为0.1～10。In addition, the ratio of the peak concentration of the n-type buffer layer 4 to the peak concentration of the n − -type drift layer 1 is 1×10 -4 to 1×10 -1 . The ratio of the depths of the n-type buffer layer 4 to the n - type drift layer 1 is 0.1-10.

实施方式2Embodiment 2

图6是表示本发明的实施方式2所涉及的半导体装置的剖视图。实施方式1是二极管，但本实施方式是IGBT(Insulated Gate Bipolar Transistor)。6 is a cross-sectional view showing a semiconductor device according to Embodiment 2 of the present invention. Embodiment 1 is a diode, but this embodiment is an IGBT (Insulated Gate Bipolar Transistor).

p型正极层2是p型基极层，其峰值浓度为1.0×1016～1.0×1018cm-3。在p型正极层2上的晶片表面部局部地形成有p+型扩散层7和n+型发射极层8。n+型发射极层8的峰值浓度为1.0×1018～1.0×1021cm-3，深度为0.2～1.0μm。The p-type anode layer 2 is a p-type base layer, and its peak concentration is 1.0×10 16 to 1.0×10 18 cm −3 . A p + -type diffusion layer 7 and an n + -type emitter layer 8 are partially formed on the wafer surface portion on the p-type positive electrode layer 2 . The peak concentration of the n + type emitter layer 8 is 1.0×10 18 to 1.0×10 21 cm −3 , and the depth is 0.2 to 1.0 μm.

在p型正极层2与n－型漂移层1之间形成有n+型层9。n+型层9的峰值浓度为1.0×1015～1.0×1017cm-3，深度比p型正极层2深0.5～1.0μm。An n + -type layer 9 is formed between the p-type positive electrode layer 2 and the n − -type drift layer 1 . The peak concentration of the n + -type layer 9 is 1.0×10 15 -1.0×10 17 cm -3 , and the depth is 0.5-1.0 μm deeper than the p-type positive electrode layer 2 .

以贯穿n+型发射极层8、p型正极层2以及n+型层9的方式设置有沟槽栅极10。在沟槽栅极10上设置有层间绝缘膜11。正极电极5是发射极电极，与p+型扩散层7连接。代替n型负极层3而设置有p型集电极层12。负极电极6是集电极电极，与p型集电极层12欧姆接触。Trench gate 10 is provided to penetrate n + -type emitter layer 8 , p-type anode layer 2 , and n + -type layer 9 . An interlayer insulating film 11 is provided on the trench gate 10 . The positive electrode 5 is an emitter electrode, and is connected to the p + -type diffusion layer 7 . A p-type collector layer 12 is provided instead of the n-type negative electrode layer 3 . The negative electrode 6 is a collector electrode, and is in ohmic contact with the p-type collector layer 12 .

n型缓冲层4的峰值浓度高于n－型漂移层1，低于p型集电极层12。并且，与实施方式1同样地，将n－型漂移层1与n型缓冲层4的连接部分处的载流子浓度的梯度设为20～2000cm-4。并且，将n型缓冲层4的有效剂量φeff设定为比n－型漂移层1的有效剂量高的1×1012～5×1012cm-2。由此，在IGBT的情况下也能够得到与实施方式1相同的效果。The peak concentration of the n-type buffer layer 4 is higher than that of the n − -type drift layer 1 and lower than that of the p-type collector layer 12 . Furthermore, similarly to Embodiment 1, the gradient of the carrier concentration at the connection portion between the n − -type drift layer 1 and the n-type buffer layer 4 is set to be 20 to 2000 cm −4 . Furthermore, the effective dose φ eff of the n-type buffer layer 4 is set to be 1×10 12 to 5×10 12 cm −2 higher than the effective dose of the n − -type drift layer 1 . Accordingly, the same effect as that of Embodiment 1 can be obtained also in the case of an IGBT.

实施方式3Embodiment 3

图7是表示本发明的实施方式3所涉及的半导体装置的剖视图。代替实施方式1的单层的n型负极层3，将n型负极层3与p型负极层13横向并排而交替地配置。负极电极6欧姆接触于n型负极层3和p型负极层13。因此，p型负极层13通过负极电极6与n型负极层3短路。n型负极层3的峰值浓度高于p型负极层13。7 is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention. Instead of the single-layer n-type negative electrode layer 3 of Embodiment 1, n-type negative electrode layers 3 and p-type negative electrode layers 13 are arranged side by side and alternately. The negative electrode 6 is in ohmic contact with the n-type negative electrode layer 3 and the p-type negative electrode layer 13 . Therefore, the p-type negative electrode layer 13 is short-circuited with the n-type negative electrode layer 3 via the negative electrode 6 . The peak concentration of the n-type negative electrode layer 3 is higher than that of the p-type negative electrode layer 13 .

在n－型漂移层1的深度tn－、n型负极层3的宽度Wn、p型负极层13的宽度Wp之间，下述关系成立。Among the depth tn − of the n − -type drift layer 1 , the width Wn of the n-type negative electrode layer 3 , and the width Wp of the p-type negative electrode layer 13 , the following relationship holds true.

2tn－≥(Wn+Wp)≥tn－/102tn - ≥(Wn+Wp)≥tn - /10

与对比例对比，说明本实施方式的效果。具体地说，说明在设计为耐压1700V的本实施方式与对比例的二极管中，n型缓冲层4的峰值浓度和扩散深度相对于Vrrm、阶跃耐量、以及恢复耐量的依赖性。图8是表示对比例所涉及的半导体装置的剖视图。在对比例中，不存在n型缓冲层4，n型负极层3为单层。The effect of this embodiment will be described in comparison with the comparative example. Specifically, the dependence of the peak concentration and diffusion depth of the n-type buffer layer 4 on Vrrm, step resistance, and recovery resistance in the diodes of the present embodiment and the comparative example designed to withstand a voltage of 1700 V will be described. 8 is a cross-sectional view showing a semiconductor device according to a comparative example. In the comparative example, there is no n-type buffer layer 4, and the n-type negative electrode layer 3 is a single layer.

在此，将非专利文献14的图4的恢复条件相对于峰值电压Vsnap-off的容许程度称为阶跃耐量。阶跃耐量越高，越能够容许高施加电压、低电流、低温、快速电流切断等所谓的硬恢复条件下的动作。另外，将非专利文献14的图7中表示的由施加电压Vcc和最大切断电流密度JA(break)构成的安全动作区域称为恢复耐量。恢复耐量越高，越能够容许高施加电压、大电流密度条件下的恢复动作。Here, the allowable degree of the recovery condition in FIG. 4 of Non-Patent Document 14 with respect to the peak voltage V snap-off is referred to as a step tolerance. The higher the step tolerance, the more permissible it is to operate under so-called hard recovery conditions such as high applied voltage, low current, low temperature, and rapid current cutoff. In addition, the safe operating region composed of the applied voltage Vcc and the maximum breaking current density J A (break) shown in FIG. 7 of Non-Patent Document 14 is called recovery capacity. The higher the recovery capacity, the more it can tolerate the recovery operation under the conditions of high applied voltage and high current density.

图9是表示用于模拟的n型缓冲层的峰值浓度和扩散深度的图。如该图所示，将剂量固定为3.75×1012cm-2，设定以三角形近似法所设定的峰值浓度和扩散深度，模拟出接近高斯分布的n型缓冲层4。另外，与n型缓冲层4的厚度无关，将n－型漂移层1的厚度设为恒定。Fig. 9 is a graph showing the peak concentration and diffusion depth of the n-type buffer layer used in the simulation. As shown in the figure, the dose is fixed at 3.75×10 12 cm -2 , and the peak concentration and diffusion depth set by the triangle approximation method are set to simulate the n-type buffer layer 4 with a nearly Gaussian distribution. In addition, regardless of the thickness of the n-type buffer layer 4 , the thickness of the n − -type drift layer 1 is made constant.

图10是表示对比例和实施方式3中的耐压波形的缓冲层厚度依赖性的模拟结果的图。各个二极管均设计为耐压1700V。图11、12是表示对比例和实施方式3中的活跃恢复(snappy recovery)波形的Vcc依赖性的模拟结果的图。n型缓冲层4的峰值浓度为5×1016cm-3，n型缓冲层4的厚度在图11中为1.5μm，在图12中为50μm。10 is a graph showing simulation results of buffer layer thickness dependence of withstand voltage waveforms in Comparative Example and Embodiment 3. FIG. Each diode is designed to withstand a voltage of 1700V. 11 and 12 are diagrams showing simulation results of the Vcc dependence of the snappy recovery waveform in the comparative example and the third embodiment. The peak concentration of the n-type buffer layer 4 is 5×10 16 cm −3 , and the thickness of the n-type buffer layer 4 is 1.5 μm in FIG. 11 and 50 μm in FIG. 12 .

在对比例中，由主结部处的电场强度的增高造成的碰撞电离所产生的电子利用n－型漂移层1中的高电场而向负极侧移动。由此，电子的浓度超过缓冲层中的载流子浓度，从而根据泊松方程的关系，n型缓冲层4中的电场的梯度逆转，在主结的基础上，在负极侧电场强度也增高。因此，在对比例中，n型缓冲层4越厚，负微分电阻NDR的特性从JR＝10A/cm2左右起越表现得显著。在JR＝100～1000A/cm2附近，在主结和负极侧两者处产生碰撞电离，从主结侧和负极侧两者向n－型漂移层1中供给电子和空穴，达到二次击穿。In the comparative example, electrons generated by impact ionization caused by an increase in the electric field intensity at the main junction move toward the negative electrode side by the high electric field in the n − -type drift layer 1 . As a result, the concentration of electrons exceeds the carrier concentration in the buffer layer, and the gradient of the electric field in the n-type buffer layer 4 is reversed according to the relationship of Poisson's equation, and the electric field intensity on the negative electrode side also increases on the basis of the main junction. . Therefore, in the comparative example, the thicker the n-type buffer layer 4 is, the more prominent the characteristic of the negative differential resistance NDR is from about JR=10A/cm 2 . Near JR=100～1000A/cm 2 , impact ionization occurs at both the main junction and the negative electrode side, and electrons and holes are supplied to the n - type drift layer 1 from both the main junction side and the negative electrode side to achieve secondary breakdown.

另一方面，在本实施方式中，耐压波形中没有显现出NDR特性，在n型缓冲层4较薄的情况下，在耐压波形的JR＝1A/cm2附近出现2次击穿。该小电流区域中的二次击穿导致二极管的恢复SOA中的最大切断电流密度的降低、雪崩耐量的降低，因此要求使二次击穿的发生点大电流化。另一方面，在表现出NDR特性的二极管构造中，在恢复时负极侧的电场上升，由此发生电压浪涌和阶跃，容易以其作为触发而发生高频振荡(参照图11、12)。因此，二极管的耐压波形需要接近直线型的线，而不表现出由NDR特性、二次击穿产生的S形曲线。从图10可以看出，优选使n型缓冲层4较厚。On the other hand, in the present embodiment, the NDR characteristic does not appear in the withstand voltage waveform, and when the n-type buffer layer 4 is thin, secondary breakdown occurs near JR=1A/cm 2 of the withstand voltage waveform. Secondary breakdown in this small current region leads to a decrease in the maximum off-current density in the recovery SOA of the diode and a decrease in the avalanche withstand capacity, and therefore it is required to increase the current at the occurrence point of the secondary breakdown. On the other hand, in a diode structure exhibiting NDR characteristics, the electric field on the negative electrode side rises during recovery, thereby generating voltage surges and steps, which are easily used as triggers to generate high-frequency oscillations (see Figures 11 and 12) . Therefore, the withstand voltage waveform of the diode needs to be close to a straight line without showing an S-shaped curve caused by NDR characteristics and secondary breakdown. As can be seen from FIG. 10, it is preferable to make the n-type buffer layer 4 thicker.

但是，如果使n－型漂移层1的厚度恒定，仅仅使n型缓冲层4变厚，则导通状态下的电阻成分变大，导致VF的增加(恶化)。因此，在本实施方式中，将n－型漂移层1与n型缓冲层4的连接部分处的载流子浓度的梯度设为20～2000cm-4。通过如上述所示使连接部分处的浓度变化变缓，从而能够防止耐压波形的二次击穿以及NDR，抑制VF的增加，并且抑制恢复时的连接部分处的电场强度的增高。其结果，能够防止由负极侧的电场强度的增高而产生的阶跃、以及以该阶跃作为触发而产生的高频振荡，因此能够实现高振荡耐量。However, if the thickness of the n − -type drift layer 1 is kept constant and only the n-type buffer layer 4 is thickened, the resistance component in the on state increases, resulting in an increase (deterioration) of VF. Therefore, in the present embodiment, the gradient of the carrier concentration at the connection portion between the n - -type drift layer 1 and the n-type buffer layer 4 is set to be 20 to 2000 cm -4 . Slowing the concentration change at the connection portion as described above prevents secondary breakdown of the withstand voltage waveform and NDR, suppresses an increase in VF, and suppresses an increase in electric field strength at the connection portion during recovery. As a result, it is possible to prevent a step caused by an increase in the electric field intensity on the negative electrode side and high-frequency oscillation triggered by the step, thereby realizing high oscillation tolerance.

另外，将由(Wn+Wp)表示的宽度称为RFC单元间距(cell pitch)。如果使RFC单元间距变窄，则VF增加，EREC减少。即，VF-EREC折衷曲线向高速侧偏移。因此，在将本实施方式应用于要装入逆变器的续流二极管的情况下，通过与用途相匹配地调整RFC单元间距，从而能够调整VF-EREC折衷特性。但是，如果将RFC单元间距设定得过窄，则阶跃耐量降低，相反，如果设定得过宽，则恢复耐量降低。In addition, the width represented by (Wn+Wp) is called an RFC cell pitch (cell pitch). If the RFC cell pitch is narrowed, VF increases and EREC decreases. That is, the VF-EREC tradeoff curve shifts to the high-speed side. Therefore, when the present embodiment is applied to a freewheeling diode to be incorporated in an inverter, the VF-EREC trade-off characteristic can be adjusted by adjusting the RFC cell pitch according to the application. However, if the RFC cell pitch is set too narrow, the step tolerance will decrease, and conversely, if it is set too wide, the recovery tolerance will decrease.

另外，将由(Wp/(Wn+Wp))表示的比率称为RFC单元短路率(cell short rate)。如果使RFC单元短路率变小，则VF增加，EREC减少。即，VF-EREC折衷曲线向高速侧偏移。因此，在将本实施方式应用于要装入逆变器的续流二极管的情况下，通过与用途相匹配地调整RFC单元短路率，从而能够调整VF-EREC折衷特性。但是，如果将RFC单元短路率设定得过小，则阶跃耐量降低，交叉点(cross point)增加，相反，如果设定得过大，则恢复耐量降低。In addition, the ratio represented by (Wp/(Wn+Wp)) is called RFC cell short rate (cell short rate). If the short-circuit rate of the RFC unit is reduced, VF increases and EREC decreases. That is, the VF-EREC tradeoff curve shifts to the high-speed side. Therefore, when the present embodiment is applied to a freewheeling diode to be incorporated in an inverter, the VF-EREC trade-off characteristic can be adjusted by adjusting the RFC unit short circuit ratio according to the application. However, if the short-circuit ratio of the RFC cell is set too small, the step resistance decreases and the cross point (cross point) increases, and conversely, if it is set too large, the recovery capacity decreases.

如上述所示，在本实施方式中，通过调整RFC单元间距或RFC单元短路率，从而能够控制VF-EREC折衷特性而不依赖于寿命控制方法。As described above, in the present embodiment, by adjusting the RFC cell pitch or the RFC cell short circuit rate, it is possible to control the VF-EREC tradeoff characteristic without depending on the lifetime control method.

另外，如果减少p型负极层13的剂量，则阶跃耐量降低，但能够抑制EREC和泄漏电流。如果增加P型负极层13的剂量，则得到相反的结果。与此相对，在本实施方式中，能够确保阶跃耐量和恢复耐量，能够扩大p型负极层13的剂量的设定容许范围。In addition, if the dose of the p-type negative electrode layer 13 is reduced, the step resistance decreases, but EREC and leakage current can be suppressed. If the dosage of the P-type negative electrode layer 13 is increased, the opposite result is obtained. On the other hand, in the present embodiment, the step tolerance and the recovery tolerance can be ensured, and the allowable range for setting the dose of the p-type negative electrode layer 13 can be expanded.

在单纯的p-n结中，VF的温度依赖性基本为正，如果温度上升，则电流变得容易流动。在将功率芯片并联连接而得到的大容量的功率模块中，如果芯片的温度分布产生不均匀，则发生诸如在发热量大的芯片中进一步流过电流而发热这样的正反馈，有可能引起模块的损坏。因此，室温的VF曲线与高温的VF曲线相交叉的电流值(交叉点)优选较低。在本实施方式中，能够降低正极和负极的有效的剂量，降低来自双方的载流子注入效率，因此能够实现低电流值的交叉点。In a simple p-n junction, the temperature dependence of VF is almost positive, and current becomes easier to flow when the temperature rises. In a large-capacity power module obtained by connecting power chips in parallel, if the temperature distribution of the chips is not uniform, positive feedback such as further current flowing through the chips with large heat generation and heat generation will occur, which may cause module damage. damage. Therefore, the current value (intersection point) at which the VF curve at room temperature intersects with the VF curve at high temperature is preferably low. In the present embodiment, the effective dosage of the positive electrode and the negative electrode can be reduced, and the carrier injection efficiency from both can be reduced, so that a cross point of a low current value can be realized.

另外，也可以使负极电极6与n型负极层3欧姆接触，与p型负极层13肖特基接触。负极电极6与p型负极层13之间的肖特基势垒差较大，由此，变为与对寄生的pnp晶体管附加了电阻成分相同的状态，能够抑制由寄生的pnp晶体管动作产生的器件纵向的电流。其结果，能够实现高恢复SOA和高雪崩耐量。In addition, the negative electrode 6 may be in ohmic contact with the n-type negative electrode layer 3 and in Schottky contact with the p-type negative electrode layer 13 . The Schottky barrier difference between the negative electrode 6 and the p-type negative electrode layer 13 is large, thereby, it becomes the same state as adding a resistance component to the parasitic pnp transistor, and it is possible to suppress the disturbance caused by the operation of the parasitic pnp transistor. current in the vertical direction of the device. As a result, high recovery SOA and high avalanche tolerance can be realized.

实施方式4Embodiment 4

图13是表示本发明的实施方式4所涉及的半导体装置的后视图。图14是沿图13的I-II的剖视图。代替实施方式3的单层的n型缓冲层4，将n型缓冲层4与n型缓冲层14横向并排而交替地配置。在n－型漂移层1与n型负极层3之间设置有n型缓冲层4，在n－型漂移层1与p型负极层13之间设置有n型缓冲层14。n型缓冲层4、14的峰值浓度高于n－型漂移层1，低于n型负极层3。n型缓冲层4的峰值浓度高于n型缓冲层14。其他结构与实施方式3相同。13 is a rear view showing a semiconductor device according to Embodiment 4 of the present invention. Fig. 14 is a sectional view taken along line I-II of Fig. 13 . Instead of the single-layer n-type buffer layer 4 of Embodiment 3, n-type buffer layers 4 and n-type buffer layers 14 are arranged side by side and alternately. An n-type buffer layer 4 is provided between the n − -type drift layer 1 and the n-type negative electrode layer 3 , and an n-type buffer layer 14 is provided between the n − -type drift layer 1 and the p-type negative electrode layer 13 . The peak concentrations of the n-type buffer layers 4 and 14 are higher than the n - type drift layer 1 and lower than the n-type negative electrode layer 3 . The peak concentration of n-type buffer layer 4 is higher than that of n-type buffer layer 14 . Other structures are the same as those in Embodiment 3.

图15是沿图13的III-IV的剖视图。设置有p型正极层2的区域是活性区域，与其相比外侧的区域是终端区域。在终端区域的正极侧设置有通常的p型保护环层15，在终端区域的最外周部设置有n型沟道截断层16。p型保护环层15的峰值浓度高于p型正极层2，n型沟道截断层16的峰值浓度高于n－型漂移层1。Fig. 15 is a sectional view along line III-IV of Fig. 13 . The region where the p-type positive electrode layer 2 is provided is the active region, and the region outside it is the termination region. A normal p-type guard ring layer 15 is provided on the positive electrode side of the termination region, and an n-type channel stopper layer 16 is provided on the outermost peripheral portion of the termination region. The peak concentration of the p-type guard ring layer 15 is higher than that of the p-type anode layer 2 , and the peak concentration of the n-type channel stop layer 16 is higher than that of the n − -type drift layer 1 .

终端区域的负极构造从向活性区域侧与p型正极层2的最外周部分离了距离WGR：10～500μm的位置开始。终端区域的负极构造是n型层17和p型层18的两层构造。The negative electrode structure in the terminal region starts from a position separated from the outermost peripheral portion of the p-type positive electrode layer 2 by a distance WGR: 10 to 500 μm toward the active region side. The negative electrode structure of the termination region is a two-layer structure of n-type layer 17 and p-type layer 18 .

在本实施方式中，通过提高n型负极层3上的n型缓冲层4的剂量，从而提高导通状态下的来自负极侧的电子的注入效率。另外，在施加L负载电路中的感应电动势而使装置达到雪崩状态时，耗尽层难以到达p型负极层13，耐压波形的NDR(二次击穿)得到抑制。其结果，能够实现低VF和高雪崩耐量。将雪崩状态的容许程度称为雪崩耐量。In this embodiment, by increasing the dose of n-type buffer layer 4 on n-type negative electrode layer 3 , the injection efficiency of electrons from the negative electrode side in the on state is improved. In addition, when the device enters an avalanche state by applying induced electromotive force in the L load circuit, the depletion layer hardly reaches the p-type negative electrode layer 13, and NDR (secondary breakdown) of the withstand voltage waveform is suppressed. As a result, low VF and high avalanche resistance can be realized. The allowable degree of the avalanche state is called avalanche tolerance.

另外，n型负极层3和p型负极层13为条带图案。由此，能够简单地设计反映出设想的n型负极层3与p型负极层13之比的图案。In addition, the n-type negative electrode layer 3 and the p-type negative electrode layer 13 are in a stripe pattern. Accordingly, it is possible to easily design a pattern reflecting the ratio of the assumed n-type negative electrode layer 3 to the p-type negative electrode layer 13 .

图16是表示本发明的实施方式4所涉及的半导体装置的变形例1的仰视图。如上述所示，即使终端区域的负极为n型，也能够得到与上述相同的效果。16 is a bottom view showing Modification 1 of the semiconductor device according to Embodiment 4 of the present invention. As described above, even if the negative electrode of the terminal region is n-type, the same effect as above can be obtained.

图17是表示本发明的实施方式4所涉及的半导体装置的变形例2的仰视图。n型负极层3为点图案。由此，能够实现对角部也进行了考虑的图案设计，能够实现均匀的器件动作。其结果，能够实现高恢复SOA。此外，p型负极层13为点图案也能够得到相同的效果。17 is a bottom view showing Modification 2 of the semiconductor device according to Embodiment 4 of the present invention. The n-type negative electrode layer 3 is a dot pattern. Accordingly, it is possible to realize a pattern design that also takes into account corners, and to realize uniform device operation. As a result, a high recovery SOA can be realized. In addition, the same effect can be obtained even if the p-type negative electrode layer 13 is a dot pattern.

实施方式5Embodiment 5

图18是表示本发明的实施方式5所涉及的半导体装置的剖视图。n型缓冲层4的深度比n型缓冲层14深。其他结构与实施方式4相同。在此情况下，也能够得到与实施方式4相同的效果。18 is a cross-sectional view showing a semiconductor device according to Embodiment 5 of the present invention. The n-type buffer layer 4 is deeper than the n-type buffer layer 14 . Other structures are the same as those in Embodiment 4. Also in this case, the same effect as that of Embodiment 4 can be obtained.

实施方式6Embodiment 6

图19是表示本发明的实施方式6所涉及的半导体装置的剖视图。代替实施方式4的单层的p型正极层2，将p型正极层2与p型正极层19横向并排而交替地配置。正极电极5与p型正极层2、19欧姆接触。因此，p型正极层19通过正极电极5与p型正极层2短路。p型正极层19的峰值浓度低于p型正极层2。p型正极层2与p型正极层19的峰值浓度比为0.5～500。19 is a cross-sectional view showing a semiconductor device according to Embodiment 6 of the present invention. Instead of the single-layer p-type positive electrode layer 2 of Embodiment 4, p-type positive electrode layers 2 and p-type positive electrode layers 19 are arranged side by side and alternately. The positive electrode 5 is in ohmic contact with the p-type positive electrode layer 2 , 19 . Therefore, p-type positive electrode layer 19 is short-circuited to p-type positive electrode layer 2 via positive electrode 5 . The p-type positive electrode layer 19 has a lower peak concentration than the p-type positive electrode layer 2 . The peak concentration ratio of the p-type positive electrode layer 2 to the p-type positive electrode layer 19 is 0.5-500.

通过设置低浓度的p型正极层19，从而导通状态下的正极侧的注入效率得到抑制，因此导通状态的正极侧的载流子浓度降低，能够抑制振荡的触发、即负极侧的电场强度的上升。另外，在导通状态下n－型漂移层1内的载流子少，因此能够抑制在恢复时载流子集中于终端区域与活性区域的边界部而导致击穿的现象。其结果，能够实现高恢复SOA、高振荡耐量、低VF、低交叉点、高浪涌电流耐量。By providing the low-concentration p-type positive electrode layer 19, the injection efficiency on the positive electrode side in the on state is suppressed, so the carrier concentration on the positive electrode side in the on state is reduced, and the trigger of oscillation, that is, the electric field on the negative electrode side can be suppressed. Intensity rises. In addition, since there are few carriers in the n - -type drift layer 1 in the on state, it is possible to suppress the phenomenon that the carriers concentrate at the boundary between the termination region and the active region and cause breakdown during recovery. As a result, high recovery SOA, high oscillation tolerance, low VF, low crossover point, and high surge current tolerance can be realized.

实施方式7Embodiment 7

图20是表示本发明的实施方式7所涉及的半导体装置的剖视图。p型正极层19仅设置在p型正极层2的顶面的一部分。p型正极层19的深度相对于p型正极层2的深度之比为0.1～0.9。在此情况下，也能够得到与实施方式6相同的效果。20 is a cross-sectional view showing a semiconductor device according to Embodiment 7 of the present invention. P-type positive electrode layer 19 is provided only on a part of the top surface of p-type positive electrode layer 2 . The ratio of the depth of the p-type positive electrode layer 19 to the depth of the p-type positive electrode layer 2 is 0.1 to 0.9. Also in this case, the same effect as that of Embodiment 6 can be obtained.

实施方式8Embodiment 8

图21是表示本发明的实施方式8所涉及的半导体装置的剖视图。在终端区域的n－型漂移层1的底面，仅设置有单层的n型层17。负极电极6与n型层17接触而电连接。n型层17具有1×1015～1×1016cm-3的峰值浓度。由此，n型缓冲层14相对于负极电极6的接触电阻变大。因此，能够抑制在导通状态下来自终端区域的负极侧的电子的注入，提高恢复SOA。21 is a cross-sectional view showing a semiconductor device according to Embodiment 8 of the present invention. Only a single n-type layer 17 is provided on the bottom surface of the n − -type drift layer 1 in the termination region. Negative electrode 6 contacts and is electrically connected to n-type layer 17 . The n-type layer 17 has a peak concentration of 1×10 15 to 1×10 16 cm −3 . As a result, the contact resistance of n-type buffer layer 14 to negative electrode 6 increases. Therefore, injection of electrons from the negative electrode side of the termination region in the on state can be suppressed, and recovery SOA can be improved.

实施方式9Embodiment 9

图22是表示本发明的实施方式9所涉及的半导体装置的剖视图。n型缓冲层4为单层，并且终端区域的负极构造也为n型层17单层。由此，与实施方式8相比，能够进一步简化结构。22 is a cross-sectional view showing a semiconductor device according to Embodiment 9 of the present invention. The n-type buffer layer 4 is a single layer, and the negative electrode structure in the terminal region is also a single-layer n-type layer 17 . Accordingly, compared with Embodiment 8, the configuration can be further simplified.

实施方式10Embodiment 10

图23是表示本发明的实施方式10所涉及的半导体装置的剖视图。在终端区域的最外周部设置有n型沟道截断缓冲层20。在n型沟道截断缓冲层20中设置有n型沟道截断层21以及p型沟道截断层22。n型沟道截断缓冲层20的峰值浓度高于n－型漂移层1。n型沟道截断层21的峰值浓度高于n型沟道截断缓冲层20以及p型沟道截断层22。由此，能够实现高恢复SOA。23 is a cross-sectional view showing a semiconductor device according to Embodiment 10 of the present invention. An n-type channel stopper buffer layer 20 is provided on the outermost peripheral portion of the termination region. An n-type channel stopper layer 21 and a p-type channel stopper layer 22 are provided in the n-type channel stopper buffer layer 20 . The peak concentration of the n-type channel stop buffer layer 20 is higher than that of the n − -type drift layer 1 . The peak concentration of the n-type channel stopper layer 21 is higher than that of the n-type channel stopper buffer layer 20 and the p-type channel stopper layer 22 . Thereby, a high recovery SOA can be realized.

实施方式11Embodiment 11

图24是表示本发明的实施方式11所涉及的半导体装置的剖视图。代替通常的p型保护环层15，设置有LNFLR(Linearly-Narrowed Field Limiting Ring)构造23。LNFLR构造23是从活性区域朝向终端区域周期性地并排的多个p型层。该多个p型层朝向终端区域具有线性的浓度梯度。24 is a cross-sectional view showing a semiconductor device according to Embodiment 11 of the present invention. Instead of the usual p-type guard ring layer 15, an LNFLR (Linearly-Narrowed Field Limiting Ring) structure 23 is provided. The LNFLR structure 23 is a plurality of p-type layers periodically juxtaposed from the active region toward the terminal region. The plurality of p-type layers has a linear concentration gradient towards the termination region.

在活性区域的p型正极层2与LNFLR构造23之间设置有RESURF(Reduced SurfaceField)构造24。RESURF构造24具有在活性区域端形成的深的p层、以及扩散深度与LNFLR构造23的扩散层相同的p层。RESURF构造24的剂量为2×1012/m2，宽度为5～100μm。通过设置RESURF构造24，从而能够缓和恢复时的电场峰值。A RESURF (Reduced Surface Field) structure 24 is provided between the p-type positive electrode layer 2 and the LNFLR structure 23 in the active region. The RESURF structure 24 has a deep p layer formed at the end of the active region, and a p layer having the same diffusion depth as the diffusion layer of the LNFLR structure 23 . The RESURF structure 24 has a dose of 2×10 12 /m 2 and a width of 5-100 μm. By providing the RESURF structure 24, it is possible to relax the electric field peak at the time of recovery.

实施方式12Embodiment 12

图25是表示本发明的实施方式12所涉及的半导体装置的剖视图。代替实施方式11的RESURF构造24，在本实施方式中，设置有VLD(Variation of Lateral Doping)构造25。VLD构造25具有在活性区域端形成的深的p层、以及为了连接该深的p层与LNFLR扩散层的深度而具有梯度的p层。25 is a cross-sectional view showing a semiconductor device according to Embodiment 12 of the present invention. In place of the RESURF structure 24 of Embodiment 11, in this embodiment, a VLD (Variation of Lateral Doping) structure 25 is provided. The VLD structure 25 has a deep p layer formed at the edge of the active region, and a p layer having a gradient to connect the deep p layer and the depth of the LNFLR diffusion layer.

实施方式13Embodiment 13

图26是表示本发明的实施方式13所涉及的半导体装置的剖视图。在活性区域中设置有IGBT，在终端区域中设置有LNFLR构造23。在此情况下，也能够得到与实施方式11相同的效果。26 is a cross-sectional view showing a semiconductor device according to Embodiment 13 of the present invention. An IGBT is provided in the active area, and an LNFLR structure 23 is provided in the termination area. Also in this case, the same effect as that of Embodiment 11 can be obtained.

此外，本发明的半导体装置不限于由硅形成，也可以由带隙大于硅的宽带隙半导体形成。宽带隙半导体例如是碳化硅、氮化镓类材料、或者金刚石。由这样的宽带隙半导体形成的半导体装置的耐电压性、容许电流密度高，因此能够实现小型化。通过使用该小型化的装置，由此，组装有该装置的半导体模块也能够实现小型化。另外，元件的耐热性高，因此能够将散热器的散热片小型化，将水冷部风冷化，因而能够进一步使半导体模块小型化。另外，元件的功率损耗低、效率高，因此能够使半导体模块高效化。In addition, the semiconductor device of the present invention is not limited to being formed of silicon, but may be formed of a wide bandgap semiconductor having a band gap larger than that of silicon. Wide bandgap semiconductors are, for example, silicon carbide, gallium nitride-like materials, or diamond. A semiconductor device formed of such a wide bandgap semiconductor has high withstand voltage and allowable current density, and thus can be miniaturized. By using this miniaturized device, a semiconductor module incorporating the device can also be miniaturized. In addition, since the heat resistance of the element is high, it is possible to reduce the size of the fins of the heat sink, and to air-cool the water cooling unit, thereby further reducing the size of the semiconductor module. In addition, since the power loss of the element is low and the efficiency is high, it is possible to increase the efficiency of the semiconductor module.

另外，在上述实施方式中，以1200V或1700V等级的低/中耐压等级为例进行了说明。但是，无论耐压等级如何，都能够得到上述的效果。In addition, in the above-mentioned embodiment, the low/medium withstand voltage class of 1200V or 1700V class has been described as an example. However, the above effects can be obtained regardless of the withstand voltage level.

标号的说明Explanation of labels

1n－型漂移层，2、19p型正极层，3n型负极层，4、14n型缓冲层，6负极电极，12p型集电极层，13p型负极层，17n型层，20n型沟道截断缓冲层，21n型沟道截断层，22p型沟道截断层，23LNFLR构造，24RESURF构造，25VLD构造。1n - type drift layer, 2, 19p positive layer, 3n negative layer, 4, 14n buffer layer, 6 negative electrode, 12p collector layer, 13p negative layer, 17n layer, 20n channel cut-off buffer layer, 21n type channel stop layer, 22p type channel stop layer, 23LNFLR structure, 24RESURF structure, 25VLD structure.

Claims (15)

1. a kind of semiconductor device, it is characterised in that possess：
N-type drift layer；
P-type anode layer, it is arranged on the top surface of the n-type drift layer；
Negative electrode layer, it is arranged on the bottom surface of the n-type drift layer；And
N-type buffer layer, it is arranged between the n-type drift layer and the negative electrode layer,
The peak concentration of the N-type buffer layer is higher than the n-type drift layer, less than the negative electrode layer,
The gradient of the n-type drift layer and the carrier concentration of the connecting portion office of the N-type buffer layer is 20~2000cm-4。
2. semiconductor device according to claim 1, it is characterised in that
The effective dose of the N-type buffer layer is 1 × 1012~5 × 1012cm-2, higher than the n-type drift layer.
3. semiconductor device according to claim 1 or 2, it is characterised in that
The negative electrode layer is n-type.
4. semiconductor device according to claim 1 or 2, it is characterised in that
The negative electrode layer is p-type.
5. semiconductor device according to claim 1 or 2, it is characterised in that
The negative electrode layer has the n-type negative electrode layer and p-type negative electrode layer configured laterally side by side.
6. semiconductor device according to claim 5, it is characterised in that
The N-type buffer layer have be arranged on the first N-type buffer layer between the n-type drift layer and the n-type negative electrode layer, with And the second N-type buffer layer between the n-type drift layer and the p-type negative electrode layer is arranged on,
The peak concentration of first N-type buffer layer is higher than second N-type buffer layer.
7. semiconductor device according to claim 5, it is characterised in that
The semiconductor device is also equipped with negative electrode, the negative electrode and the n-type negative electrode layer Ohmic contact, with the p-type Negative electrode layer Schottky contacts.
8. semiconductor device according to claim 5, it is characterised in that
The n-type negative electrode layer and the p-type negative electrode layer are strip pattern.
9. semiconductor device according to claim 5, it is characterised in that
The n-type negative electrode layer or the p-type negative electrode layer are dot pattern.
10. semiconductor device according to claim 1 or 2, it is characterised in that
There is the p-type anode layer the first p-type anode layer and peak concentration to be less than the second p-type of the first p-type anode layer Anode layer,
The peak concentration ratio of the first p-type anode layer and the second p-type anode layer is less than or equal to 500.
11. semiconductor device according to claim 10, it is characterised in that
The depth of the second p-type anode layer is 0.1~0.9 relative to the ratio of the depth of the first p-type anode layer.
12. semiconductor device according to claim 1 or 2, it is characterised in that
The semiconductor device possesses：
N-layer, it is arranged at the bottom surface of the n-type drift layer in terminal area, has 1 × 1015~1 × 1016cm-3Peak value Concentration；And
Negative electrode, it contacts and electrically connected with the negative electrode layer and the n-layer.
13. semiconductor device according to claim 1 or 2, it is characterised in that
The semiconductor device has：
N-type channel blocks cushion, and it is arranged on the most peripheral portion of terminal area；And
N-type channel blocks layer and p-type raceway groove blocks layer, and they are arranged on the n-type channel and blocked in cushion,
The peak concentration that the n-type channel blocks cushion is higher than the n-type drift layer,
The peak concentration that the n-type channel blocks layer blocks cushion and the p-type raceway groove blocks higher than the n-type channel Layer.
14. semiconductor device according to claim 1 or 2, it is characterised in that
The semiconductor device is also equipped with：
LNFLR is constructed, and it is arranged on terminal area, and the LNFLR is linear narrowing field limiting ring；And
RESURF is constructed, and it is arranged on the outer end of the p-type anode layer, and the RESURF is to reduce surface field.
15. semiconductor device according to claim 1 or 2, it is characterised in that
The semiconductor device is also equipped with：
LNFLR is constructed, and it is arranged on terminal area, and the LNFLR is linear narrowing field limiting ring；And
VLD is constructed, and it is arranged on the outer end of the p-type anode layer, and the VLD is variety lateral doping.
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