CN105281755A - Delay phase-locked loop and filtering updating and control method of the same - Google Patents
Delay phase-locked loop and filtering updating and control method of the same Download PDFInfo
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- CN105281755A CN105281755A CN201510793693.9A CN201510793693A CN105281755A CN 105281755 A CN105281755 A CN 105281755A CN 201510793693 A CN201510793693 A CN 201510793693A CN 105281755 A CN105281755 A CN 105281755A
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Abstract
The invention discloses a filtering updating and control method for a delay phase-locked loop. The method comprises the steps: when a power off mode exits, a memory control system emits a power off mode exit signal to a counter; the counter outputs a first signal to a logic control circuit; and the logic control circuit can control the delay chain through a speed updating circuit, and can adjust the updated speed as 1step/(k*tck) after the delay chain is updated several times in the same direction continuously by means of the 1step/(m*tck) update speed, wherein k>m. When the power off mode exits, a DLL can automatically adjust the update speed so as to avoid generation of overshoot because of incorrect and excessive update and guarantee that the rising edges of VCLK and DQS are aligned, so that no error occurs during the system operation.
Description
[technical field]
The present invention relates to PHASE-LOCKED LOOP PLL TECHNIQUE field, particularly a kind of delay phase-locked loop and filtering thereof more new control method.
[background technology]
Refer to shown in Fig. 1, the operation principle of existing delay phase-locked loop DLL is: input clock enters DLL delay chain, output clock is produced after postponing, output clock produces feedback clock after feedback circuit, the signal that input clock and feedback clock export UP or DN after DLL phase discriminator carries out phase compare goes increase or the minimizing of control DLL delay chain to DLL logic control circuit, until the phase alignment of input clock and feedback clock.When input clock samples the high level of feedback clock, up=1, dn=0; When input clock samples the low level of feedback clock, dn=1, up=0.After DLL locking, the phase alignment of input clock and feedback clock, the phase place of input clock and DQS is also alignd simultaneously.
The renewal speed of DLL: the initial phase relationship of input clock and feedback clock as shown in Figure 2.Because the initial phase difference td0 of input clock and feedback clock is comparatively large, thus DLL with one faster speed 1step/ (n*tck) (representing n clock cycle renewal time lag of first order chain) remove the phase difference of renewal input clock and feedback clock; Tck is the clock cycle.
When the phase difference of input clock and feedback clock is almost 0, as shown in Figure 3.In order to filter some the very little noises on input clock and power supply, the renewal speed of DLL can be slack-off, and become 1step/ (m*tck) from 1step/ (n*tck), m>n, namely renewal speed is slack-off.
There is following technical problem in prior art:
Under normal circumstances, it is rational for changing renewal speed after DLL locking, effectively can filter some the very little noises on input clock and power supply, keeps the stable of DLL delay chain.But, after DLL locking, chip can enter into power-down mode, when power-down mode exits, power supply has a larger fluctuation, the amplitude of this fluctuation and duration considerably beyond some on input clock and power supply normally, very little noise fluctuations, as shown in Figure 4.
Due to the instability of power supply, cause occur very large change the time of delay of DLL delay chain, thus cause the phase difference of input clock VCLK and alignment of data signal DQS not to be be almost 0, but have a phase difference δ, as shown in Figure 5.
After power-down mode exits, system needs the rising edge of VCLK and DQS to be in aligned condition, if power-supply fluctuation is comparatively large, the length that DLL needs to upgrade DLL delay chain is to allow the rising edge alignment of VCLK and DQS.Suppose that the decline of supply voltage causes DLL to need to reduce the number of DLL delay chain, DLL have updated x*1step time, and then due to the recovery of supply voltage, the length of DLL delay chain, in minimizing, needs again DLL to increase the number of delay chain.In theory, when supply voltage returns to the value before labile state, because supply voltage DLL when declining decreases x*1step, DLL also needs to increase x*1step, and the rising edge of such VCLK and DQS is just in aligned condition.Now likely Problems existing is, when supply voltage returns to the value before labile state, DLL does not also complete the increase of x*1step, and reason is the too much number decreasing delay chain of DLL.
[summary of the invention]
The object of the present invention is to provide a kind of delay phase-locked loop and filtering thereof more new control method, to solve the problems of the technologies described above.
To achieve these goals, the present invention adopts following technical scheme:
A kind of delay phase-locked loop, comprises delay chain, phase discriminator, feedback circuit, increasing/subtract circuit, renewal speed circuit, logic control circuit and configurable counter; Input clock signal line connection delay chain and phase discriminator; The output of delay chain connects clock signal line; The output of the input connection delay chain of feedback circuit, the output of feedback circuit connects phase discriminator; The output of phase discriminator connects logic control circuit, and the output of logic control circuit is by increasing/subtracting circuit and renewal speed circuit connection delay chain; The input connected storage control system of configurable counter, the power-down mode sent for reception memorizer control system exits signal, and the output of configurable counter connects logic control circuit.
Further, after power-down mode exits, memory control system sends power-down mode and exits signal to configurable counter, and configurable counter exports the first signal to logic control circuit; Logic control circuit is by renewal speed current controlled delay chain, make it after the renewal speed of continuous several times 1step/ (m*tck) upgrades toward same direction, renewal speed is adjusted to 1step/ (k*tck), wherein k>m.
Further, when supply voltage recovers, DLL terminates the renewal in a direction, and when upgrading toward rightabout, renewal speed reverts to 1step/ (m*tck).
Further, described several times are N time, N be more than or equal to 2 natural number.
A kind of filtering more new control method of delay phase-locked loop, comprise the following steps: after power-down mode exits, memory control system sends power-down mode and exits signal to configurable counter, and configurable counter exports the first signal to logic control circuit; Logic control circuit is by renewal speed current controlled delay chain, make it after the renewal speed of continuous several times 1step/ (m*tck) upgrades toward same direction, renewal speed is adjusted to 1step/ (k*tck), wherein k>m.
Further, when supply voltage recovers, DLL terminates the renewal in a direction, and when upgrading toward rightabout, renewal speed reverts to 1step/ (m*tck).
Further, described several times are N time, N be more than or equal to 2 natural number.
Relative to prior art, the present invention has following beneficial effect: the present invention is when power-down mode exits, and DLL can adjust renewal speed automatically, avoids the too much renewal of mistake and produces overshoot; To ensure the rising edge alignment of VCLK and DQS, Dynamic System there will not be mistake.
[accompanying drawing explanation]
Fig. 1 is the structural representation of existing delay phase-locked loop;
Fig. 2 is the initial phase schematic diagram of input clock and feedback clock;
Fig. 3 is the phase place schematic diagram of input clock and feedback clock after DLL locking;
Fig. 4 is the fluctuation schematic diagram of power-down mode when exiting on power supply;
Fig. 5 is because power-supply fluctuation causes having between VCLK and DQS the schematic diagram of phase difference δ;
Fig. 6 is the structural representation of delay phase-locked loop of the present invention;
Fig. 7 is the contrast schematic diagram that the renewal speed of filtering of the present invention more new control method and existing control method changes when power-down mode exits.
[embodiment]
Refer to shown in Fig. 6, a kind of delay phase-locked loop of the present invention, comprises delay chain, phase discriminator, feedback circuit, increasing/subtract circuit, renewal speed circuit, logic control circuit and configurable counter.
Input clock signal line connection delay chain and phase discriminator; The output of delay chain connects clock signal line; The output of the input connection delay chain of feedback circuit, the output of feedback circuit connects phase discriminator; The output of phase discriminator connects logic control circuit, and the output of logic control circuit is by increasing/subtracting circuit and renewal speed circuit connection delay chain; The input connected storage control system of configurable counter, the power-down mode that reception memorizer control system sends exits signal, and the output of configurable counter connects logic control circuit.
Refer to shown in Fig. 7, the filtering more new control method of a kind of delay phase-locked loop of the present invention, comprises the following steps:
After power-down mode exits, memory control system sends power-down mode and exits signal to configurable counter, configurable counter exports the first signal to logic control circuit, logic control circuit is by renewal speed current controlled delay chain, make it after the renewal speed of the secondary 1step/ of N continuous (m*tck) upgrades (length normally reducing DLL delay chain) toward same direction, renewal speed is adjusted to 1step/ (k*tck), like this to reduce the speed upgraded; Wherein k>m, N are configured according to different operating modes by user, and N is preferably greater than the natural number equaling 2.Because DLL continuous several times upgrades toward same direction, mean and soon close to more fresh target, renewal speed may be needed to lower, otherwise likely produce overshoot.When the recovery due to supply voltage, DLL terminates the renewal (normally reducing the length of DLL delay chain) in a direction, during toward rightabout renewal (namely DLL needs the length increasing DLL delay chain), renewal speed reverts to 1step/ (m*tck), to suppress some the less noises on input clock and power supply.
The inventive method is when power-down mode exits, and DLL can adjust renewal speed automatically, avoids the too much renewal of mistake and produces overshoot; To ensure the rising edge alignment of VCLK and DQS, Dynamic System there will not be mistake.
Claims (7)
1. a delay phase-locked loop, is characterized in that, comprises delay chain, phase discriminator, feedback circuit, increasing/subtract circuit, renewal speed circuit, logic control circuit and configurable counter;
Input clock signal line connection delay chain and phase discriminator; The output of delay chain connects clock signal line; The output of the input connection delay chain of feedback circuit, the output of feedback circuit connects phase discriminator; The output of phase discriminator connects logic control circuit, and the output of logic control circuit is by increasing/subtracting circuit and renewal speed circuit connection delay chain; The input connected storage control system of configurable counter, the power-down mode sent for reception memorizer control system exits signal, and the output of configurable counter connects logic control circuit.
2. a kind of delay phase-locked loop according to claim 1, it is characterized in that, after power-down mode exits, memory control system sends power-down mode and exits signal to configurable counter, and configurable counter exports the first signal to logic control circuit; Logic control circuit is by renewal speed current controlled delay chain, make it after the renewal speed of continuous several times 1step/ (m*tck) upgrades toward same direction, renewal speed is adjusted to 1step/ (k*tck), wherein k>m.
3. a kind of delay phase-locked loop according to claim 1, is characterized in that, when supply voltage recovers, DLL terminates the renewal in a direction, and when upgrading toward rightabout, renewal speed reverts to 1step/ (m*tck).
4. a kind of delay phase-locked loop according to claim 1, is characterized in that, described several times are N time, N be more than or equal to 2 natural number.
5. the filtering of a delay phase-locked loop more new control method, it is characterized in that, comprise the following steps: after power-down mode exits, memory control system sends power-down mode and exits signal to configurable counter, and configurable counter exports the first signal to logic control circuit; Logic control circuit is by renewal speed current controlled delay chain, make it after the renewal speed of continuous several times 1step/ (m*tck) upgrades toward same direction, renewal speed is adjusted to 1step/ (k*tck), wherein k>m.
6. the filtering more new control method of a kind of delay phase-locked loop according to claim 1, is characterized in that, when supply voltage recovers, DLL terminates the renewal in a direction, and when upgrading toward rightabout, renewal speed reverts to 1step/ (m*tck).
7. the filtering more new control method of a kind of delay phase-locked loop according to claim 1, is characterized in that, described several times are N time, N be more than or equal to 2 natural number.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100127747A1 (en) * | 2008-10-30 | 2010-05-27 | Postech Foundation And Postech Academy Industry Foundation | Digitally controlled oscillator with the wide operation range |
| CN103546151A (en) * | 2013-10-30 | 2014-01-29 | 西安华芯半导体有限公司 | High-speed DLL (Delay-locked loop) |
| CN104124964A (en) * | 2014-08-01 | 2014-10-29 | 西安华芯半导体有限公司 | Delay phase-locked loop and method for improving accuracy of delay phase-locked loop |
| CN104143975A (en) * | 2014-08-01 | 2014-11-12 | 西安华芯半导体有限公司 | DLL delay link and method for reducing duty cycle distortion of DLL clock |
| CN104702270A (en) * | 2015-03-25 | 2015-06-10 | 西安华芯半导体有限公司 | Delay phase-locked ring and update control method thereof |
-
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- 2015-11-17 CN CN201510793693.9A patent/CN105281755B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100127747A1 (en) * | 2008-10-30 | 2010-05-27 | Postech Foundation And Postech Academy Industry Foundation | Digitally controlled oscillator with the wide operation range |
| CN103546151A (en) * | 2013-10-30 | 2014-01-29 | 西安华芯半导体有限公司 | High-speed DLL (Delay-locked loop) |
| CN104124964A (en) * | 2014-08-01 | 2014-10-29 | 西安华芯半导体有限公司 | Delay phase-locked loop and method for improving accuracy of delay phase-locked loop |
| CN104143975A (en) * | 2014-08-01 | 2014-11-12 | 西安华芯半导体有限公司 | DLL delay link and method for reducing duty cycle distortion of DLL clock |
| CN104702270A (en) * | 2015-03-25 | 2015-06-10 | 西安华芯半导体有限公司 | Delay phase-locked ring and update control method thereof |
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