CN105280491A - Silicon chip and preparing method - Google Patents
Silicon chip and preparing method Download PDFInfo
- Publication number
- CN105280491A CN105280491A CN201510335859.2A CN201510335859A CN105280491A CN 105280491 A CN105280491 A CN 105280491A CN 201510335859 A CN201510335859 A CN 201510335859A CN 105280491 A CN105280491 A CN 105280491A
- Authority
- CN
- China
- Prior art keywords
- silicon chip
- nitrogen
- atoms
- argon gas
- atmosphere
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 88
- 239000010703 silicon Substances 0.000 title claims abstract description 88
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 48
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 76
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 72
- 239000013078 crystal Substances 0.000 claims abstract description 42
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 37
- 229910052786 argon Inorganic materials 0.000 claims abstract description 36
- 239000007789 gas Substances 0.000 claims abstract description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000001301 oxygen Substances 0.000 claims abstract description 16
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 16
- 238000010438 heat treatment Methods 0.000 claims description 53
- 230000007547 defect Effects 0.000 claims description 35
- 239000012298 atmosphere Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 10
- 239000003595 mist Substances 0.000 claims description 7
- 238000010792 warming Methods 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 abstract 3
- 238000001816 cooling Methods 0.000 abstract 1
- 238000003754 machining Methods 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 12
- 238000001514 detection method Methods 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 6
- 150000003376 silicon Chemical class 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 229910052571 earthenware Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 101100545275 Mus musculus Znf106 gene Proteins 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 230000008676 import Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004368 synchrotron infrared microspectroscopy Methods 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000012300 argon atmosphere Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
The invention provides a silicon chip and a preparing method. The method comprises the steps of: adopting a Czochralski method (Cz method) to prepare a crystal bar whose oxygen concentration is 5*10<17> atoms/cm3-1*10<18> atoms/cm3 and nitrogen concentration is 5*10<14> atoms/cm3-2*10<16> atoms/cm3; and after machining the crystal bar into the silicon chip, exposing the silicon chip respectively to nitrogen in the temperature rising range of 700 DEG C-1000 DEG C, to mixed gas of nitrogen and argon in the temperature rising range of 1000 DEG C-1100 DEG C and to argon in the temperature rising range of 1100 DEG C-1150 DEG C, carrying out constant temperature heat processing on the silicon chip in argon, and then cooling the silicon chip to below 700 DEG C.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of single crystals silicon chip for the manufacture of electronic devices and components such as large scale integrated circuits and manufacture method.
Background technology
The manufacture of the semiconductor components and devices such as very lagre scale integrated circuit (VLSIC) is widely used in the monocrystalline silicon piece that Czochralski method (hereinafter referred to as Cz method) produced monocrystalline silicon crystal bar manufactures through cutting heat treatment or mirror finish etc.Improving constantly in recent years along with components and parts integrated level, also improves constantly the quality requirements of silicon chip, and the silicon chip especially for components and parts can not analyse the existence of the crystal defect such as thing, lattice defects by aerobic in the scope on its surface and following several microns of surface.Therefore just need to form flawless exposed region at monocrystalline silicon sheet surface, and the blemish of silicon chip adopts heat treatment method abatement.
Particularly adulterate the monocrystalline silicon crystal bar of nitrogen, has very great help to reducing lattice defects during wafer heat.This makes the annealing silicon wafer of N doping monocrystalline silicon crystal bar be widely used.Crystal bar pulling process doping nitrogen, can suppress cavity blemish maybe pore size can be diminished, and carries out the silicon chip manufacture method that high-temperature heat treatment effectively can reduce lattice defects be widely used with argon atmosphere.But still there are problems at high-temperature heat treatment process, as easily there is the problems such as sliding change, the nondefective zone degree of depth is not enough in heat treatment process.
When silicon chip is at AN, a small amount of nitrogen can penetrate into silicon chip surface, thus suppresses the growth of defect.Heat treatment more than 1100 DEG C is still in nitrogen atmosphere, and silicon chip surface can form very thick nitride film, silicon chip surface is formed uneven, thus the method is never applied in wafer heat.
For above problem, such as patent CN200910226480.2 once disclosed a kind of annealed wafer and prepared the method for annealed wafer, and at the temperature of 650 to 800 DEG C, heat nitrogen concentration is 5 × 10
12/ cm
3to 1 × 10
16/ cm
3, concentration of carbon is 1 × 10
15/ cm
3to 5 × 10
16/ cm
3, oxygen concentration is 6 × 10
17/ cm
3to 11 × 10
17/ cm
3silicon substrate 4 hours or the longer time, and at the temperature of 1100 to 1250 DEG C to heating substrate carry out argon annealed.
By the method disclosed in patent CN200910226480.2, although lattice defects, the suppression generation of slippage or the prolongation of slippage can be reduced to a certain extent, cannot effectively suppress and prevent warpage and the sliding problem become.
The present invention is directed to above-mentioned Problems existing, a kind of high-quality silicon chip and manufacture method are provided.
Summary of the invention
A kind of silicon chip and the manufacture method that reduce slippage and warpage is the invention provides for reaching above-mentioned purpose.
The technical solution adopted in the present invention is: the oxygen concentration obtained with Cz farad monocrystalline silicon crystal bar is at 5x10
17atoms/cm
3~ 1x10
18atoms/cm
3within, nitrogen concentration is at 5x10
14atoms/cm
3~ 2x10
16atoms/cm
3within silicon rod, after being processed into silicon chip, in temperature-rise period, in the calefactive interzone of 700 DEG C ~ 1000 DEG C, make silicon chip be in nitrogen atmosphere, in 1000 DEG C ~ 1100 DEG C calefactive interzones, make silicon chip be in the mixed atmosphere of nitrogen and argon gas, in the calefactive interzone of 1100 DEG C ~ 1150 DEG C, silicon chip is in argon gas atmosphere.Afterwards in argon gas atmosphere, after 1150 DEG C of constant temp. heating process, be cooled to less than the 700 DEG C silicon chip manufacture methods obtained.
Further, when oxygen concentration in described crystal bar is 5 × 10
17atoms/cm
3~ 7 × 10
17atoms/cm
3time, the heat treatment time in argon gas atmosphere is 2 ~ 10 hours.
Further, during described heat treatment 700 DEG C to 1000 DEG C interval programming rates be 5 DEG C/min ~ 15 DEG C/min, 1000 DEG C to 1100 DEG C interval programming rates be 0.5 DEG C/min ~ 5 DEG C/min, the programming rates of 1100 DEG C to 1150 DEG C be 0.5 DEG C/min ~ 2 DEG C/min; After constant temp. heating process, the strategy identical with temperature-rise period is adopted to lower the temperature.
Further, when described 1000 DEG C to 1100 DEG C interval heat treatment, the argon gas that will be mixed with 0.1% ~ 2.0% nitrogen imports in stove, makes furnace atmosphere be the mist of nitrogen and argon gas.
Further, the invention provides a kind of silicon chip prepared by said method.
The present invention adopts 7 unique segmentation heat treatment modes, unique atmosphere treatment process of pure nitrogen gas, nitrogen and argon gas mist, pure argon is adopted successively in conjunction with Different periods, can the generation of silicon chip slippage and warpage in heat treatment process be suppressed in extremely low level simultaneously, and the zero defect layer depth after silicon chip process is not less than 7 μm, warpage increment is not more than 4 μm, and sliding change.
Embodiment
The crystal pulling furnace that this monocrystalline silicon crystal bar uses is the crystal pulling furnace of monocrystalline silicon or general Cz method crystal pulling furnace.About nitrogen in monocrystalline silicon crystal bar doped with add alpha-silicon nitride powders method, have the silicon chip of nitride film melting method, add the methods such as ammonia in addition in atmosphere as raw material.
In monocrystalline silicon crystal bar, oxygen concentration will control 5 × 10
17atoms/cm
3~ 1 × 10
18atoms/cm
3if control 5 × 10 in scope
17atoms/cm
3~ 7 × 10
17atoms/cm
3scope is best.If oxygen concentration is lower than 5 × 10 in crystal bar
17atoms/cm
3time, when argon thermal treatment can there is sliding change in silicon chip.If oxygen concentration is higher than 1x10 in crystal bar
18atoms/cm
3time above, oxygen precipitation can arrive near surface, just cannot form the zero defect layer of surface and near surface like this.If want to obtain darker zero defect layer, that just needs oxygen concentration will control 7 × 10
17atoms/cm
3below.
In monocrystalline silicon crystal bar, nitrogen concentration need control 5 × 10
14atoms/cm
3~ 2 × 10
16atoms/cm
3.When nitrogen doped concentration is less than 5 × 10
14atoms/cm
3time, crystal pulling time can cause the appearance of void-type defect, thus cannot suppress the generation of lattice defects thus at remained on surface lattice defects after making argon thermal treatment.And when nitrogen gas concn is greater than 2 × 10
16atoms/cm
3time above, nitrogen can cause oxygen separate out speedup, also can at remained on surface lattice defects.
The monocrystalline silicon crystal bar of above-mentioned Cz method manufacture, make minute surface silicon chip by common silicon chip manufacturing procedure after, heat-treat with the heat-treatment furnace of semiconductor manufacturing.Need before heat treatment to clean minute surface silicon chip, usually use ammoniacal liquor, hydrogen peroxide cleans, the thickness of the silicon chip surface oxide-film after cleaning and nitride film etc. can not more than more than 1nm.
In heat treatment process, in the nitrogen atmosphere in 700 DEG C ~ 1000 DEG C calefactive interzones, silicon chip being in, in 1000 DEG C ~ 1100 DEG C calefactive interzones, make silicon chip be in the mixed atmosphere of nitrogen and argon gas, in 1100 DEG C ~ 1150 DEG C calefactive interzones, make silicon chip be in the heat treatment carried out in argon gas atmosphere; Afterwards in argon gas atmosphere, after 1150 DEG C of constant temp. heating process, be cooled to less than the 700 DEG C silicon chip manufacture methods obtained.The nitrogen injection when temperature is at 700 DEG C ~ less than 1000 DEG C, a small amount of nitrogen can penetrate into silicon chip surface, thus suppresses the growth of defect.Although argon annealed afterwards can cut down defect, if the heat treatment more than 1100 DEG C is still in nitrogen atmosphere, silicon chip surface can form very thick nitride film, silicon chip surface is formed uneven.So between 1000 DEG C ~ 1100 DEG C time gradually nitrogen atmosphere to be switched to argon gas atmosphere.In nitrogen atmosphere, argon gas is imported during this heat treatment, also the time is needed to displace the nitrogen of the inside even if import pure argon gas, some place there will be the extreme variation of nitrogen atmosphere in the meantime, this change can cause the uneven of silicon chip surface, so the argon gas of the nitrogen being mixed with less than more than 0.1% 2% will be imported, the uneven of silicon chip surface would not be caused like this.
[embodiment 1]
Adopt Cz farad diameter as 8 inches, resistivity is as the p Xing Unit crystal silicon of 10 Ω cm.Silicon nitride element powder is added in the polycrystalline silicon raw material of pulling monocrystal silicon rod.After crystallization, the nitrogen concentration in gained silicon rod is 7x10
14atoms/cm
3, oxygen concentration is 6x10
17atoms/cm
3.
Be processed into minute surface silicon chip with this silicon rod, heat-treat with perpendicular type heat-treatment furnace.With the flow velocity nitrogen injection of 10L/min in stove, form nitrogen atmosphere; Put into silicon chip when reaching 700 DEG C and be warmed up to 1000 DEG C with the speed of 10 DEG C/min, inject the argon gas mist containing 1% nitrogen when arrival 1000 DEG C with the speed of 10L/min.1100 DEG C are warming up to the speed of 3 DEG C/min after injecting this mist.Inject argon gas completely afterwards, be warming up to 1145 DEG C and constant temperature 3 hours with the speed of 1 DEG C/min.Be cooled to 1100 DEG C with the speed of 1 DEG C/min in argon gas atmosphere, be cooled to 1000 DEG C with the speed of 5 DEG C/min afterwards, after being cooled to 700 DEG C with 10 DEG C/minute, silicon chip is taken out in stove.
In this embodiment, rise to silicon chip deformation quantity the process of 1000 DEG C from 700 DEG C less, can production cost be reduced with heating rate intensification faster; Reduce heating rate at the temperature-rise periods of 1000 DEG C to 1100 DEG C, reduce silicon chip inner radial and axial temperature gradient, alleviate or suppress to cause larger swell increment because of temperature gradient; In the process of 1100 DEG C to 1145 DEG C, reduce heating rate further, suppress the warpage caused because of expansion, anti-on-slip simultaneously becomes.The SIRM of this silicon chip Semilab She System is carried out silicon slice surface defects detection, testing result be below surface, there is no defect till 7 μm, warpage increment is not more than 4 μm and sliding change does not occur.
[comparative example 1]
Make silicon chip with the crystal bar that embodiment 1 is same, then carry out same heat treatment with perpendicular type heat-treatment furnace.But whole heat treatment process all uses argon gas atmosphere.
The SIRM of this silicon chip Semilab She System is carried out silicon slice surface defects detection, testing result only has 2 μm from the zero defect layer below surface, this degree of depth is concerning the semiconductor components and devices that will be used for making ditch columnar structure, and the degree of depth of zero defect layer is inadequate.
[comparative example 2]
Make silicon chip with the crystal bar that embodiment 1 is same, then carry out same heat treatment with perpendicular type heat-treatment furnace.But whole heat treatment process all uses nitrogen atmosphere.
After heat treatment, silicon chip extracting, silicon chip surface is uneven, this silicon chip cannot be used for making semiconductor components and devices.
[comparative example 3]
Make silicon chip with the crystal bar that embodiment 1 is same, then carry out same heat treatment with perpendicular type heat-treatment furnace.But after injecting argon gas completely, be warming up to 1145 DEG C and constant temperature 3 hours with the speed of 3 DEG C/min
Carry out surface defects detection after heat treatment, zero defect layer depth can reach 7 μm and sliding to become but warpage increment is greater than 4 μm does not occur.
[comparative example 4]
Make silicon chip with the crystal bar that embodiment 1 is same, then carry out same heat treatment with perpendicular type heat-treatment furnace.But after injecting the argon gas mist containing 1% nitrogen, be warming up to 1100 DEG C with the speed of 10 DEG C/min.
After heat treatment, silicon chip extracting, silicon chip surface is uneven, warpage increment is greater than 10 μm.This silicon chip cannot be used for making semiconductor components and devices.
[embodiment 2]
Unit crystal silicon is made equally in the same manner as in Example 1 by Cz vertical pulling legal system.Owing to changing the earthenware Crucible speed of rotation in the addition of nitrogen and crystal pulling, making the nitrogen concentration in crystal bar become 1x10
16atoms/cm
3, oxygen concentration becomes 9x10
17atoms/cm
3.
Heat-treat after making silicon chip with this silicon rod, with the heat treatment method of embodiment 1.Carry out surface defects detection after heat treatment, zero defect layer depth can reach 4 μm and sliding change does not occur.With embodiment 1 to compare zero defect layer depth be more shallow, but enough as making this zero defect layer depth of ditch type structure semiconductor components and devices.
[embodiment 3]
In the same manner as in Example 1 equally with Cz vertical pulling farad Unit crystal silicon.Owing to changing the earthenware Crucible speed of rotation in the addition of nitrogen and crystal pulling process, the nitrogen concentration in crystallization crystal bar is made to become 5x10
14atoms/cm
3, oxygen concentration becomes 5x10
17atoms/cm
3.
The method recorded after this crystal bar is made silicon chip, by embodiment 1 is heat-treated.Carry out surface defects detection after heat treatment, zero defect layer depth can reach 9 μm, warpage increment is not more than 4 μm and sliding change does not occur.
[comparative example 5]
Use Cz farad Unit crystal silicon in the same manner as in Example 1 equally.Owing to changing earthenware Crucible winding number in the addition of nitrogen and crystal pulling process, making the nitrogen concentration in crystallization crystal bar become 5x10
14atoms/cm
3, oxygen concentration becomes 4.5x10
17atoms/cm
3.
The method recorded after this crystal bar is made silicon chip, by embodiment 1 is heat-treated.But although after heat treatment, carry out that surface defects detection zero defect layer depth can reach 9 μm, warpage increment is not more than 4 μm and there occurs sliding change.
[embodiment 4]
Same heat treatment is carried out equally in the same manner as in Example 1 with the perpendicular type heat-treatment furnace of Cz farad Unit crystal silicon, then use.But after temperature is increased to 1145 DEG C, in argon gas atmosphere, carry out constant temperature heat treatment in 10 hours.
Carry out surface defects detection after heat treatment, zero defect layer depth can reach 11 μm, warpage increment is not more than 4 μm and sliding change does not occur.
[comparative example 6]
Same heat treatment is carried out equally in the same manner as in Example 1 with the perpendicular type heat-treatment furnace of Cz farad Unit crystal silicon, then use.But after temperature is increased to 1145 DEG C, the cycle annealing processing time is 15 hours.
Carry out surface defects detection after heat treatment, zero defect layer depth can reach 12 μm and sliding to become but warpage increment is greater than 4 μm does not occur.
Claims (7)
1. a silicon chip manufacture method, is characterized in that, by Czochralski farad oxygen concentration at 5x10
17atoms/cm
3~ 1x10
18atoms/cm
3within, nitrogen concentration is at 5x10
14atoms/cm
3~ 2x10
16atoms/cm
3within single crystals crystal bar; After being processed into silicon chip with this crystal bar, be in be in nitrogen atmosphere, in 1000 DEG C ~ 1100 DEG C calefactive interzones to be in argon gas atmosphere in nitrogen and argon gas mixed atmosphere, in 1100 DEG C ~ 1150 DEG C calefactive interzones at 700 DEG C ~ 1000 DEG C calefactive interzones and heat-treat, and in argon gas atmosphere, after 1150 DEG C of constant temp. heating process, be cooled to 700 DEG C below obtain silicon chip.
2. silicon chip manufacture method as claimed in claim 1, is characterized in that the oxygen concentration of described silicon chip is 5x10
17atoms/cm
3~ 7x10
17atoms/cm
3.
3. silicon chip manufacture method as claimed in claim 1, is characterized in that the constant temp. heating process carrying out 2 ~ 10 hours in argon gas atmosphere.
4. silicon chip manufacture method as claimed in claim 1, it is characterized in that when wafer heat, be warming up to 1000 DEG C with the heating rate of 5 DEG C/min ~ 15 DEG C/min from 700 DEG C, be warming up to 1100 DEG C with the heating rate of 0.5 DEG C/min ~ 5 DEG C/min from 1000 DEG C, be warming up to 1150 DEG C with 0.5 DEG C/min ~ 2 DEG C/minute from 1100 DEG C.
5. the silicon chip manufacture method according to any one of Claims 1-4, when it is characterized in that silicon chip is heat-treated, when heat-treating in 1000 DEG C ~ 1100 DEG C calefactive interzones, the mist of nitrogen and argon gas is imported in stove, make furnace atmosphere be the mixed atmosphere of nitrogen and argon gas.
6. silicon chip manufacture method as claimed in claim 5, is characterized in that in the mist of nitrogen in described importing stove and argon gas, the mass fraction of its nitrogen is 0.1% ~ 2.0%.
7. the silicon chip after the method process according to any one of claim 1 ~ 6, is characterized in that, the zero defect layer depth of silicon chip is not less than 7 μm, amount of warpage is not more than 4 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510335859.2A CN105280491A (en) | 2015-06-17 | 2015-06-17 | Silicon chip and preparing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510335859.2A CN105280491A (en) | 2015-06-17 | 2015-06-17 | Silicon chip and preparing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105280491A true CN105280491A (en) | 2016-01-27 |
Family
ID=55149306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510335859.2A Pending CN105280491A (en) | 2015-06-17 | 2015-06-17 | Silicon chip and preparing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105280491A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115398042A (en) * | 2020-04-17 | 2022-11-25 | 信越半导体株式会社 | Single crystal silicon substrate for vapor phase growth, vapor phase growth substrate, and method for producing these substrates |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1545725A (en) * | 2001-08-23 | 2004-11-10 | 信越半导体株式会社 | Epitaxial wafer and a method for producing it |
| CN1547764A (en) * | 2001-08-30 | 2004-11-17 | ��Խ�뵼����ʽ���� | Production method for anneal wafer and anneal wafer |
| US20090117719A1 (en) * | 2006-01-31 | 2009-05-07 | Sumco Corporation | High frequency diode and method for producing same |
| CN101675507A (en) * | 2007-05-02 | 2010-03-17 | 硅电子股份公司 | Silicon wafer and method for manufacturing the same |
| CN101748491A (en) * | 2008-12-18 | 2010-06-23 | 硅电子股份公司 | Annealed wafer and method for producing annealed wafer |
| CN103144024A (en) * | 2011-12-06 | 2013-06-12 | 有研半导体材料股份有限公司 | Process for manufacturing 300mm silicon polished wafer by using high-temperature heat treatment |
-
2015
- 2015-06-17 CN CN201510335859.2A patent/CN105280491A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1545725A (en) * | 2001-08-23 | 2004-11-10 | 信越半导体株式会社 | Epitaxial wafer and a method for producing it |
| CN1547764A (en) * | 2001-08-30 | 2004-11-17 | ��Խ�뵼����ʽ���� | Production method for anneal wafer and anneal wafer |
| US20090117719A1 (en) * | 2006-01-31 | 2009-05-07 | Sumco Corporation | High frequency diode and method for producing same |
| CN101675507A (en) * | 2007-05-02 | 2010-03-17 | 硅电子股份公司 | Silicon wafer and method for manufacturing the same |
| CN101748491A (en) * | 2008-12-18 | 2010-06-23 | 硅电子股份公司 | Annealed wafer and method for producing annealed wafer |
| CN103144024A (en) * | 2011-12-06 | 2013-06-12 | 有研半导体材料股份有限公司 | Process for manufacturing 300mm silicon polished wafer by using high-temperature heat treatment |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115398042A (en) * | 2020-04-17 | 2022-11-25 | 信越半导体株式会社 | Single crystal silicon substrate for vapor phase growth, vapor phase growth substrate, and method for producing these substrates |
| CN115398042B (en) * | 2020-04-17 | 2024-05-03 | 信越半导体株式会社 | Single crystal silicon substrate for vapor phase growth, vapor phase growth substrate, and method for producing these substrates |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100829767B1 (en) | High resistance silicon wafer and its manufacturing method | |
| CN102396055B (en) | Anneal wafer, method for manufacturing anneal wafer, and method for manufacturing device | |
| JP4794137B2 (en) | Heat treatment method for silicon semiconductor substrate | |
| US8545622B2 (en) | Annealed wafer and manufacturing method of annealed wafer | |
| CN108368638B (en) | Semiconductor wafer made of monocrystalline silicon and method for producing the same | |
| JP2010532584A (en) | Suppression of oxygen precipitates in highly doped single crystal silicon substrates. | |
| CN101160420A (en) | Method for manufacturing silicon single crystal, and silicon wafer | |
| US10211066B2 (en) | Silicon epitaxial wafer and method of producing same | |
| CN114318500A (en) | Crystal pulling furnace and method for pulling single crystal silicon rod and single crystal silicon rod | |
| CN101155950B (en) | Silicon single crystal growing method, silicon wafer and soi substrate using such silicon wafer | |
| US8211228B2 (en) | Method for producing single crystal and a method for producing annealed wafer | |
| JP2004503086A (en) | Method and apparatus for manufacturing a silicon wafer having a denuded area | |
| CN105297140B (en) | Silicon wafer and annealing method | |
| KR20100061360A (en) | Silicon single crystal and method for growing thereof, and silicon wafer and method for manufacturing thereof | |
| TWI855103B (en) | Carbon-doped silicon single crystal wafer and method for manufacturing the same | |
| CN105280491A (en) | Silicon chip and preparing method | |
| JP5262021B2 (en) | Silicon wafer and manufacturing method thereof | |
| WO2017140507A1 (en) | Fz silicon and method to prepare fz silicon | |
| JP2004503085A (en) | Method and apparatus for manufacturing a silicon wafer having a denuded area | |
| CN105316767A (en) | Silicon wafer for very large scale integrated circuit and manufacturing method and application thereof | |
| JP2007223831A (en) | Method and apparatus for manufacturing silicon wafer and silicon single crystal | |
| TWI628316B (en) | Methods for forming monocrystalline silicon ingot and wafer | |
| JP2010114211A (en) | Method of manufacturing epitaxial silicon wafer | |
| TW201741507A (en) | Process for producing a semiconductor wafer of single-crystal silicon, apparatus for producing a semiconductor wafer of single-crystal silicon and semiconductor wafer of single-crystal silicon | |
| JP5333620B2 (en) | Epitaxial silicon wafer manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160127 |