CN105279321A - SIP (System In Package) module design method based on board level verification and test system - Google Patents

Abstract

A SIP module design method based on a board-level verification test system. Firstly, select the device to be integrated and design the principle verification PCB board, write the driver program, complete the principle verification, then perform structural design and wiring design, and finally perform functional verification and complete the chip back Testing and functional testing, this method realizes the principle verification, functional verification and functional testing of the SIP module based on the PCB board, which improves the integrity of the SIP module design, avoids the problem of incomplete design work, and conducts inspections on the PCB board during the design process. Reuse is reduced, design workload and difficulty are reduced, efficiency is improved, and the requirements of SIP module design are met to the greatest extent.

Description

A Design Method of SIP Module Based on Board Level Verification Test System

technical field

The invention relates to a SIP module design method, in particular to a SIP module design method based on a board-level verification test system, belonging to the field of integrated circuit design.

Background technique

System-in-Package (SIP) has developed rapidly in recent years. It is an important way to realize the miniaturization, light weight and multi-function of electronic products, and has become an important advanced packaging and system integration technology. The SIP module integrates different types of circuits (mostly bare-die, but also chips and discrete components) into the same package, and realizes some passive device functions, interconnection and Mechanical installation, and finally complete the functions of the whole or part of the system. The integrated circuits can be of different functions, different processes, and different states, which greatly reduces the difficulty and requirements of system integration, improves the feasibility of engineering realization, and realizes heterogeneous integrate.

Because the SIP design technology originally originated from the packaging design, the current research on SIP modules is mostly focused on the packaging process, such as interconnection implementation methods and substrate materials, while the system modular design based on the use of SIP technology is still in a single requirement and a single implementation stage, there is no engineering research, nor a complete design process.

Contents of the invention

The technical problem that the present invention solves is: aiming at the deficiencies in the prior art, a kind of SIP module design method based on board-level verification test system is proposed, the method realizes the principle verification, function verification and function test of SIP module based on PCB board, improves It improves the integrity of the SIP module design, avoids the problem of incomplete design work, and reuses the PCB board in the design process, reduces the design workload and difficulty, improves efficiency, and satisfies the SIP module design to the greatest extent. demand.

Technical solution of the present invention is: a kind of SIP module design method based on board-level verification test system, comprises the following steps:

(1) According to preset requirements, select the devices to be integrated and determine the connection relationship between the devices to be integrated, the devices to be integrated include integrated circuit bare cores, MEMS, optoelectronic devices and discrete devices, the integrated circuit bare cores Including: processor, memory, converter and field programmable gate array;

(2) Design principle verification PCB board;

(3) write driver program, described driver program comprises address decoding program, boot program and header file;

(4) Use the PCB board in step (2) and the driver in step (3) to verify the principle of the device to be integrated and the connection relationship between the devices to be integrated selected in step (1). If the principle verification is passed, Then enter step (6), if the principle verification fails, then enter step (5);

(5) If the principle verification fails due to hardware reasons, return to step (1) to adjust the devices to be integrated or the connection relationship between the devices to be integrated in step (1); if the principle verification fails to pass due to software reasons, Then return to step (3), rewrite the driver;

(6) Carry out the structural design and wiring design of the SIP module;

(7) Carry out functional verification to the SIP module designed in step (6), if the functional verification is passed, then enter step (8), otherwise, return to step (1) and redesign;

(8) The SIP module passed through functional verification in the production step (7), and the produced SIP module is returned to the chip test, if the chip-back test is passed, then the design process of the SIP module is completed, if the chip-back test fails, then return In step (1), the design of the SIP module is carried out again, and the chip-back test includes a function test and a parameter test of the SIP module.

In the step (2), the principle verification PCB board is specifically: the principle verification PCB board is divided into a motherboard and a daughter board, and the motherboard and the daughter board are connected by a multi-pin connector; Integrate the device, realize the connection relationship of the device to be integrated, and place the supporting connector to realize the physical connection with the motherboard; Level conversion circuit, power management circuit, clock input circuit, interface drive circuit, selector and FPGA configuration circuit.

The address decoding program in the step (3) corresponds to the initial address, address length and data width of each device to be integrated according to the connection relationship between each device to be integrated in the step (1), and then considers the big and small ends to write .

The structural design method of the SIP module is 2D, 2.5D or 3D.

In described step (7), carry out function verification to the SIP module designed in step (6), specifically realize by function verification system, described function verification system comprises function verification motherboard and function verification sub-board, function verification motherboard and The functional verification sub-boards are connected by multi-pin connectors; the functional verification motherboard multiplexes the mother board of the PCB board, and the functional verification sub-board includes a socket for placing the SIP module and a matching connector of the principle verification PCB board sub-board. plugin.

Described SIP module function test is specifically realized by function test system, and described function test system comprises function test motherboard and function test daughter board, utilizes multi-pin connector to be connected between function test mother board and function test daughter board; Described function The sub-board of the test sub-board multiplexing function verification PCB board, the functional test motherboard includes components that support the work of the functional test sub-board, and the components that support the work of the functional test sub-board include: power supply and level conversion circuits, power management circuits, Clock input circuit, interface drive circuit, selector and FPGA configuration circuit.

The multiplexing principle of the connection relationship between the devices to be integrated in the wiring design verifies the connection relationship between the devices to be integrated in the sub-board of the PCB.

The beneficial effect of the present invention compared with prior art is:

(1) The present invention proposes a set of complete SIP module design flow, fills up the blank of current SIP module design flow, avoids the problem of flow confusion in the current SIP module design;

(2) In the design process, the present invention not only considers the design issues of the SIP module entity itself, but also takes into account issues such as principle verification, functional verification, and functional testing, thereby improving the integrity of the design and avoiding The problem of incomplete design work. Design errors due to missing steps and processes are reduced.

Description of drawings

Fig. 1 is the flow chart of the present invention.

Fig. 2 is a schematic diagram of the connection relationship among the devices to be integrated in the embodiment of the present invention.

detailed description

The method of the present invention is based on the designer, and the production links are not within the scope of the invention. The design method adopting the SIP module of the present invention includes three stages: the stage of principle verification, the stage of module entity design and production, and the stage of chip verification and test. The three stages are carried out sequentially, the input of the next stage comes from the output of the previous stage, and the three stages constitute a relatively complete SIP module design process. Designs and results from the three-stage process can be reused to simplify design. As shown in Figure 1 is the flow chart of the present invention, from shown in Figure 1, a kind of SIP module design method based on board-level verification test system that the present invention proposes is characterized in that comprising the following steps:

(1) According to preset requirements, select the devices to be integrated and determine the connection relationship between the devices to be integrated, the devices to be integrated include integrated circuit bare cores, MEMS, optoelectronic devices and discrete devices, the integrated circuit bare cores Including: processor, memory, converter and field programmable gate array;

(2) Design the principle verification PCB board; specifically: the principle verification PCB board is divided into a motherboard and a sub-board, and the motherboard and the sub-board are connected by a multi-pin connector; wherein only selected devices to be integrated are placed on the sub-board, And the connection relationship of the devices to be integrated is realized, and the supporting connectors are placed to realize the physical connection with the motherboard; the motherboard contains components that support the work of the daughter board, and the components that support the work of the daughter board include: power supply and level conversion circuits, power management circuits, clock input circuits, interface drive circuits, selectors and FPGA configuration circuits.

(3) write driver program, described driver program comprises address decoding program, boot program and header file; Described address decoding program corresponds to each device to be integrated according to the connection relationship between each device to be integrated in step (1) start address, address length and data width, and then write with big and small endian in mind.

(4) Use the PCB board in step (2) and the driver in step (3) to verify the principle of the device to be integrated and the connection relationship between the devices to be integrated selected in step (1). If the principle verification is passed, Then enter step (6), if the principle verification fails, then enter step (5);

(5) If the principle verification fails due to hardware reasons, return to step (1) to adjust the devices to be integrated or the connection relationship between the devices to be integrated in step (1); if the principle verification fails to pass due to software reasons, Then return to step (3), rewrite the driver;

(6) carry out structural design and wiring design of SIP module; The structural design method of described SIP module is 2D, 2.5D or 3D;

(7) Carry out functional verification to the SIP module designed in step (6), if the functional verification is passed, then enter step (8), otherwise, return to step (1) and re-design; said functional verification specifically passes the functional verification System implementation, the function verification system includes a function verification motherboard and a function verification sub-board, and the function verification motherboard and the function verification daughter board are connected by a multi-pin connector; the function verification motherboard multiplexing principle verifies the PCB board The mother board and the functional verification daughter board include a socket for placing the SIP module and a matching connector for the principle verification PCB board daughter board.

(8) The SIP module passed through functional verification in the production step (7), and the produced SIP module is returned to the chip test, if the chip-back test is passed, then the design process of the SIP module is completed, if the chip-back test fails, then return In step (1), the design of the SIP module is carried out again, and the chip-back test includes a function test and a parameter test of the SIP module. Described SIP module function test is specifically realized by function test system, and described function test system comprises function test motherboard and function test daughter board, utilizes multi-pin connector to be connected between function test mother board and function test daughter board; Described function The sub-board of the test sub-board multiplexing function verification PCB board, the functional test motherboard includes components that support the work of the functional test sub-board, and the components that support the work of the functional test sub-board include: power supply and level conversion circuits, power management circuits, Clock input circuit, interface drive circuit, selector and FPGA configuration circuit.

Example 1

Take the design process of a certain type of SIP module (hereinafter referred to as this module) as an example:

(1) In the principle verification stage, after receiving user requirements or design goals as project start conditions, the first step is to conduct requirement analysis and system software and hardware division;

The second step is carried out separately and in parallel according to the software and hardware process. The hardware sequence is used to select components and determine the preliminary test plan, board-level design and production, synchronize the software to write the task book, and then write the driver in parallel to plan the development environment.

This module selects a SoC, an FPGA, a SRAM, a SDRAM and a FLASH, a total of 5 integrated circuit chips as the target components for SIP integration. In this module interconnection design, SoC is used as the main control chip, and SRAM, SDRAM, FLASH and FPGA as an extended peripheral are arranged in its accessible address space according to the design of the processor in SoC. Figure 2 shows the interconnection of each chip of this module.

When designing the principle verification system for hardware, in order to reduce the planar area of the verification system, reduce the length of the interconnection line and reuse it in the entire design process, the principle verification system is divided into two PCB boards for design, namely the mother board (hereinafter referred to as principle A Board) and sub-board (hereinafter referred to as the principle B board), the two boards are connected by a multi-pin connector and work as a system. Among them, only 5 chips to be integrated are placed on the principle B board, and the connection relationship is realized. In addition, matching connectors are placed to realize the physical connection with the principle A board. The design relationship of the principle B board can be referred to in Figure 2. ;Principle A board includes all components and designs that support the work of principle B board, such as power supply and level conversion, multi-power supply management, multi-clock input, drive circuits for various interfaces, selectors for various configuration selections, and FPGA configuration circuit etc. The design of this module enables the FPGA to be configured off-chip or on-chip. The off-chip configuration is the same as the general FPGA—it is completed by configuring the PROM and the configuration circuit designed on the board. The volatile memory can store the configuration data, and the SoC of the main control is used to access and inject data into the FPGA to complete the configuration.

Software design At this stage, the driver program is mainly written. According to the connection mode of SRAM, SDRAM, FLASH and FPGA set by the hardware in this module, the starting address, address length and data width of each space are correspondingly determined, and then the address decoding design is carried out considering the big and small ends. In addition, writing a boot program and writing an exemplary header file can provide subsequent reuse. For the design of FPGA internal and external dual configuration, according to the FPGA configuration data flow file format, the programming of data packet generation, storage, reading, injection and completion of judgment is performed, and subsequent multiplexing can be provided at the same time.

The third step is to carry out joint debugging of software and hardware on the verification system. If there is a problem in the joint debugging, it is necessary to distinguish software or hardware problems. For hardware problems, it is necessary to return to the hardware process to select components and determine the steps of the preliminary test plan or board level according to the specific situation. The design and production steps are readjusted, and software problems need to be readjusted in the driver writing step in the software process; the preliminary verification is finally completed, and the output of this stage is to confirm the system composition and functions, form the preliminary version of the driver, and determine the composition of the development environment modules, etc.

(2) After completing the relevant work of principle verification, it will enter the stage of module entity design and production.

The first step is to confirm the components to be integrated and the packaging form based on the conclusion of the principle verification. Most of the components to be integrated exist in the form of bare cores (in the state of a whole wafer or in the state of being diced and divided into pieces), but because the integration type of SIP modules is relatively Freedom, some chips or discrete components that are small in size and difficult to obtain bare cores can be integrated in the form of packaging. After the principle verification of this module, the 5 selected integrated circuit chips can meet the functional requirements, and all of them exist in the form of wafers, all of which are bonded and assembled. The same bonding material and bonding process and 0.20mm gold wire bond can be selected. Bonding, thermosonic bonding process. The packaging form of the design module is BGA416, which is packaged by high-density multi-layer organic substrate and plastic packaging.

The second step is to carry out structural design and wiring design, and then form a handover document according to the requirements of the manufacturer. In structural design, if the bare core has a single-sided or double-sided bonding design (the upper and lower layers of chips are bonded on different sides after stacking to avoid the influence of wire bonding), the shape is the same, and the size difference is small (so that the upper layer of chips can be used after stacking) Bonding wires whose length does not exceed a typical value are bonded to the substrate), in order to further miniaturize, a stacked structure design can be considered. If the above requirements are not met, but the final module has strict signal trace length requirements, or the module size requirements are small, then it is necessary to consider the relatively high-cost silicon transfer substrate designed into a 2.5D or 3D structure, which can be stacked The bonding and transfer design of the chip on the chip. Considering that all bare cores of this module are bonded on four sides, the larger SoC and FPGA chips are multi-layer bonded, which is not suitable for stacking assembly; the module size does not require extremely small, and the number of external pins Many, extremely small form factors are not possible. Therefore, the structural design adopts a relatively common 2D method. According to the length of the interconnection line, the interconnection relationship, and the shape distribution determined by the final shape, a structure with large chips diagonally inserted, small chips inserted, and high-speed chips close to the main control chip can be realized.

In the wiring design, the principle design is carried out first. At this time, design reuse is adopted to design the principle B board in the principle verification stage. After replacing the original chip model with the bare core model, the connection relationship of the five chips is copied to the principle B board. In addition, the bare core pins that do not need to be drawn out and have no connection relationship are pulled up/down or left empty according to the input or output form. Subsequently, lay-out design is carried out according to the process rules of the substrate processing party.

The third step is to perform functional verification through the functional verification system to judge whether the designed SIP module meets the preset functions,

(3) After producing the return film and completing the testing, verification, software, and document related work described in the previous stage, it will enter the return film verification test stage.

Firstly, functional testing is carried out, and vector debugging and parameter evaluation are carried out at the same time. Any testing, verification, and evaluation process that does not meet the design requirements needs to be analyzed and located. Go back to re-do or avoid, adjust, and form a preliminary design report after all requirements are met. The function test is carried out by using the function test system; the vector debugging and parameter evaluation are carried out by using the parameter test vector design.

The design of the functional test system and the verification system is carried out by supporting relevant software of the PCB board level system. The design of the verification system reuses the design of the principle verification system, which also adopts the sub-motherboard method. Principle A board does not need to be modified and can be reused directly. The sub-board replaces the design of the principle B board (hereinafter referred to as the verification board B), replaces the original 5 chips with the applicable socket of this module, and also places the same connector as the principle B board to match the A board. Complete the verification of the design of the B-board. When the specific verification is carried out, put the module in the socket, and connect the verification board B and the principle board A.

Considering the efficiency of functional testing in the future, the functional testing system minimizes manual intervention and uses the internal resources of modules for mutual testing as much as possible. The functional test system makes full use of the programmable characteristics of the FPGA in the programmable processor, and connects most of the pins to be tested to the programmable logic for various test designs. In the design of the test system, the sub-mother board structure design is also adopted. The sub-board can be directly reused to verify the B-board, while the main board can be formed by using the principle A-board design, adding an automatic test interface and interconnection test connections (hereinafter referred to as the power test A-board). During the specific test, put the module in the socket, and connect the power test A board and verification B board. The principle verification system, the verification system and the function test system of the present invention consist of three sets of sub-motherboard-level systems and six boards. Due to the multiplexing design, only four boards need to be designed, which reduces the design workload and difficulty, and improves the efficiency.

Parametric test vectors and parametric test systems need to be designed simultaneously. The parameter test system is implemented on the ATE test bench, and the specific design of the test board is sufficient. The test vector is based on the parameters to be tested of the module. For example, this module uses the vector to test the static parameters of the pins. First, the peripheral test is performed and then the FPGA test is performed. That is, in the SoC chip debugging mode, use the debug interface to control the SoC chip to its The peripheral interface is used to access, and a specific test waveform is given. During the actual measurement, the actual waveform is compared with the test waveform and sampled to perform parameter testing. Afterwards, as in step (1), the dual-configuration design uses the FPGA to configure, and then according to the FPGA test waveform that implements the design, the actual waveform is compared and sampled, and the parameter test is performed.

Claims (7)

1. a kind of SIP module design method based on board-level verification test system, it is characterized in that comprising the following steps: (1) According to preset requirements, select the devices to be integrated and determine the connection relationship between the devices to be integrated, the devices to be integrated include integrated circuit bare cores, MEMS, optoelectronic devices and discrete devices, the integrated circuit bare cores Including: processor, memory, converter and field programmable gate array; (2) Design principle verification PCB board; (3) write driver program, described driver program comprises address decoding program, boot program and header file; (4) Use the PCB board in step (2) and the driver in step (3) to verify the principle of the device to be integrated and the connection relationship between the devices to be integrated selected in step (1). If the principle verification is passed, Then enter step (6), if the principle verification fails, then enter step (5); (5) If the principle verification fails due to hardware reasons, return to step (1) to adjust the devices to be integrated or the connection relationship between the devices to be integrated in step (1); if the principle verification fails to pass due to software reasons, Then return to step (3), rewrite the driver; (6) Carry out the structural design and wiring design of the SIP module; (7) Carry out functional verification to the SIP module designed in step (6), if the functional verification is passed, then enter step (8), otherwise, return to step (1) and redesign; (8) The SIP module passed through functional verification in the production step (7), and the produced SIP module is returned to the chip test, if the chip-back test is passed, then the design process of the SIP module is completed, if the chip-back test fails, then return In step (1), the design of the SIP module is carried out again, and the chip-back test includes a function test and a parameter test of the SIP module. 2. a kind of SIP module design method based on board-level verification test system according to claim 1, is characterized in that: in described step (2), principle verification PCB board; Be specifically: described principle verification PCB board is divided into The mother board and daughter board are connected by multi-pin connectors; only the selected devices to be integrated are placed on the daughter board, and the connection relationship of the devices to be integrated is realized. The physical connection of the board; the motherboard contains components that support the work of the daughter board, and the components that support the work of the daughter board include: power supply and level conversion circuit, power management circuit, clock input circuit, interface drive circuit, selector and FPGA configuration circuit. 3. a kind of SIP module design method based on board-level verification test system according to claim 1, is characterized in that: the address decoding program in the described step (3) is according to each device to be integrated in the step (1) The connection relationship between them corresponds to the start address, address length and data width of each device to be integrated, and then write considering the big and small ends. 4. A kind of SIP module design method based on the board-level verification test system according to claim 1, characterized in that: the structural design method of the SIP module is 2D, 2.5D or 3D. 5. a kind of SIP module design method based on board-level verification test system according to claim 2, is characterized in that: in described step (7), the SIP module designed in step (6) is carried out functional verification, specifically Realized by a function verification system, the function verification system includes a function verification motherboard and a function verification sub-board, and the function verification motherboard and the function verification daughter board are connected by a multi-pin connector; the function verification motherboard multiplexing principle verification The mother board of the PCB board, the functional verification daughter board includes a socket for placing the SIP module and a matching connector for the principle verification PCB board daughter board. 6. a kind of SIP module design method based on board-level verification test system according to claim 5, is characterized in that: described SIP module function test is specifically realized by function test system, and described function test system comprises function test motherboard Connect with the functional test sub-board, the functional test motherboard and the functional test sub-board by using a multi-pin connector; the functional test sub-board multiplexes the function of verifying the sub-board of the PCB board, and the functional test motherboard includes a supporting function test sub-board Working elements, the elements supporting the function test sub-board include: power supply and level conversion circuit, power management circuit, clock input circuit, interface drive circuit, selector and FPGA configuration circuit. 7. a kind of SIP module design method based on board-level verification test system according to claim 2, it is characterized in that: in the described wiring design, the connection relationship multiplexing principle between each device to be integrated is verified in each PCB sub-board. The connection relationship between the devices to be integrated.