CN105262963A - Dark pixel array, replacing control circuit system and method thereof - Google Patents
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Abstract
The invention provides a dark pixel array, a replacing control circuit system and a method thereof. When damaged lines exist in a first dark pixel area, discarding of a whole chip is not required, information of related lines is written in a register according to a testing result, and a system automatically replaces the damaged lines by good lines in a second dark pixel area. A normal calculation operation can be normally performed on a dark current level after replacement. The method of the invention can greatly improve the yield rate of the chip. Furthermore when the chip operates normally and a new damage of the dark pixel occurs in an actual application process, a replaceable good line can be used for restoring the chip when the replaceable good line exists in the second dark pixel area. Therefore the dark pixel array, the replacing control circuit system and the method have advantages of ensuring high accuracy in dark current level calculation, realizing simple operation and easy application of the operation method, and improving a process efficiency.
Description
Technical Field
The invention relates to the field of CMOS image sensors, in particular to a dark pixel array for calculating the current level of dark pixels, a control circuit system for reading and replacing dark pixel rows and a method for replacing the dark pixel rows by using the control circuit system.
Background
In a typical image sensor design, in order to detect the dark current level of the image sensor and correct the dark current level, some dark pixel regions are usually added to the pixel array of the image sensor. The pixels in these dark pixel areas are in circuit with the normal pixels, but are shielded from the light by a metal layer during manufacture. However, the metal layer may not cover some of the dark pixels during the process of manufacturing the dark pixels, causing the dark pixels to operate improperly and become dark pixel dead spots. If the number of bad pixels in a row of dark pixels is more than a certain standard, the dark pixel row becomes a bad dark pixel row.
When dark current level calculation is performed, several rows in the middle of the dark pixel area are usually selected for dark current level calculation. If one or more bad pixel rows are present therein, the calculated dark current level is affected. In response to this situation, the conventional approach is to discard the image sensor chip having the dark and bad pixels. This results in a reduction in chip yield and an increase in manufacturing costs.
Therefore, a solution to the problem of dark pixel dead pixel is needed to improve the yield of the chip and reduce the manufacturing cost.
Disclosure of Invention
In order to overcome the problems, the invention adds the backup pixel area in the dark pixel area, and when the dark pixel row for dark current level calculation is expected to have bad rows, the good dark pixel row in the backup dark pixel area is used for replacing the bad rows so as to ensure the accuracy of dark current level calculation.
In order to achieve the above object, the present invention provides a dark pixel array for dark pixel current level calculation, which is a dark pixel array of M rows × N columns; which includes a first dark pixel region and a second dark pixel region;
the first dark pixel area is a dark pixel array with L rows and P columns, and all pixels in the first dark pixel area are used for calculating the dark current level under the condition that no bad row exists;
the second dark pixel area is a dark pixel array with K rows multiplied by P columns and is used as a backup pixel area of the first dark pixel area, and when the first dark pixel area has a bad row, the first dark pixel area is replaced by a corresponding good row in the second dark pixel area; the second dark pixel area is arranged adjacent to the first dark pixel area; wherein, K is more than or equal to 1 and less than or equal to L and less than M, and P is less than N.
Preferably, the dark pixel array further comprises a peripheral dark pixel region surrounding the first and second dark pixel regions; the peripheral dark pixel area comprises J rows and P columns, which are not used for calculating the dark current level, but used for sacrificing the dark pixel area when the first dark pixel area and the second dark pixel area are prepared, so that light leakage in the first dark pixel area and the second dark pixel area is avoided; wherein J is more than L and less than M, and P is more than N.
In order to achieve the above object, the present invention further provides a control circuit system for performing a dark pixel row read replacement operation using the above dark pixel array, comprising: the device comprises a memory, a dark pixel row counter, a first dark pixel area row good-bad mark register, a shift register, a second dark pixel area row good-bad mark register, a temporary storage register, a row address generator and a read operation controller; wherein
A memory for storing quality flag data of a dark pixel row of the first dark pixel area of the dark pixel area array and quality flag data of a dark pixel row of the second dark pixel area of the dark pixel area array; the memory can also store data when not powered on, and the quality mark data on the memory is loaded into the corresponding register by the system when powered on;
a dark pixel row counter; when the collection of each frame of image is started, the value of the dark pixel row counter is reset to 0; during image acquisition, after the reading operation of each row is completed by the reading operation controller, adding 1 to the value of the dark pixel row counter, wherein the maximum value of the dark pixel row counter is the row number of all the dark pixel rows in the first dark pixel area; when the value of the dark pixel row counter reaches the maximum value, the dark pixel row counter sends a stop detection signal to a row address generator;
the first dark pixel area line good-bad mark register has a common L bit value, and the 0 th bit value to the L-1 th bit value respectively represent the good-bad mark data of the corresponding dark pixel line in the first dark pixel area; when the system is powered on, the good-and-bad mark data of the dark pixel row of the first dark pixel area stored in the memory is loaded into the first dark pixel area row good-and-bad mark register by the system;
the shift register loads each bit value in the first dark pixel area line good-bad mark register into the shift register by a system when each dark current level calculation is started; when the dark pixel row counter finishes counting for each row, the shift register directionally moves once; the 0 th bit of the shift register represents the quality of the current line;
the second dark pixel area line good-bad mark register has a K bit value, and the 0 th bit value to the K-1 th bit value respectively correspond to the good-bad mark data of each dark pixel line in the second dark pixel area; when the system is powered on, the good-and-bad mark data of the dark pixel row of the second dark pixel area stored in the memory is loaded into the good-and-bad mark register of the row of the second dark pixel area by the system;
a temporary storage register, wherein the bit value in the good-bad mark register of the second dark pixel area line is loaded into the temporary storage register when each dark current level calculation is started;
the row address generator detects a 0 th bit value in the shift register to judge whether the current row of the first dark pixel area is a good row or a bad row; when the current row is a good row, the row address generator sends the row address of the current row to a read operation controller, and the read operation controller performs read operation on the row address of the current row; when the current row is a bad row, the row address generator detects the position in the temporary storage register from the 0 th bit to the K-1 th bit, when a first good row is detected, the row address of the good row in the second dark pixel area is calculated according to the bit address corresponding to the good row, the row address of the good row replaces the row address of the current row, and meanwhile, the row address of the good row is sent to a read operation controller to read the good row; after the replacement is completed, the line address generator inverts the bit value of the good line which is used for replacement and corresponds to the temporary storage register; when the value of the dark pixel row counter reaches the maximum value, the row address generator stops detection after receiving the detection stopping signal sent by the dark pixel row counter;
and the read operation controller completes the read operation of the corresponding row according to the row address sent by the row address generator.
Preferably, in the bit values in the line good and bad flag register of the first dark pixel area, a good line is represented by 0, and a bad line is represented by 1; or 1 for good rows and 0 for bad rows.
Preferably, in the bit values in the second dark pixel area line good-bad flag register, 0 is used for representing a good line, and 1 is used for representing a bad line; or 1 for good rows and 0 for bad rows.
Preferably, the dark pixel array further comprises a peripheral dark pixel region surrounding the first and second dark pixel regions; the peripheral dark pixel area comprises J rows and P columns, which are not used for calculating the dark current level, but used for sacrificing the dark pixel area when the first dark pixel area and the second dark pixel area are prepared, so that light leakage in the first dark pixel area and the second dark pixel area is avoided; wherein J is more than K and less than or equal to L and less than M, and P is less than N.
In order to achieve the above object, the present invention further provides a dark pixel row replacement method using the above control circuit system for the dark pixel row read replacement operation and the above dark pixel array, the dark pixel row replacement method including the steps of:
step 01: detecting dark pixel rows in the first dark pixel area and the second dark pixel area of the dark pixel area array, and writing good-bad mark data of each row into a memory;
step 02: when the system is powered on, the quality mark data in the memory is loaded into the corresponding register by the system; loading the good-and-bad mark data of the dark pixel row of the first dark pixel area into the first dark pixel area row good-and-bad mark register, and loading the good-and-bad mark data of the dark pixel row of the second dark pixel area into the second dark pixel area row good-and-bad mark register;
step 03: at the beginning of each dark current calculation, the value of the dark pixel row counter is reset to 0; then, the dark pixel row counter loads each bit value in the first dark pixel area row good and bad flag register into the shift register by a system, and loads the bit value in the second dark pixel area row good and bad flag register into the temporary storage register;
step 04: the row address generator detects a 0 th bit value in the shift register to judge whether the current row of the first dark pixel area is a good row or a bad row;
step 05: when the current row is a good row, the row address generator sends the row address of the current row to the read operation controller, and the read operation controller performs read operation on the row address of the current row;
when a current row is bad, the row address generator detects the position in the temporary storage register from the 0 th bit to the K-1 th bit, when a first good row is detected, the row address of the good row in the second dark pixel area is calculated according to the bit address corresponding to the good row, the row address of the good row replaces the row address of the current row, meanwhile, the row address of the good row is sent to the read operation controller, and the read operation controller performs read operation on the good row; after the replacement is completed, the line address generator inverts the bit value of the good line which is used for replacement and corresponds to the temporary storage register;
step 06: starting to perform the operation of the next row, and adding 1 to the value of the dark pixel row counter;
step 07: repeating the steps 04-06 until the value of the dark pixel row counter equals the row number values of all dark pixel rows in the first dark pixel area, the dark pixel row counter sending a stop detection signal to the row address generator;
step 08: and the row address generator stops detection after receiving the detection stopping signal sent by the dark pixel row counter.
Preferably, the dark pixel array further comprises a peripheral dark pixel region surrounding the first and second dark pixel regions; the peripheral dark pixel area comprises J rows and P columns, which are not used for calculating the dark current level, but used for sacrificing the dark pixel area when the first dark pixel area and the second dark pixel area are prepared, so that light leakage in the first dark pixel area and the second dark pixel area is avoided; wherein J is more than K and less than or equal to L and less than M, and P is less than N.
Preferably, in the bit values in the line good and bad flag register of the first dark pixel area, a good line is represented by 0, and a bad line is represented by 1; or 1 for good rows and 0 for bad rows.
Preferably, in the bit values in the second dark pixel area line good-bad flag register, 0 is used for representing a good line, and 1 is used for representing a bad line; or 1 for good rows and 0 for bad rows.
According to the dark pixel array, the replacement control circuit system and the replacement control method, when a bad row exists in the first dark pixel area, the whole chip does not need to be abandoned, only the information of the relevant row needs to be written into the register according to the test result, and the system automatically replaces the bad row with the good row in the second dark pixel area; the replaced dark current level can be normally calculated. The method can greatly improve the yield of the chip; furthermore, when the chip works normally and the dark pixel is damaged newly in the practical application process, if a replaceable good line exists in the second dark pixel area, the chip can be repaired; therefore, the method not only ensures the accuracy of dark current level calculation, but also is simple and easy to implement, and improves the process efficiency.
Drawings
FIG. 1 is a schematic diagram of a dark pixel array according to a preferred embodiment of the present invention
FIG. 2 is a block diagram of the control circuitry for the dark pixel row read replacement operation according to a preferred embodiment of the present invention
FIG. 3 is a flow chart of a dark pixel row replacement method according to a preferred embodiment of the invention
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The dark pixel array, the control circuitry for the dark pixel row read replacement operation, and the dark pixel row replacement method of the present invention are described in further detail below with reference to fig. 1-3 and the specific embodiments. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
Referring to fig. 1, the dark pixel array for dark pixel current level calculation of the present embodiment is a dark pixel array with M rows × N columns; it includes:
a first dark pixel region 101, which is an L row × P column dark pixel array; in the case where there is no bad row, all pixels in the first dark pixel region 101 are used for the calculation of the dark current level;
a second dark pixel area 102, which is a dark pixel array of K rows × P columns, as a backup pixel area of the first dark pixel area 101; when the first dark pixel area 101 has a bad row, replacing the bad row with a corresponding good row in the second dark pixel area 102; the second dark pixel region 102 is disposed adjacent to the first dark pixel region 101; wherein, L is more than or equal to K and less than M, and P is less than N; when the number of dark pixel lines of the second dark pixel area 102 is less than the number of dark pixel lines of the first dark pixel area 101, the number of good lines of the second dark pixel area 102 is required to be greater than or equal to the number of bad lines in the first dark pixel area 101, and therefore, K is required to be greater than or equal to the number of bad lines that may occur in the first dark pixel area 101, if the number of bad lines that are expected to occur in the first dark pixel area 101 is defined as Q lines, K is required to be greater than or equal to Q, but K has a value of at least 1 regardless of whether the number of bad lines Q is 0, so that when the value of Q is greater than or equal to 1, Q is greater than or equal to K and less than L; when the Q value is equal to 0, K is more than or equal to 1 and less than or equal to L and less than M. It should be noted that, in general, the number of bad rows that may occur in the dark pixel region is usually related to the process, and is determined by the manufacturing process and is a statistical empirical value.
In this embodiment, the dark pixel array may further include a peripheral dark pixel region 103, where the peripheral dark pixel region 103 surrounds the first dark pixel region 101 and the second dark pixel region 102; the peripheral dark pixel region 103 includes J rows and P columns, which are not used for calculation of the dark current level, but are used for sacrificial dark pixel regions when the first dark pixel region 101 and the second dark pixel region 102 are prepared, preventing light leakage in the first dark pixel region 101 and the second dark pixel region 102; wherein J is more than L and less than M, and P is more than N; this is because, in general, when a dark pixel array is prepared, dark pixels in an area at the edge of the dark pixel array fail or deteriorate due to manufacturing or light leakage and cannot be used to calculate a dark current level, and therefore, in order to prevent bad lines from occurring at the edges of the first and second dark pixel areas 101 and 102 and to increase the good line ratio of the first and second dark pixel areas 101 and 102 as much as possible, peripheral dark pixel areas 103 are provided at the peripheries of the first and second dark pixel areas 101 and 102, and thus may become "sacrificial dark pixel areas".
Referring to fig. 2, in the present embodiment, the control circuit system for performing the dark pixel row reading replacement operation by using the dark pixel array includes the following components:
a memory 201 for storing quality flag data of a dark pixel row of a first dark pixel area of the dark pixel area array and quality flag data of a dark pixel row of a second dark pixel area of the dark pixel area array; the memory can also store data when not powered on, and the quality mark data on the memory is loaded into the corresponding register by the system when powered on;
a dark pixel row counter 204; at the beginning of each frame of image acquisition, the value of the dark pixel line counter 204 is reset to 0; during image acquisition, after the read operation controller 208 finishes the read operation of each row, the value of the dark pixel row counter 204 is added with 1, and the maximum value of the dark pixel row counter 204 is the row number of all dark pixel rows in the first dark pixel area; when the value of the dark pixel row counter 204 reaches the maximum value, the dark pixel row counter 204 sends a stop detection signal to the row address generator 207;
the first dark pixel area line good-bad flag register 202 has a total L bit value, and the bit values from 0 th to L-1 th respectively represent the good-bad flag data of each dark pixel line in the corresponding first dark pixel area 101, for example, in the bit values in the first dark pixel area line good-bad flag register, 0 represents a good line, and 1 represents a bad line; or 1 for good rows, 0 for bad rows, etc.; when the system is powered on, the good-and-bad flag data of the dark pixel row of the first dark pixel area 101 stored in the memory 201 is loaded into the first dark pixel area row good-and-bad flag register 202 by the system;
a shift register 205, for loading each bit value in the first dark pixel area line good-bad flag register 202 into the shift register 205 from the system at the beginning of each dark current level calculation; when the dark pixel row counter 204 finishes counting one row each time, the shift register 205 is directionally moved once; bit 0 of the shift register 205 characterizes how good the current row is;
the second dark pixel area line good-bad flag register 203 has a total K bit value, and the bit values from 0 th to K-1 th correspond to the good-bad flag data of each dark pixel line in the second dark pixel area 102, for example, in the bit values in the second dark pixel area line good-bad flag register, 0 is used to represent a good line, and 1 is used to represent a bad line; or 1 for good rows, 0 for bad rows, etc.; when the system is powered on, the good-and-bad flag data of the dark pixel row of the second dark pixel area stored in the memory 201 is loaded into the second dark pixel area row good-and-bad flag register 203 by the system;
a temporary storage register 206 for loading the bit value in the second dark pixel area line good-bad flag register 203 into the temporary storage register 206 when each dark current level calculation is started; when the replacement is completed, the temporary storage register 206 receives the negation operation control signal sent by the row address generator 207, and the temporary storage register 206 negates the bit value of the good row corresponding to the replacement;
a row address generator 207 for detecting the 0 th bit value in the shift register 205 to determine whether the current row of the first dark pixel region is a good row or a bad row; when the current row is a good row, the row address generator 207 sends the row address of the current row to the read operation controller 208, and the read operation controller 208 performs read operation on the row address of the current row; when the current row is a bad row, the row address generator 207 detects the position in the temporary storage register 206, from the 0 th bit to the K-1 th bit, when the first good row is detected, the row address of the good row in the second dark pixel area 102 is calculated according to the bit address corresponding to the good row, the row address of the good row replaces the row address of the current row, and meanwhile, the row address of the good row is sent to the read operation controller 208 to perform read operation on the good row; after the replacement is completed, the row address generator 207 sends an inversion operation control signal to the temporary storage register 206, and the temporary storage register 206 inverts the bit value of the good row corresponding to the replacement; when the value of the dark pixel row counter 204 reaches its set maximum value (the row number of all dark pixel rows of the first dark pixel region), the row address generator 207 stops the detection after receiving the stop detection signal sent by the dark pixel row counter 204;
the read operation controller 208 completes the read operation of the corresponding row according to the row address sent by the row address generator 207. In this embodiment, the read operation controller 208 has a row address decoder, and can decode the row address sent by the row address generator to obtain a format that can be read by the read operation controller.
Referring to fig. 3, in the present embodiment, the method for replacing the dark pixel row by the control circuit system for the dark pixel row reading replacement operation includes the following steps:
step 01: detecting dark pixel rows in a first dark pixel area and a second dark pixel area of the dark pixel area array, and writing the good-bad mark data of each row into a memory;
step 02: when the system is powered on, the quality mark data in the memory is loaded into the corresponding register by the system;
specifically, in this embodiment, the good-and-bad flag data of the dark pixel row of the first dark pixel area is loaded into the first dark pixel area row good-and-bad flag register, and the good-and-bad flag data of the dark pixel row of the second dark pixel area is loaded into the second dark pixel area row good-and-bad flag register; the first dark pixel area line good-bad mark register has a common L bit value, and the bit values from 0 th to L-1 th respectively represent the good-bad mark data of the corresponding dark pixel line in the first dark pixel area, for example, in the bit values in the first dark pixel area line good-bad mark register, 0 represents a good line, and 1 represents a bad line; or 1 for good rows, 0 for bad rows, etc.; the second dark pixel area line good-bad mark register has a K bit value, the bit values from 0 th to K-1 th correspond to the good-bad mark data of each dark pixel line in the second dark pixel area, for example, in the bit values in the second dark pixel area line good-bad mark register, 0 is used for representing a good line, and 1 is used for representing a bad line; or 1 for good rows, 0 for bad rows, etc.;
step 03: at the beginning of each dark current calculation, the value of the dark pixel row counter is reset to 0; loading each bit value in the line good and bad mark register of the first dark pixel area into a shift register by a system, and loading the bit value in the line good and bad mark register of the second dark pixel area into a temporary storage register;
step 04: the row address generator detects a 0 th bit value in the shift register to judge whether the current row of the first dark pixel area is a good row or a bad row;
specifically, the 0 th bit value in the shift register represents the quality of the dark pixel row in the first dark pixel area to be read currently;
step 05: when the current row is good, the row address generator sends the row address of the current row to the read operation controller, and the read operation controller performs read operation on the row address of the current row;
when the current line is a bad line, the line address generator detects the position in the temporary storage register from the 0 th bit to the K-1 th bit, when the first good line is detected, the line address of the good line in the second dark pixel area is calculated according to the bit address corresponding to the good line, the line address of the good line is replaced by the line address of the current line, meanwhile, the line address of the good line is sent to the read operation controller, and the read operation controller performs read operation on the good line; after the replacement is finished, the row address generator inverts the bit value of the good row which is used for replacement and corresponds to the temporary storage register;
step 06: starting to operate the next row, and adding 1 to the value of the dark pixel row counter;
step 07: repeating the steps 04-06 until the value of the dark pixel row counter is equal to the row number values of all the dark pixel rows in the first dark pixel area, the dark pixel row counter sending a stop detection signal to the row address generator;
specifically, the steps 04-06 are repeated until the value of the dark pixel row counter is equal to L, and all L dark pixel rows in the first dark pixel area are executed.
Step 08: and the row address generator stops detection after receiving the detection stopping signal sent by the dark pixel row counter.
In summary, according to the dark pixel array, the replacement control circuit system and the method of the present invention, when a bad row exists in the first dark pixel area, the whole chip does not need to be discarded, only the information of the relevant row needs to be written into the register according to the test result, and the system automatically replaces the bad row with the good row in the second dark pixel area; the replaced dark current level can be normally calculated. The method can greatly improve the yield of the chip; furthermore, when the chip works normally and the dark pixel is damaged newly in the practical application process, if a replaceable good line exists in the second dark pixel area, the chip can be repaired; therefore, the method not only ensures the accuracy of dark current level calculation, but also is simple and easy to implement, and improves the process efficiency.
Although the present invention has been described with reference to preferred embodiments, which are illustrated for the purpose of illustration only and not for the purpose of limitation, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A dark pixel array for dark pixel current level calculation is an M row by N column dark pixel array; the pixel structure is characterized by comprising a first dark pixel area and a second dark pixel area;
the first dark pixel area is a dark pixel array with L rows and P columns, and all pixels in the first dark pixel area are used for calculating the dark current level under the condition that no bad row exists;
the second dark pixel area is a dark pixel array with K rows multiplied by P columns and is used as a backup pixel area of the first dark pixel area, and when the first dark pixel area has a bad row, the first dark pixel area is replaced by a corresponding good row in the second dark pixel area; the second dark pixel area is arranged adjacent to the first dark pixel area; wherein, K is more than or equal to 1 and less than or equal to L and less than M, and P is less than N.
2. The dark pixel array for dark pixel current level calculation of claim 1, further comprising a peripheral dark pixel region enclosed outside the first and second dark pixel regions; the peripheral dark pixel area comprises J rows and P columns, which are not used for calculating the dark current level, but used for sacrificing the dark pixel area when the first dark pixel area and the second dark pixel area are prepared, so that light leakage in the first dark pixel area and the second dark pixel area is avoided; wherein J is more than L and less than M, and P is more than N.
3. Control circuitry for performing a dark pixel row read replacement operation with the dark pixel array of claim 1, comprising: the device comprises a memory, a dark pixel row counter, a first dark pixel area row good-bad mark register, a shift register, a second dark pixel area row good-bad mark register, a temporary storage register, a row address generator and a read operation controller; wherein,
a memory for storing quality flag data of a dark pixel row of the first dark pixel area of the dark pixel area array and quality flag data of a dark pixel row of the second dark pixel area of the dark pixel area array; the memory can also store data when not powered on, and the quality mark data on the memory is loaded into the corresponding register by the system when powered on;
a dark pixel line counter whose value is reset to 0 at the start of each frame of image acquisition; during image acquisition, after the reading operation of each row is completed by the reading operation controller, adding 1 to the value of the dark pixel row counter, wherein the maximum value of the dark pixel row counter is the row number of all the dark pixel rows in the first dark pixel area; when the value of the dark pixel row counter reaches the maximum value, the dark pixel row counter sends a stop detection signal to a row address generator;
the first dark pixel area line good-bad mark register has a common L bit value, and the 0 th bit value to the L-1 th bit value respectively represent the good-bad mark data of the corresponding dark pixel line in the first dark pixel area; when the system is powered on, the good-and-bad mark data of the dark pixel row of the first dark pixel area stored in the memory is loaded into the first dark pixel area row good-and-bad mark register by the system;
the shift register loads each bit value in the first dark pixel area line good-bad mark register into the shift register by a system when each dark current level calculation is started; when the dark pixel row counter finishes counting for each row, the shift register directionally moves once; the 0 th bit of the shift register represents the quality of the current line;
the second dark pixel area line good-bad mark register has a K bit value, and the 0 th bit value to the K-1 th bit value respectively correspond to the good-bad mark data of each dark pixel line in the second dark pixel area; when the system is powered on, the good-and-bad mark data of the dark pixel row of the second dark pixel area stored in the memory is loaded into the good-and-bad mark register of the row of the second dark pixel area by the system;
a temporary storage register, wherein the bit value in the good-bad mark register of the second dark pixel area line is loaded into the temporary storage register when each dark current level calculation is started;
the row address generator detects a 0 th bit value in the shift register to judge whether the current row of the first dark pixel area is a good row or a bad row; when the current row is a good row, the row address generator sends the row address of the current row to a read operation controller, and the read operation controller performs read operation on the row address of the current row; when the current row is a bad row, the row address generator detects the position in the temporary storage register from the 0 th bit to the K-1 th bit, when a first good row is detected, the row address of the good row in the second dark pixel area is calculated according to the bit address corresponding to the good row, the row address of the good row replaces the row address of the current row, and meanwhile, the row address of the good row is sent to a read operation controller to read the good row; after the replacement is completed, the line address generator inverts the bit value of the good line which is used for replacement and corresponds to the temporary storage register; when the value of the dark pixel row counter reaches the maximum value, the row address generator stops detection after receiving the detection stopping signal sent by the dark pixel row counter;
and the read operation controller completes the read operation of the corresponding row according to the row address sent by the row address generator.
4. The control circuitry for a dark pixel row read replace operation according to claim 3, wherein of said bit values in said first dark pixel area row good-bad flag register, a good row is represented by 0 and a bad row is represented by 1; or 1 for good rows and 0 for bad rows.
5. The control circuitry for a dark pixel row read replace operation according to claim 3, wherein said bit values in said second dark pixel region row good-bad flag register indicate a good row by 0 and a bad row by 1; or 1 for good rows and 0 for bad rows.
6. The control circuitry for a dark pixel row read replace operation according to claim 3, wherein said dark pixel array further comprises a peripheral dark pixel region enclosed outside said first dark pixel region and said second dark pixel region; the peripheral dark pixel area comprises J rows and P columns, which are not used for calculating the dark current level, but used for sacrificing the dark pixel area when the first dark pixel area and the second dark pixel area are prepared, so that light leakage in the first dark pixel area and the second dark pixel area is avoided; wherein J is more than K and less than or equal to L and less than M, and P is less than N.
7. A dark pixel row replacement method using the control circuitry for the dark pixel row read replacement operation of claim 3 and the dark pixel array of claim 1, the dark pixel row replacement method comprising the steps of:
step 01: detecting dark pixel rows in the first dark pixel area and the second dark pixel area of the dark pixel area array, and writing good-bad mark data of each row into a memory;
step 02: when the system is powered on, the quality mark data in the memory is loaded into the corresponding register by the system; loading the good-and-bad mark data of the dark pixel row of the first dark pixel area into the first dark pixel area row good-and-bad mark register, and loading the good-and-bad mark data of the dark pixel row of the second dark pixel area into the second dark pixel area row good-and-bad mark register;
step 03: at the beginning of each dark current calculation, the value of the dark pixel row counter is reset to 0; then, the dark pixel row counter loads each bit value in the first dark pixel area row good and bad flag register into the shift register by a system, and loads the bit value in the second dark pixel area row good and bad flag register into the temporary storage register;
step 04: the row address generator detects a 0 th bit value in the shift register to judge whether the current row of the first dark pixel area is a good row or a bad row;
step 05: when the current row is a good row, the row address generator sends the row address of the current row to the read operation controller, and the read operation controller performs read operation on the row address of the current row;
when a current row is bad, the row address generator detects the position in the temporary storage register from the 0 th bit to the K-1 th bit, when a first good row is detected, the row address of the good row in the second dark pixel area is calculated according to the bit address corresponding to the good row, the row address of the good row replaces the row address of the current row, meanwhile, the row address of the good row is sent to the read operation controller, and the read operation controller performs read operation on the good row; after the replacement is completed, the line address generator inverts the bit value of the good line which is used for replacement and corresponds to the temporary storage register;
step 06: starting to perform the operation of the next row, and adding 1 to the value of the dark pixel row counter;
step 07: repeating the steps 04-06 until the value of the dark pixel row counter equals the row number values of all dark pixel rows in the first dark pixel area, the dark pixel row counter sending a stop detection signal to the row address generator;
step 08: and the row address generator stops detection after receiving the detection stopping signal sent by the dark pixel row counter.
8. The dark pixel row replacement method of claim 7, wherein the dark pixel array further comprises a peripheral dark pixel region surrounding the first and second dark pixel regions; the peripheral dark pixel area comprises J rows and P columns, which are not used for calculating the dark current level, but used for sacrificing the dark pixel area when the first dark pixel area and the second dark pixel area are prepared, so that light leakage in the first dark pixel area and the second dark pixel area is avoided; wherein J is more than K and less than or equal to L and less than M, and P is less than N.
9. The dark pixel row replacement method according to claim 7, wherein, among the bit values in the first dark pixel area row good-bad flag register, a good row is represented by 0, and a bad row is represented by 1; or 1 for good rows and 0 for bad rows.
10. The dark pixel row replacement method according to claim 7, wherein, among the bit values in the second dark pixel region row good-bad flag register, a good row is represented by 0, and a bad row is represented by 1; or 1 for good rows and 0 for bad rows.
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